1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 #if defined(__FreeBSD__) 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/etherdevice.h> 21 #include <linux/rcupdate.h> 22 #include <linux/lockdep.h> 23 #include <linux/seq_file.h> 24 #endif 25 26 #include "util.h" 27 28 #define RTW_MAX_MAC_ID_NUM 32 29 #define RTW_MAX_SEC_CAM_NUM 32 30 #define MAX_PG_CAM_BACKUP_NUM 8 31 32 #define RTW_SCAN_MAX_SSIDS 4 33 #define RTW_SCAN_MAX_IE_LEN 128 34 35 #define RTW_MAX_PATTERN_NUM 12 36 #define RTW_MAX_PATTERN_MASK_SIZE 16 37 #define RTW_MAX_PATTERN_SIZE 128 38 39 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 40 41 #define RFREG_MASK 0xfffff 42 #define INV_RF_DATA 0xffffffff 43 #define TX_PAGE_SIZE_SHIFT 7 44 45 #define RTW_CHANNEL_WIDTH_MAX 3 46 #define RTW_RF_PATH_MAX 4 47 #define HW_FEATURE_LEN 13 48 49 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 50 51 extern bool rtw_bf_support; 52 extern bool rtw_disable_lps_deep_mode; 53 extern unsigned int rtw_debug_mask; 54 extern bool rtw_edcca_enabled; 55 extern const struct ieee80211_ops rtw_ops; 56 57 #define RTW_MAX_CHANNEL_NUM_2G 14 58 #define RTW_MAX_CHANNEL_NUM_5G 49 59 60 struct rtw_dev; 61 62 enum rtw_hci_type { 63 RTW_HCI_TYPE_PCIE, 64 RTW_HCI_TYPE_USB, 65 RTW_HCI_TYPE_SDIO, 66 67 RTW_HCI_TYPE_UNDEFINE, 68 }; 69 70 struct rtw_hci { 71 struct rtw_hci_ops *ops; 72 enum rtw_hci_type type; 73 74 u32 rpwm_addr; 75 u32 cpwm_addr; 76 77 u8 bulkout_num; 78 }; 79 80 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 81 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 82 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 83 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 84 85 #define IS_CH_5G_BAND_MID(channel) \ 86 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 87 88 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 89 #define IS_CH_5G_BAND(channel) \ 90 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 91 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 92 93 enum rtw_supported_band { 94 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 95 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 96 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 97 }; 98 99 /* now, support upto 80M bw */ 100 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 101 102 enum rtw_bandwidth { 103 RTW_CHANNEL_WIDTH_20 = 0, 104 RTW_CHANNEL_WIDTH_40 = 1, 105 RTW_CHANNEL_WIDTH_80 = 2, 106 RTW_CHANNEL_WIDTH_160 = 3, 107 RTW_CHANNEL_WIDTH_80_80 = 4, 108 RTW_CHANNEL_WIDTH_5 = 5, 109 RTW_CHANNEL_WIDTH_10 = 6, 110 }; 111 112 enum rtw_sc_offset { 113 RTW_SC_DONT_CARE = 0, 114 RTW_SC_20_UPPER = 1, 115 RTW_SC_20_LOWER = 2, 116 RTW_SC_20_UPMOST = 3, 117 RTW_SC_20_LOWEST = 4, 118 RTW_SC_40_UPPER = 9, 119 RTW_SC_40_LOWER = 10, 120 }; 121 122 enum rtw_net_type { 123 RTW_NET_NO_LINK = 0, 124 RTW_NET_AD_HOC = 1, 125 RTW_NET_MGD_LINKED = 2, 126 RTW_NET_AP_MODE = 3, 127 }; 128 129 enum rtw_rf_type { 130 RF_1T1R = 0, 131 RF_1T2R = 1, 132 RF_2T2R = 2, 133 RF_2T3R = 3, 134 RF_2T4R = 4, 135 RF_3T3R = 5, 136 RF_3T4R = 6, 137 RF_4T4R = 7, 138 RF_TYPE_MAX, 139 }; 140 141 enum rtw_rf_path { 142 RF_PATH_A = 0, 143 RF_PATH_B = 1, 144 RF_PATH_C = 2, 145 RF_PATH_D = 3, 146 }; 147 148 enum rtw_bb_path { 149 BB_PATH_A = BIT(0), 150 BB_PATH_B = BIT(1), 151 BB_PATH_C = BIT(2), 152 BB_PATH_D = BIT(3), 153 154 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 155 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 156 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 157 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 158 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 159 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 160 161 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 162 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 163 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 164 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 165 166 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 167 }; 168 169 enum rtw_rate_section { 170 RTW_RATE_SECTION_CCK = 0, 171 RTW_RATE_SECTION_OFDM, 172 RTW_RATE_SECTION_HT_1S, 173 RTW_RATE_SECTION_HT_2S, 174 RTW_RATE_SECTION_VHT_1S, 175 RTW_RATE_SECTION_VHT_2S, 176 177 /* keep last */ 178 RTW_RATE_SECTION_MAX, 179 }; 180 181 enum rtw_wireless_set { 182 WIRELESS_CCK = 0x00000001, 183 WIRELESS_OFDM = 0x00000002, 184 WIRELESS_HT = 0x00000004, 185 WIRELESS_VHT = 0x00000008, 186 }; 187 188 #define HT_STBC_EN BIT(0) 189 #define VHT_STBC_EN BIT(1) 190 #define HT_LDPC_EN BIT(0) 191 #define VHT_LDPC_EN BIT(1) 192 193 enum rtw_chip_type { 194 RTW_CHIP_TYPE_8822B, 195 RTW_CHIP_TYPE_8822C, 196 RTW_CHIP_TYPE_8723D, 197 RTW_CHIP_TYPE_8821C, 198 }; 199 200 enum rtw_tx_queue_type { 201 /* the order of AC queues matters */ 202 RTW_TX_QUEUE_BK = 0x0, 203 RTW_TX_QUEUE_BE = 0x1, 204 RTW_TX_QUEUE_VI = 0x2, 205 RTW_TX_QUEUE_VO = 0x3, 206 207 RTW_TX_QUEUE_BCN = 0x4, 208 RTW_TX_QUEUE_MGMT = 0x5, 209 RTW_TX_QUEUE_HI0 = 0x6, 210 RTW_TX_QUEUE_H2C = 0x7, 211 /* keep it last */ 212 RTK_MAX_TX_QUEUE_NUM 213 }; 214 215 enum rtw_rx_queue_type { 216 RTW_RX_QUEUE_MPDU = 0x0, 217 RTW_RX_QUEUE_C2H = 0x1, 218 /* keep it last */ 219 RTK_MAX_RX_QUEUE_NUM 220 }; 221 222 enum rtw_fw_type { 223 RTW_NORMAL_FW = 0x0, 224 RTW_WOWLAN_FW = 0x1, 225 }; 226 227 enum rtw_rate_index { 228 RTW_RATEID_BGN_40M_2SS = 0, 229 RTW_RATEID_BGN_40M_1SS = 1, 230 RTW_RATEID_BGN_20M_2SS = 2, 231 RTW_RATEID_BGN_20M_1SS = 3, 232 RTW_RATEID_GN_N2SS = 4, 233 RTW_RATEID_GN_N1SS = 5, 234 RTW_RATEID_BG = 6, 235 RTW_RATEID_G = 7, 236 RTW_RATEID_B_20M = 8, 237 RTW_RATEID_ARFR0_AC_2SS = 9, 238 RTW_RATEID_ARFR1_AC_1SS = 10, 239 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 240 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 241 RTW_RATEID_ARFR4_AC_3SS = 13, 242 RTW_RATEID_ARFR5_N_3SS = 14, 243 RTW_RATEID_ARFR7_N_4SS = 15, 244 RTW_RATEID_ARFR6_AC_4SS = 16 245 }; 246 247 enum rtw_trx_desc_rate { 248 DESC_RATE1M = 0x00, 249 DESC_RATE2M = 0x01, 250 DESC_RATE5_5M = 0x02, 251 DESC_RATE11M = 0x03, 252 253 DESC_RATE6M = 0x04, 254 DESC_RATE9M = 0x05, 255 DESC_RATE12M = 0x06, 256 DESC_RATE18M = 0x07, 257 DESC_RATE24M = 0x08, 258 DESC_RATE36M = 0x09, 259 DESC_RATE48M = 0x0a, 260 DESC_RATE54M = 0x0b, 261 262 DESC_RATEMCS0 = 0x0c, 263 DESC_RATEMCS1 = 0x0d, 264 DESC_RATEMCS2 = 0x0e, 265 DESC_RATEMCS3 = 0x0f, 266 DESC_RATEMCS4 = 0x10, 267 DESC_RATEMCS5 = 0x11, 268 DESC_RATEMCS6 = 0x12, 269 DESC_RATEMCS7 = 0x13, 270 DESC_RATEMCS8 = 0x14, 271 DESC_RATEMCS9 = 0x15, 272 DESC_RATEMCS10 = 0x16, 273 DESC_RATEMCS11 = 0x17, 274 DESC_RATEMCS12 = 0x18, 275 DESC_RATEMCS13 = 0x19, 276 DESC_RATEMCS14 = 0x1a, 277 DESC_RATEMCS15 = 0x1b, 278 DESC_RATEMCS16 = 0x1c, 279 DESC_RATEMCS17 = 0x1d, 280 DESC_RATEMCS18 = 0x1e, 281 DESC_RATEMCS19 = 0x1f, 282 DESC_RATEMCS20 = 0x20, 283 DESC_RATEMCS21 = 0x21, 284 DESC_RATEMCS22 = 0x22, 285 DESC_RATEMCS23 = 0x23, 286 DESC_RATEMCS24 = 0x24, 287 DESC_RATEMCS25 = 0x25, 288 DESC_RATEMCS26 = 0x26, 289 DESC_RATEMCS27 = 0x27, 290 DESC_RATEMCS28 = 0x28, 291 DESC_RATEMCS29 = 0x29, 292 DESC_RATEMCS30 = 0x2a, 293 DESC_RATEMCS31 = 0x2b, 294 295 DESC_RATEVHT1SS_MCS0 = 0x2c, 296 DESC_RATEVHT1SS_MCS1 = 0x2d, 297 DESC_RATEVHT1SS_MCS2 = 0x2e, 298 DESC_RATEVHT1SS_MCS3 = 0x2f, 299 DESC_RATEVHT1SS_MCS4 = 0x30, 300 DESC_RATEVHT1SS_MCS5 = 0x31, 301 DESC_RATEVHT1SS_MCS6 = 0x32, 302 DESC_RATEVHT1SS_MCS7 = 0x33, 303 DESC_RATEVHT1SS_MCS8 = 0x34, 304 DESC_RATEVHT1SS_MCS9 = 0x35, 305 306 DESC_RATEVHT2SS_MCS0 = 0x36, 307 DESC_RATEVHT2SS_MCS1 = 0x37, 308 DESC_RATEVHT2SS_MCS2 = 0x38, 309 DESC_RATEVHT2SS_MCS3 = 0x39, 310 DESC_RATEVHT2SS_MCS4 = 0x3a, 311 DESC_RATEVHT2SS_MCS5 = 0x3b, 312 DESC_RATEVHT2SS_MCS6 = 0x3c, 313 DESC_RATEVHT2SS_MCS7 = 0x3d, 314 DESC_RATEVHT2SS_MCS8 = 0x3e, 315 DESC_RATEVHT2SS_MCS9 = 0x3f, 316 317 DESC_RATEVHT3SS_MCS0 = 0x40, 318 DESC_RATEVHT3SS_MCS1 = 0x41, 319 DESC_RATEVHT3SS_MCS2 = 0x42, 320 DESC_RATEVHT3SS_MCS3 = 0x43, 321 DESC_RATEVHT3SS_MCS4 = 0x44, 322 DESC_RATEVHT3SS_MCS5 = 0x45, 323 DESC_RATEVHT3SS_MCS6 = 0x46, 324 DESC_RATEVHT3SS_MCS7 = 0x47, 325 DESC_RATEVHT3SS_MCS8 = 0x48, 326 DESC_RATEVHT3SS_MCS9 = 0x49, 327 328 DESC_RATEVHT4SS_MCS0 = 0x4a, 329 DESC_RATEVHT4SS_MCS1 = 0x4b, 330 DESC_RATEVHT4SS_MCS2 = 0x4c, 331 DESC_RATEVHT4SS_MCS3 = 0x4d, 332 DESC_RATEVHT4SS_MCS4 = 0x4e, 333 DESC_RATEVHT4SS_MCS5 = 0x4f, 334 DESC_RATEVHT4SS_MCS6 = 0x50, 335 DESC_RATEVHT4SS_MCS7 = 0x51, 336 DESC_RATEVHT4SS_MCS8 = 0x52, 337 DESC_RATEVHT4SS_MCS9 = 0x53, 338 339 DESC_RATE_MAX, 340 }; 341 342 enum rtw_regulatory_domains { 343 RTW_REGD_FCC = 0, 344 RTW_REGD_MKK = 1, 345 RTW_REGD_ETSI = 2, 346 RTW_REGD_IC = 3, 347 RTW_REGD_KCC = 4, 348 RTW_REGD_ACMA = 5, 349 RTW_REGD_CHILE = 6, 350 RTW_REGD_UKRAINE = 7, 351 RTW_REGD_MEXICO = 8, 352 RTW_REGD_CN = 9, 353 RTW_REGD_WW, 354 355 RTW_REGD_MAX 356 }; 357 358 enum rtw_txq_flags { 359 RTW_TXQ_AMPDU, 360 RTW_TXQ_BLOCK_BA, 361 }; 362 363 enum rtw_flags { 364 RTW_FLAG_RUNNING, 365 RTW_FLAG_FW_RUNNING, 366 RTW_FLAG_SCANNING, 367 RTW_FLAG_INACTIVE_PS, 368 RTW_FLAG_LEISURE_PS, 369 RTW_FLAG_LEISURE_PS_DEEP, 370 RTW_FLAG_DIG_DISABLE, 371 RTW_FLAG_BUSY_TRAFFIC, 372 RTW_FLAG_WOWLAN, 373 RTW_FLAG_RESTARTING, 374 RTW_FLAG_RESTART_TRIGGERING, 375 RTW_FLAG_FORCE_LOWEST_RATE, 376 377 NUM_OF_RTW_FLAGS, 378 }; 379 380 enum rtw_evm { 381 RTW_EVM_OFDM = 0, 382 RTW_EVM_1SS, 383 RTW_EVM_2SS_A, 384 RTW_EVM_2SS_B, 385 /* keep it last */ 386 RTW_EVM_NUM 387 }; 388 389 enum rtw_snr { 390 RTW_SNR_OFDM_A = 0, 391 RTW_SNR_OFDM_B, 392 RTW_SNR_OFDM_C, 393 RTW_SNR_OFDM_D, 394 RTW_SNR_1SS_A, 395 RTW_SNR_1SS_B, 396 RTW_SNR_1SS_C, 397 RTW_SNR_1SS_D, 398 RTW_SNR_2SS_A, 399 RTW_SNR_2SS_B, 400 RTW_SNR_2SS_C, 401 RTW_SNR_2SS_D, 402 /* keep it last */ 403 RTW_SNR_NUM 404 }; 405 406 enum rtw_wow_flags { 407 RTW_WOW_FLAG_EN_MAGIC_PKT, 408 RTW_WOW_FLAG_EN_REKEY_PKT, 409 RTW_WOW_FLAG_EN_DISCONNECT, 410 411 /* keep it last */ 412 RTW_WOW_FLAG_MAX, 413 }; 414 415 /* the power index is represented by differences, which cck-1s & ht40-1s are 416 * the base values, so for 1s's differences, there are only ht20 & ofdm 417 */ 418 struct rtw_2g_1s_pwr_idx_diff { 419 #ifdef __LITTLE_ENDIAN 420 s8 ofdm:4; 421 s8 bw20:4; 422 #else 423 s8 bw20:4; 424 s8 ofdm:4; 425 #endif 426 } __packed; 427 428 struct rtw_2g_ns_pwr_idx_diff { 429 #ifdef __LITTLE_ENDIAN 430 s8 bw20:4; 431 s8 bw40:4; 432 s8 cck:4; 433 s8 ofdm:4; 434 #else 435 s8 ofdm:4; 436 s8 cck:4; 437 s8 bw40:4; 438 s8 bw20:4; 439 #endif 440 } __packed; 441 442 struct rtw_2g_txpwr_idx { 443 u8 cck_base[6]; 444 u8 bw40_base[5]; 445 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 446 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 447 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 448 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 449 }; 450 451 struct rtw_5g_ht_1s_pwr_idx_diff { 452 #ifdef __LITTLE_ENDIAN 453 s8 ofdm:4; 454 s8 bw20:4; 455 #else 456 s8 bw20:4; 457 s8 ofdm:4; 458 #endif 459 } __packed; 460 461 struct rtw_5g_ht_ns_pwr_idx_diff { 462 #ifdef __LITTLE_ENDIAN 463 s8 bw20:4; 464 s8 bw40:4; 465 #else 466 s8 bw40:4; 467 s8 bw20:4; 468 #endif 469 } __packed; 470 471 struct rtw_5g_ofdm_ns_pwr_idx_diff { 472 #ifdef __LITTLE_ENDIAN 473 s8 ofdm_3s:4; 474 s8 ofdm_2s:4; 475 s8 ofdm_4s:4; 476 s8 res:4; 477 #else 478 s8 res:4; 479 s8 ofdm_4s:4; 480 s8 ofdm_2s:4; 481 s8 ofdm_3s:4; 482 #endif 483 } __packed; 484 485 struct rtw_5g_vht_ns_pwr_idx_diff { 486 #ifdef __LITTLE_ENDIAN 487 s8 bw160:4; 488 s8 bw80:4; 489 #else 490 s8 bw80:4; 491 s8 bw160:4; 492 #endif 493 } __packed; 494 495 struct rtw_5g_txpwr_idx { 496 u8 bw40_base[14]; 497 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 498 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 499 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 500 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 501 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 502 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 503 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 504 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 505 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 506 }; 507 508 struct rtw_txpwr_idx { 509 struct rtw_2g_txpwr_idx pwr_idx_2g; 510 struct rtw_5g_txpwr_idx pwr_idx_5g; 511 }; 512 513 struct rtw_timer_list { 514 struct timer_list timer; 515 void (*function)(void *data); 516 void *args; 517 }; 518 519 struct rtw_channel_params { 520 u8 center_chan; 521 u8 bandwidth; 522 u8 primary_chan_idx; 523 /* center channel by different available bandwidth, 524 * val of (bw > current bandwidth) is invalid 525 */ 526 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 527 }; 528 529 struct rtw_hw_reg { 530 u32 addr; 531 u32 mask; 532 }; 533 534 struct rtw_ltecoex_addr { 535 u32 ctrl; 536 u32 wdata; 537 u32 rdata; 538 }; 539 540 struct rtw_reg_domain { 541 u32 addr; 542 u32 mask; 543 #define RTW_REG_DOMAIN_MAC32 0 544 #define RTW_REG_DOMAIN_MAC16 1 545 #define RTW_REG_DOMAIN_MAC8 2 546 #define RTW_REG_DOMAIN_RF_A 3 547 #define RTW_REG_DOMAIN_RF_B 4 548 #define RTW_REG_DOMAIN_NL 0xFF 549 u8 domain; 550 }; 551 552 struct rtw_rf_sipi_addr { 553 u32 hssi_1; 554 u32 hssi_2; 555 u32 lssi_read; 556 u32 lssi_read_pi; 557 }; 558 559 struct rtw_hw_reg_offset { 560 struct rtw_hw_reg hw_reg; 561 u8 offset; 562 }; 563 564 struct rtw_backup_info { 565 u8 len; 566 u32 reg; 567 u32 val; 568 }; 569 570 enum rtw_vif_port_set { 571 PORT_SET_MAC_ADDR = BIT(0), 572 PORT_SET_BSSID = BIT(1), 573 PORT_SET_NET_TYPE = BIT(2), 574 PORT_SET_AID = BIT(3), 575 PORT_SET_BCN_CTRL = BIT(4), 576 }; 577 578 struct rtw_vif_port { 579 struct rtw_hw_reg mac_addr; 580 struct rtw_hw_reg bssid; 581 struct rtw_hw_reg net_type; 582 struct rtw_hw_reg aid; 583 struct rtw_hw_reg bcn_ctrl; 584 }; 585 586 struct rtw_tx_pkt_info { 587 u32 tx_pkt_size; 588 u8 offset; 589 u8 pkt_offset; 590 u8 tim_offset; 591 u8 mac_id; 592 u8 rate_id; 593 u8 rate; 594 u8 qsel; 595 u8 bw; 596 u8 sec_type; 597 u8 sn; 598 bool ampdu_en; 599 u8 ampdu_factor; 600 u8 ampdu_density; 601 u16 seq; 602 bool stbc; 603 bool ldpc; 604 bool dis_rate_fallback; 605 bool bmc; 606 bool use_rate; 607 bool ls; 608 bool fs; 609 bool short_gi; 610 bool report; 611 bool rts; 612 bool dis_qselseq; 613 bool en_hwseq; 614 u8 hw_ssn_sel; 615 bool nav_use_hdr; 616 bool bt_null; 617 }; 618 619 struct rtw_rx_pkt_stat { 620 bool phy_status; 621 bool icv_err; 622 bool crc_err; 623 bool decrypted; 624 bool is_c2h; 625 626 s32 signal_power; 627 u16 pkt_len; 628 u8 bw; 629 u8 drv_info_sz; 630 u8 shift; 631 u8 rate; 632 u8 mac_id; 633 u8 cam_id; 634 u8 ppdu_cnt; 635 u32 tsf_low; 636 s8 rx_power[RTW_RF_PATH_MAX]; 637 u8 rssi; 638 u8 rxsc; 639 s8 rx_snr[RTW_RF_PATH_MAX]; 640 u8 rx_evm[RTW_RF_PATH_MAX]; 641 s8 cfo_tail[RTW_RF_PATH_MAX]; 642 u16 freq; 643 u8 band; 644 645 struct rtw_sta_info *si; 646 struct ieee80211_vif *vif; 647 struct ieee80211_hdr *hdr; 648 }; 649 650 DECLARE_EWMA(tp, 10, 2); 651 652 struct rtw_traffic_stats { 653 /* units in bytes */ 654 u64 tx_unicast; 655 u64 rx_unicast; 656 657 /* count for packets */ 658 u64 tx_cnt; 659 u64 rx_cnt; 660 661 /* units in Mbps */ 662 u32 tx_throughput; 663 u32 rx_throughput; 664 struct ewma_tp tx_ewma_tp; 665 struct ewma_tp rx_ewma_tp; 666 }; 667 668 enum rtw_lps_mode { 669 RTW_MODE_ACTIVE = 0, 670 RTW_MODE_LPS = 1, 671 RTW_MODE_WMM_PS = 2, 672 }; 673 674 enum rtw_lps_deep_mode { 675 LPS_DEEP_MODE_NONE = 0, 676 LPS_DEEP_MODE_LCLK = 1, 677 LPS_DEEP_MODE_PG = 2, 678 }; 679 680 enum rtw_pwr_state { 681 RTW_RF_OFF = 0x0, 682 RTW_RF_ON = 0x4, 683 RTW_ALL_ON = 0xc, 684 }; 685 686 struct rtw_lps_conf { 687 enum rtw_lps_mode mode; 688 enum rtw_lps_deep_mode deep_mode; 689 enum rtw_lps_deep_mode wow_deep_mode; 690 enum rtw_pwr_state state; 691 u8 awake_interval; 692 u8 rlbm; 693 u8 smart_ps; 694 u8 port_id; 695 bool sec_cam_backup; 696 bool pattern_cam_backup; 697 }; 698 699 enum rtw_hw_key_type { 700 RTW_CAM_NONE = 0, 701 RTW_CAM_WEP40 = 1, 702 RTW_CAM_TKIP = 2, 703 RTW_CAM_AES = 4, 704 RTW_CAM_WEP104 = 5, 705 }; 706 707 struct rtw_cam_entry { 708 bool valid; 709 bool group; 710 u8 addr[ETH_ALEN]; 711 u8 hw_key_type; 712 struct ieee80211_key_conf *key; 713 }; 714 715 struct rtw_sec_desc { 716 /* search strategy */ 717 bool default_key_search; 718 719 u32 total_cam_num; 720 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 721 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 722 }; 723 724 struct rtw_tx_report { 725 /* protect the tx report queue */ 726 spinlock_t q_lock; 727 struct sk_buff_head queue; 728 atomic_t sn; 729 struct timer_list purge_timer; 730 }; 731 732 struct rtw_ra_report { 733 struct rate_info txrate; 734 u32 bit_rate; 735 u8 desc_rate; 736 }; 737 738 struct rtw_txq { 739 struct list_head list; 740 741 unsigned long flags; 742 unsigned long last_push; 743 }; 744 745 #define RTW_BC_MC_MACID 1 746 DECLARE_EWMA(rssi, 10, 16); 747 748 struct rtw_sta_info { 749 struct ieee80211_sta *sta; 750 struct ieee80211_vif *vif; 751 752 struct ewma_rssi avg_rssi; 753 u8 rssi_level; 754 755 u8 mac_id; 756 u8 rate_id; 757 enum rtw_bandwidth bw_mode; 758 enum rtw_rf_type rf_type; 759 enum rtw_wireless_set wireless_set; 760 u8 stbc_en:2; 761 u8 ldpc_en:2; 762 bool sgi_enable; 763 bool vht_enable; 764 u8 init_ra_lv; 765 u64 ra_mask; 766 767 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 768 769 struct rtw_ra_report ra_report; 770 771 bool use_cfg_mask; 772 struct cfg80211_bitrate_mask *mask; 773 }; 774 775 enum rtw_bfee_role { 776 RTW_BFEE_NONE, 777 RTW_BFEE_SU, 778 RTW_BFEE_MU 779 }; 780 781 struct rtw_bfee { 782 enum rtw_bfee_role role; 783 784 u16 p_aid; 785 u8 g_id; 786 u8 mac_addr[ETH_ALEN]; 787 u8 sound_dim; 788 789 /* SU-MIMO */ 790 u8 su_reg_index; 791 792 /* MU-MIMO */ 793 u16 aid; 794 }; 795 796 struct rtw_bf_info { 797 u8 bfer_mu_cnt; 798 u8 bfer_su_cnt; 799 DECLARE_BITMAP(bfer_su_reg_maping, 2); 800 u8 cur_csi_rpt_rate; 801 }; 802 803 struct rtw_vif { 804 enum rtw_net_type net_type; 805 u16 aid; 806 u8 mac_addr[ETH_ALEN]; 807 u8 bssid[ETH_ALEN]; 808 u8 port; 809 u8 bcn_ctrl; 810 struct list_head rsvd_page_list; 811 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 812 const struct rtw_vif_port *conf; 813 struct cfg80211_scan_request *scan_req; 814 struct ieee80211_scan_ies *scan_ies; 815 816 struct rtw_traffic_stats stats; 817 818 struct rtw_bfee bfee; 819 }; 820 821 struct rtw_regulatory { 822 char alpha2[2]; 823 u8 txpwr_regd_2g; 824 u8 txpwr_regd_5g; 825 }; 826 827 enum rtw_regd_state { 828 RTW_REGD_STATE_WORLDWIDE, 829 RTW_REGD_STATE_PROGRAMMED, 830 RTW_REGD_STATE_SETTING, 831 832 RTW_REGD_STATE_NR, 833 }; 834 835 struct rtw_regd { 836 enum rtw_regd_state state; 837 const struct rtw_regulatory *regulatory; 838 enum nl80211_dfs_regions dfs_region; 839 }; 840 841 struct rtw_chip_ops { 842 int (*mac_init)(struct rtw_dev *rtwdev); 843 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 844 void (*shutdown)(struct rtw_dev *rtwdev); 845 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 846 void (*phy_set_param)(struct rtw_dev *rtwdev); 847 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 848 u8 bandwidth, u8 primary_chan_idx); 849 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 850 struct rtw_rx_pkt_stat *pkt_stat, 851 struct ieee80211_rx_status *rx_status); 852 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 853 u32 addr, u32 mask); 854 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 855 u32 addr, u32 mask, u32 data); 856 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 857 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 858 u32 size); 859 int (*set_antenna)(struct rtw_dev *rtwdev, 860 u32 antenna_tx, 861 u32 antenna_rx); 862 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 863 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 864 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 865 void (*phy_calibration)(struct rtw_dev *rtwdev); 866 void (*dpk_track)(struct rtw_dev *rtwdev); 867 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 868 void (*pwr_track)(struct rtw_dev *rtwdev); 869 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 870 struct rtw_bfee *bfee, bool enable); 871 void (*set_gid_table)(struct rtw_dev *rtwdev, 872 struct ieee80211_vif *vif, 873 struct ieee80211_bss_conf *conf); 874 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 875 u8 fixrate_en, u8 *new_rate); 876 void (*adaptivity_init)(struct rtw_dev *rtwdev); 877 void (*adaptivity)(struct rtw_dev *rtwdev); 878 void (*cfo_init)(struct rtw_dev *rtwdev); 879 void (*cfo_track)(struct rtw_dev *rtwdev); 880 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 881 enum rtw_bb_path tx_path_1ss, 882 enum rtw_bb_path tx_path_cck, 883 bool is_tx2_path); 884 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 885 u8 rx_path, bool is_tx2_path); 886 887 /* for coex */ 888 void (*coex_set_init)(struct rtw_dev *rtwdev); 889 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 890 u8 ctrl_type, u8 pos_type); 891 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 892 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 893 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 894 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 895 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 896 }; 897 898 #define RTW_PWR_POLLING_CNT 20000 899 900 #define RTW_PWR_CMD_READ 0x00 901 #define RTW_PWR_CMD_WRITE 0x01 902 #define RTW_PWR_CMD_POLLING 0x02 903 #define RTW_PWR_CMD_DELAY 0x03 904 #define RTW_PWR_CMD_END 0x04 905 906 /* define the base address of each block */ 907 #define RTW_PWR_ADDR_MAC 0x00 908 #define RTW_PWR_ADDR_USB 0x01 909 #define RTW_PWR_ADDR_PCIE 0x02 910 #define RTW_PWR_ADDR_SDIO 0x03 911 912 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 913 #define RTW_PWR_INTF_USB_MSK BIT(1) 914 #define RTW_PWR_INTF_PCI_MSK BIT(2) 915 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 916 917 #define RTW_PWR_CUT_TEST_MSK BIT(0) 918 #define RTW_PWR_CUT_A_MSK BIT(1) 919 #define RTW_PWR_CUT_B_MSK BIT(2) 920 #define RTW_PWR_CUT_C_MSK BIT(3) 921 #define RTW_PWR_CUT_D_MSK BIT(4) 922 #define RTW_PWR_CUT_E_MSK BIT(5) 923 #define RTW_PWR_CUT_F_MSK BIT(6) 924 #define RTW_PWR_CUT_G_MSK BIT(7) 925 #define RTW_PWR_CUT_ALL_MSK 0xFF 926 927 enum rtw_pwr_seq_cmd_delay_unit { 928 RTW_PWR_DELAY_US, 929 RTW_PWR_DELAY_MS, 930 }; 931 932 struct rtw_pwr_seq_cmd { 933 u16 offset; 934 u8 cut_mask; 935 u8 intf_mask; 936 u8 base:4; 937 u8 cmd:4; 938 u8 mask; 939 u8 value; 940 }; 941 942 enum rtw_chip_ver { 943 RTW_CHIP_VER_CUT_A = 0x00, 944 RTW_CHIP_VER_CUT_B = 0x01, 945 RTW_CHIP_VER_CUT_C = 0x02, 946 RTW_CHIP_VER_CUT_D = 0x03, 947 RTW_CHIP_VER_CUT_E = 0x04, 948 RTW_CHIP_VER_CUT_F = 0x05, 949 RTW_CHIP_VER_CUT_G = 0x06, 950 }; 951 952 #define RTW_INTF_PHY_PLATFORM_ALL 0 953 954 enum rtw_intf_phy_cut { 955 RTW_INTF_PHY_CUT_A = BIT(0), 956 RTW_INTF_PHY_CUT_B = BIT(1), 957 RTW_INTF_PHY_CUT_C = BIT(2), 958 RTW_INTF_PHY_CUT_D = BIT(3), 959 RTW_INTF_PHY_CUT_E = BIT(4), 960 RTW_INTF_PHY_CUT_F = BIT(5), 961 RTW_INTF_PHY_CUT_G = BIT(6), 962 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 963 }; 964 965 enum rtw_ip_sel { 966 RTW_IP_SEL_PHY = 0, 967 RTW_IP_SEL_MAC = 1, 968 RTW_IP_SEL_DBI = 2, 969 970 RTW_IP_SEL_UNDEF = 0xFFFF 971 }; 972 973 enum rtw_pq_map_id { 974 RTW_PQ_MAP_VO = 0x0, 975 RTW_PQ_MAP_VI = 0x1, 976 RTW_PQ_MAP_BE = 0x2, 977 RTW_PQ_MAP_BK = 0x3, 978 RTW_PQ_MAP_MG = 0x4, 979 RTW_PQ_MAP_HI = 0x5, 980 RTW_PQ_MAP_NUM = 0x6, 981 982 RTW_PQ_MAP_UNDEF, 983 }; 984 985 enum rtw_dma_mapping { 986 RTW_DMA_MAPPING_EXTRA = 0, 987 RTW_DMA_MAPPING_LOW = 1, 988 RTW_DMA_MAPPING_NORMAL = 2, 989 RTW_DMA_MAPPING_HIGH = 3, 990 991 RTW_DMA_MAPPING_MAX, 992 RTW_DMA_MAPPING_UNDEF, 993 }; 994 995 struct rtw_rqpn { 996 enum rtw_dma_mapping dma_map_vo; 997 enum rtw_dma_mapping dma_map_vi; 998 enum rtw_dma_mapping dma_map_be; 999 enum rtw_dma_mapping dma_map_bk; 1000 enum rtw_dma_mapping dma_map_mg; 1001 enum rtw_dma_mapping dma_map_hi; 1002 }; 1003 1004 struct rtw_prioq_addr { 1005 u32 rsvd; 1006 u32 avail; 1007 }; 1008 1009 struct rtw_prioq_addrs { 1010 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1011 bool wsize; 1012 }; 1013 1014 struct rtw_page_table { 1015 u16 hq_num; 1016 u16 nq_num; 1017 u16 lq_num; 1018 u16 exq_num; 1019 u16 gapq_num; 1020 }; 1021 1022 struct rtw_intf_phy_para { 1023 u16 offset; 1024 u16 value; 1025 u16 ip_sel; 1026 u16 cut_mask; 1027 u16 platform; 1028 }; 1029 1030 struct rtw_wow_pattern { 1031 u16 crc; 1032 u8 type; 1033 u8 valid; 1034 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1035 }; 1036 1037 struct rtw_pno_request { 1038 bool inited; 1039 u32 match_set_cnt; 1040 struct cfg80211_match_set *match_sets; 1041 u8 channel_cnt; 1042 struct ieee80211_channel *channels; 1043 struct cfg80211_sched_scan_plan scan_plan; 1044 }; 1045 1046 struct rtw_wow_param { 1047 struct ieee80211_vif *wow_vif; 1048 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1049 u8 txpause; 1050 u8 pattern_cnt; 1051 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1052 1053 bool ips_enabled; 1054 struct rtw_pno_request pno_req; 1055 }; 1056 1057 struct rtw_intf_phy_para_table { 1058 const struct rtw_intf_phy_para *usb2_para; 1059 const struct rtw_intf_phy_para *usb3_para; 1060 const struct rtw_intf_phy_para *gen1_para; 1061 const struct rtw_intf_phy_para *gen2_para; 1062 u8 n_usb2_para; 1063 u8 n_usb3_para; 1064 u8 n_gen1_para; 1065 u8 n_gen2_para; 1066 }; 1067 1068 struct rtw_table { 1069 const void *data; 1070 const u32 size; 1071 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1072 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1073 u32 addr, u32 data); 1074 enum rtw_rf_path rf_path; 1075 }; 1076 1077 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1078 const struct rtw_table *tbl) 1079 { 1080 (*tbl->parse)(rtwdev, tbl); 1081 } 1082 1083 enum rtw_rfe_fem { 1084 RTW_RFE_IFEM, 1085 RTW_RFE_EFEM, 1086 RTW_RFE_IFEM2G_EFEM5G, 1087 RTW_RFE_NUM, 1088 }; 1089 1090 struct rtw_rfe_def { 1091 const struct rtw_table *phy_pg_tbl; 1092 const struct rtw_table *txpwr_lmt_tbl; 1093 const struct rtw_table *agc_btg_tbl; 1094 }; 1095 1096 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1097 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1098 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1099 } 1100 1101 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1102 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1103 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1104 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1105 } 1106 1107 #define RTW_PWR_TRK_5G_1 0 1108 #define RTW_PWR_TRK_5G_2 1 1109 #define RTW_PWR_TRK_5G_3 2 1110 #define RTW_PWR_TRK_5G_NUM 3 1111 1112 #define RTW_PWR_TRK_TBL_SZ 30 1113 1114 /* This table stores the values of TX power that will be adjusted by power 1115 * tracking. 1116 * 1117 * For 5G bands, there are 3 different settings. 1118 * For 2G there are cck rate and ofdm rate with different settings. 1119 */ 1120 struct rtw_pwr_track_tbl { 1121 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1122 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1123 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1124 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1125 const u8 *pwrtrk_2gb_n; 1126 const u8 *pwrtrk_2gb_p; 1127 const u8 *pwrtrk_2ga_n; 1128 const u8 *pwrtrk_2ga_p; 1129 const u8 *pwrtrk_2g_cckb_n; 1130 const u8 *pwrtrk_2g_cckb_p; 1131 const u8 *pwrtrk_2g_ccka_n; 1132 const u8 *pwrtrk_2g_ccka_p; 1133 const s8 *pwrtrk_xtal_n; 1134 const s8 *pwrtrk_xtal_p; 1135 }; 1136 1137 enum rtw_wlan_cpu { 1138 RTW_WCPU_11AC, 1139 RTW_WCPU_11N, 1140 }; 1141 1142 enum rtw_fw_fifo_sel { 1143 RTW_FW_FIFO_SEL_TX, 1144 RTW_FW_FIFO_SEL_RX, 1145 RTW_FW_FIFO_SEL_RSVD_PAGE, 1146 RTW_FW_FIFO_SEL_REPORT, 1147 RTW_FW_FIFO_SEL_LLT, 1148 RTW_FW_FIFO_SEL_RXBUF_FW, 1149 1150 RTW_FW_FIFO_MAX, 1151 }; 1152 1153 enum rtw_fwcd_item { 1154 RTW_FWCD_TLV, 1155 RTW_FWCD_REG, 1156 RTW_FWCD_ROM, 1157 RTW_FWCD_IMEM, 1158 RTW_FWCD_DMEM, 1159 RTW_FWCD_EMEM, 1160 }; 1161 1162 /* hardware configuration for each IC */ 1163 struct rtw_chip_info { 1164 struct rtw_chip_ops *ops; 1165 u8 id; 1166 1167 const char *fw_name; 1168 enum rtw_wlan_cpu wlan_cpu; 1169 u8 tx_pkt_desc_sz; 1170 u8 tx_buf_desc_sz; 1171 u8 rx_pkt_desc_sz; 1172 u8 rx_buf_desc_sz; 1173 u32 phy_efuse_size; 1174 u32 log_efuse_size; 1175 u32 ptct_efuse_size; 1176 u32 txff_size; 1177 u32 rxff_size; 1178 u32 fw_rxff_size; 1179 u8 band; 1180 u8 page_size; 1181 u8 csi_buf_pg_num; 1182 u8 dig_max; 1183 u8 dig_min; 1184 u8 txgi_factor; 1185 bool is_pwr_by_rate_dec; 1186 bool rx_ldpc; 1187 bool tx_stbc; 1188 u8 max_power_index; 1189 u8 ampdu_density; 1190 1191 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1192 const struct rtw_fwcd_segs *fwcd_segs; 1193 1194 u8 default_1ss_tx_path; 1195 1196 bool path_div_supported; 1197 bool ht_supported; 1198 bool vht_supported; 1199 u8 lps_deep_mode_supported; 1200 1201 /* init values */ 1202 u8 sys_func_en; 1203 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1204 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1205 const struct rtw_rqpn *rqpn_table; 1206 const struct rtw_prioq_addrs *prioq_addrs; 1207 const struct rtw_page_table *page_table; 1208 const struct rtw_intf_phy_para_table *intf_table; 1209 1210 const struct rtw_hw_reg *dig; 1211 const struct rtw_hw_reg *dig_cck; 1212 u32 rf_base_addr[2]; 1213 u32 rf_sipi_addr[2]; 1214 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1215 u8 fix_rf_phy_num; 1216 const struct rtw_ltecoex_addr *ltecoex_addr; 1217 1218 const struct rtw_table *mac_tbl; 1219 const struct rtw_table *agc_tbl; 1220 const struct rtw_table *bb_tbl; 1221 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1222 const struct rtw_table *rfk_init_tbl; 1223 1224 const struct rtw_rfe_def *rfe_defs; 1225 u32 rfe_defs_size; 1226 1227 bool en_dis_dpd; 1228 u16 dpd_ratemask; 1229 u8 iqk_threshold; 1230 u8 lck_threshold; 1231 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1232 1233 u8 bfer_su_max_num; 1234 u8 bfer_mu_max_num; 1235 1236 struct rtw_hw_reg_offset *edcca_th; 1237 s8 l2h_th_ini_cs; 1238 s8 l2h_th_ini_ad; 1239 1240 const char *wow_fw_name; 1241 const struct wiphy_wowlan_support *wowlan_stub; 1242 const u8 max_sched_scan_ssids; 1243 1244 /* coex paras */ 1245 u32 coex_para_ver; 1246 u8 bt_desired_ver; 1247 bool scbd_support; 1248 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1249 bool ble_hid_profile_support; 1250 bool wl_mimo_ps_support; 1251 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1252 u8 bt_rssi_type; 1253 u8 ant_isolation; 1254 u8 rssi_tolerance; 1255 u8 table_sant_num; 1256 u8 table_nsant_num; 1257 u8 tdma_sant_num; 1258 u8 tdma_nsant_num; 1259 u8 bt_afh_span_bw20; 1260 u8 bt_afh_span_bw40; 1261 u8 afh_5g_num; 1262 u8 wl_rf_para_num; 1263 u8 coex_info_hw_regs_num; 1264 const u8 *bt_rssi_step; 1265 const u8 *wl_rssi_step; 1266 const struct coex_table_para *table_nsant; 1267 const struct coex_table_para *table_sant; 1268 const struct coex_tdma_para *tdma_sant; 1269 const struct coex_tdma_para *tdma_nsant; 1270 const struct coex_rf_para *wl_rf_para_tx; 1271 const struct coex_rf_para *wl_rf_para_rx; 1272 const struct coex_5g_afh_map *afh_5g; 1273 const struct rtw_hw_reg *btg_reg; 1274 const struct rtw_reg_domain *coex_info_hw_regs; 1275 u32 wl_fw_desired_ver; 1276 }; 1277 1278 enum rtw_coex_bt_state_cnt { 1279 COEX_CNT_BT_RETRY, 1280 COEX_CNT_BT_REINIT, 1281 COEX_CNT_BT_REENABLE, 1282 COEX_CNT_BT_POPEVENT, 1283 COEX_CNT_BT_SETUPLINK, 1284 COEX_CNT_BT_IGNWLANACT, 1285 COEX_CNT_BT_INQ, 1286 COEX_CNT_BT_PAGE, 1287 COEX_CNT_BT_ROLESWITCH, 1288 COEX_CNT_BT_AFHUPDATE, 1289 COEX_CNT_BT_INFOUPDATE, 1290 COEX_CNT_BT_IQK, 1291 COEX_CNT_BT_IQKFAIL, 1292 1293 COEX_CNT_BT_MAX 1294 }; 1295 1296 enum rtw_coex_wl_state_cnt { 1297 COEX_CNT_WL_SCANAP, 1298 COEX_CNT_WL_CONNPKT, 1299 COEX_CNT_WL_COEXRUN, 1300 COEX_CNT_WL_NOISY0, 1301 COEX_CNT_WL_NOISY1, 1302 COEX_CNT_WL_NOISY2, 1303 COEX_CNT_WL_5MS_NOEXTEND, 1304 COEX_CNT_WL_FW_NOTIFY, 1305 1306 COEX_CNT_WL_MAX 1307 }; 1308 1309 struct rtw_coex_rfe { 1310 bool ant_switch_exist; 1311 bool ant_switch_diversity; 1312 bool ant_switch_with_bt; 1313 u8 rfe_module_type; 1314 u8 ant_switch_polarity; 1315 1316 /* true if WLG at BTG, else at WLAG */ 1317 bool wlg_at_btg; 1318 }; 1319 1320 #define COEX_WL_TDMA_PARA_LENGTH 5 1321 1322 struct rtw_coex_dm { 1323 bool cur_ps_tdma_on; 1324 bool cur_wl_rx_low_gain_en; 1325 bool ignore_wl_act; 1326 1327 u8 reason; 1328 u8 bt_rssi_state[4]; 1329 u8 wl_rssi_state[4]; 1330 u8 wl_ch_info[3]; 1331 u8 cur_ps_tdma; 1332 u8 cur_table; 1333 u8 ps_tdma_para[5]; 1334 u8 cur_bt_pwr_lvl; 1335 u8 cur_bt_lna_lvl; 1336 u8 cur_wl_pwr_lvl; 1337 u8 bt_status; 1338 u32 cur_ant_pos_type; 1339 u32 cur_switch_status; 1340 u32 setting_tdma; 1341 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1342 }; 1343 1344 #define COEX_BTINFO_SRC_WL_FW 0x0 1345 #define COEX_BTINFO_SRC_BT_RSP 0x1 1346 #define COEX_BTINFO_SRC_BT_ACT 0x2 1347 #define COEX_BTINFO_SRC_BT_IQK 0x3 1348 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1349 #define COEX_BTINFO_SRC_H2C60 0x5 1350 #define COEX_BTINFO_SRC_MAX 0x6 1351 1352 #define COEX_INFO_FTP BIT(7) 1353 #define COEX_INFO_A2DP BIT(6) 1354 #define COEX_INFO_HID BIT(5) 1355 #define COEX_INFO_SCO_BUSY BIT(4) 1356 #define COEX_INFO_ACL_BUSY BIT(3) 1357 #define COEX_INFO_INQ_PAGE BIT(2) 1358 #define COEX_INFO_SCO_ESCO BIT(1) 1359 #define COEX_INFO_CONNECTION BIT(0) 1360 #define COEX_BTINFO_LENGTH_MAX 10 1361 #define COEX_BTINFO_LENGTH 7 1362 1363 #define COEX_BT_HIDINFO_LIST 0x0 1364 #define COEX_BT_HIDINFO_A 0x1 1365 #define COEX_BT_HIDINFO_NAME 3 1366 1367 #define COEX_BT_HIDINFO_LENGTH 6 1368 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1369 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1370 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1371 #define COEX_BT_BLE_HANDLE_THRS 0x10 1372 #define COEX_BT_HIDINFO_NOTCON 0xff 1373 1374 struct rtw_coex_hid { 1375 u8 hid_handle; 1376 u8 hid_vendor; 1377 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1378 bool hid_info_completed; 1379 bool is_game_hid; 1380 }; 1381 1382 struct rtw_coex_hid_handle_list { 1383 u8 cmd_id; 1384 u8 len; 1385 u8 subid; 1386 u8 handle_cnt; 1387 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1388 } __packed; 1389 1390 struct rtw_coex_hid_info_a { 1391 u8 cmd_id; 1392 u8 len; 1393 u8 subid; 1394 u8 handle; 1395 u8 vendor; 1396 u8 name[COEX_BT_HIDINFO_NAME]; 1397 } __packed; 1398 1399 struct rtw_coex_stat { 1400 bool bt_disabled; 1401 bool bt_disabled_pre; 1402 bool bt_link_exist; 1403 bool bt_whck_test; 1404 bool bt_inq_page; 1405 bool bt_inq_remain; 1406 bool bt_inq; 1407 bool bt_page; 1408 bool bt_ble_voice; 1409 bool bt_ble_exist; 1410 bool bt_hfp_exist; 1411 bool bt_a2dp_exist; 1412 bool bt_hid_exist; 1413 bool bt_pan_exist; /* PAN or OPP */ 1414 bool bt_opp_exist; /* OPP only */ 1415 bool bt_acl_busy; 1416 bool bt_fix_2M; 1417 bool bt_setup_link; 1418 bool bt_multi_link; 1419 bool bt_multi_link_pre; 1420 bool bt_multi_link_remain; 1421 bool bt_a2dp_sink; 1422 bool bt_a2dp_active; 1423 bool bt_reenable; 1424 bool bt_ble_scan_en; 1425 bool bt_init_scan; 1426 bool bt_slave; 1427 bool bt_418_hid_exist; 1428 bool bt_ble_hid_exist; 1429 bool bt_game_hid_exist; 1430 bool bt_hid_handle_cnt; 1431 bool bt_mailbox_reply; 1432 1433 bool wl_under_lps; 1434 bool wl_under_ips; 1435 bool wl_hi_pri_task1; 1436 bool wl_hi_pri_task2; 1437 bool wl_force_lps_ctrl; 1438 bool wl_gl_busy; 1439 bool wl_linkscan_proc; 1440 bool wl_ps_state_fail; 1441 bool wl_tx_limit_en; 1442 bool wl_ampdu_limit_en; 1443 bool wl_connected; 1444 bool wl_slot_extend; 1445 bool wl_cck_lock; 1446 bool wl_cck_lock_pre; 1447 bool wl_cck_lock_ever; 1448 bool wl_connecting; 1449 bool wl_slot_toggle; 1450 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1451 bool wl_mimo_ps; 1452 1453 u32 bt_supported_version; 1454 u32 bt_supported_feature; 1455 u32 hi_pri_tx; 1456 u32 hi_pri_rx; 1457 u32 lo_pri_tx; 1458 u32 lo_pri_rx; 1459 u32 patch_ver; 1460 u16 bt_reg_vendor_ae; 1461 u16 bt_reg_vendor_ac; 1462 s8 bt_rssi; 1463 u8 kt_ver; 1464 u8 gnt_workaround_state; 1465 u8 tdma_timer_base; 1466 u8 bt_profile_num; 1467 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1468 u8 bt_info_lb2; 1469 u8 bt_info_lb3; 1470 u8 bt_info_hb0; 1471 u8 bt_info_hb1; 1472 u8 bt_info_hb2; 1473 u8 bt_info_hb3; 1474 u8 bt_ble_scan_type; 1475 u8 bt_hid_pair_num; 1476 u8 bt_hid_slot; 1477 u8 bt_a2dp_bitpool; 1478 u8 bt_iqk_state; 1479 1480 u16 wl_beacon_interval; 1481 u8 wl_noisy_level; 1482 u8 wl_fw_dbg_info[10]; 1483 u8 wl_fw_dbg_info_pre[10]; 1484 u8 wl_rx_rate; 1485 u8 wl_tx_rate; 1486 u8 wl_rts_rx_rate; 1487 u8 wl_coex_mode; 1488 u8 wl_iot_peer; 1489 u8 ampdu_max_time; 1490 u8 wl_tput_dir; 1491 1492 u8 wl_toggle_para[6]; 1493 u8 wl_toggle_interval; 1494 1495 u16 score_board; 1496 u16 retry_limit; 1497 1498 /* counters to record bt states */ 1499 u32 cnt_bt[COEX_CNT_BT_MAX]; 1500 1501 /* counters to record wifi states */ 1502 u32 cnt_wl[COEX_CNT_WL_MAX]; 1503 1504 /* counters to record bt c2h data */ 1505 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1506 1507 u32 darfrc; 1508 u32 darfrch; 1509 1510 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1511 struct rtw_coex_hid_handle_list hid_handle_list; 1512 }; 1513 1514 struct rtw_coex { 1515 /* protects coex info request section */ 1516 struct mutex mutex; 1517 struct sk_buff_head queue; 1518 wait_queue_head_t wait; 1519 1520 bool under_5g; 1521 bool stop_dm; 1522 bool freeze; 1523 bool freerun; 1524 bool wl_rf_off; 1525 bool manual_control; 1526 1527 struct rtw_coex_stat stat; 1528 struct rtw_coex_dm dm; 1529 struct rtw_coex_rfe rfe; 1530 1531 struct delayed_work bt_relink_work; 1532 struct delayed_work bt_reenable_work; 1533 struct delayed_work defreeze_work; 1534 struct delayed_work wl_remain_work; 1535 struct delayed_work bt_remain_work; 1536 struct delayed_work wl_connecting_work; 1537 struct delayed_work bt_multi_link_remain_work; 1538 struct delayed_work wl_ccklock_work; 1539 1540 }; 1541 1542 #define DPK_RF_REG_NUM 7 1543 #define DPK_RF_PATH_NUM 2 1544 #define DPK_BB_REG_NUM 18 1545 #define DPK_CHANNEL_WIDTH_80 1 1546 1547 DECLARE_EWMA(thermal, 10, 4); 1548 1549 struct rtw_dpk_info { 1550 bool is_dpk_pwr_on; 1551 bool is_reload; 1552 1553 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1554 1555 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1556 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1557 1558 u32 gnt_control; 1559 u32 gnt_value; 1560 1561 u8 result[RTW_RF_PATH_MAX]; 1562 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1563 u32 coef[RTW_RF_PATH_MAX][20]; 1564 u16 dpk_gs[RTW_RF_PATH_MAX]; 1565 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1566 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1567 1568 u8 dpk_band; 1569 u8 dpk_ch; 1570 u8 dpk_bw; 1571 }; 1572 1573 struct rtw_phy_cck_pd_reg { 1574 u32 reg_pd; 1575 u32 mask_pd; 1576 u32 reg_cs; 1577 u32 mask_cs; 1578 }; 1579 1580 #define DACK_MSBK_BACKUP_NUM 0xf 1581 #define DACK_DCK_BACKUP_NUM 0x2 1582 1583 struct rtw_swing_table { 1584 const u8 *p[RTW_RF_PATH_MAX]; 1585 const u8 *n[RTW_RF_PATH_MAX]; 1586 }; 1587 1588 struct rtw_pkt_count { 1589 u16 num_bcn_pkt; 1590 u16 num_qry_pkt[DESC_RATE_MAX]; 1591 }; 1592 1593 DECLARE_EWMA(evm, 10, 4); 1594 DECLARE_EWMA(snr, 10, 4); 1595 1596 struct rtw_iqk_info { 1597 bool done; 1598 struct { 1599 u32 s1_x; 1600 u32 s1_y; 1601 u32 s0_x; 1602 u32 s0_y; 1603 } result; 1604 }; 1605 1606 enum rtw_rf_band { 1607 RF_BAND_2G_CCK, 1608 RF_BAND_2G_OFDM, 1609 RF_BAND_5G_L, 1610 RF_BAND_5G_M, 1611 RF_BAND_5G_H, 1612 RF_BAND_MAX 1613 }; 1614 1615 #define RF_GAIN_NUM 11 1616 #define RF_HW_OFFSET_NUM 10 1617 1618 struct rtw_gapk_info { 1619 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1620 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1621 bool txgapk_bp_done; 1622 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1623 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1624 u8 read_txgain; 1625 u8 channel; 1626 }; 1627 1628 #define EDCCA_TH_L2H_IDX 0 1629 #define EDCCA_TH_H2L_IDX 1 1630 #define EDCCA_TH_L2H_LB 48 1631 #define EDCCA_ADC_BACKOFF 12 1632 #define EDCCA_IGI_BASE 50 1633 #define EDCCA_IGI_L2H_DIFF 8 1634 #define EDCCA_L2H_H2L_DIFF 7 1635 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1636 1637 enum rtw_edcca_mode { 1638 RTW_EDCCA_NORMAL = 0, 1639 RTW_EDCCA_ADAPTIVITY = 1, 1640 }; 1641 1642 struct rtw_cfo_track { 1643 bool is_adjust; 1644 u8 crystal_cap; 1645 s32 cfo_tail[RTW_RF_PATH_MAX]; 1646 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1647 u32 packet_count; 1648 u32 packet_count_pre; 1649 }; 1650 1651 #define RRSR_INIT_2G 0x15f 1652 #define RRSR_INIT_5G 0x150 1653 1654 enum rtw_dm_cap { 1655 RTW_DM_CAP_NA, 1656 RTW_DM_CAP_TXGAPK, 1657 RTW_DM_CAP_NUM 1658 }; 1659 1660 struct rtw_dm_info { 1661 u32 cck_fa_cnt; 1662 u32 ofdm_fa_cnt; 1663 u32 total_fa_cnt; 1664 u32 cck_cca_cnt; 1665 u32 ofdm_cca_cnt; 1666 u32 total_cca_cnt; 1667 1668 u32 cck_ok_cnt; 1669 u32 cck_err_cnt; 1670 u32 ofdm_ok_cnt; 1671 u32 ofdm_err_cnt; 1672 u32 ht_ok_cnt; 1673 u32 ht_err_cnt; 1674 u32 vht_ok_cnt; 1675 u32 vht_err_cnt; 1676 1677 u8 min_rssi; 1678 u8 pre_min_rssi; 1679 u16 fa_history[4]; 1680 u8 igi_history[4]; 1681 u8 igi_bitmap; 1682 bool damping; 1683 u8 damping_cnt; 1684 u8 damping_rssi; 1685 1686 u8 cck_gi_u_bnd; 1687 u8 cck_gi_l_bnd; 1688 1689 u8 fix_rate; 1690 u8 tx_rate; 1691 u32 rrsr_val_init; 1692 u32 rrsr_mask_min; 1693 u8 thermal_avg[RTW_RF_PATH_MAX]; 1694 u8 thermal_meter_k; 1695 u8 thermal_meter_lck; 1696 s8 delta_power_index[RTW_RF_PATH_MAX]; 1697 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1698 u8 default_ofdm_index; 1699 bool pwr_trk_triggered; 1700 bool pwr_trk_init_trigger; 1701 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1702 s8 txagc_remnant_cck; 1703 s8 txagc_remnant_ofdm; 1704 1705 /* backup dack results for each path and I/Q */ 1706 u32 dack_adck[RTW_RF_PATH_MAX]; 1707 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1708 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1709 1710 struct rtw_dpk_info dpk_info; 1711 struct rtw_cfo_track cfo_track; 1712 1713 /* [bandwidth 0:20M/1:40M][number of path] */ 1714 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1715 u32 cck_fa_avg; 1716 u8 cck_pd_default; 1717 1718 /* save the last rx phy status for debug */ 1719 s8 rx_snr[RTW_RF_PATH_MAX]; 1720 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1721 s16 cfo_tail[RTW_RF_PATH_MAX]; 1722 u8 rssi[RTW_RF_PATH_MAX]; 1723 u8 curr_rx_rate; 1724 struct rtw_pkt_count cur_pkt_count; 1725 struct rtw_pkt_count last_pkt_count; 1726 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1727 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1728 1729 u32 dm_flags; /* enum rtw_dm_cap */ 1730 struct rtw_iqk_info iqk; 1731 struct rtw_gapk_info gapk; 1732 bool is_bt_iqk_timeout; 1733 1734 s8 l2h_th_ini; 1735 enum rtw_edcca_mode edcca_mode; 1736 u8 scan_density; 1737 }; 1738 1739 struct rtw_efuse { 1740 u32 size; 1741 u32 physical_size; 1742 u32 logical_size; 1743 u32 protect_size; 1744 1745 u8 addr[ETH_ALEN]; 1746 u8 channel_plan; 1747 u8 country_code[2]; 1748 u8 rf_board_option; 1749 u8 rfe_option; 1750 u8 power_track_type; 1751 u8 thermal_meter[RTW_RF_PATH_MAX]; 1752 u8 thermal_meter_k; 1753 u8 crystal_cap; 1754 u8 ant_div_cfg; 1755 u8 ant_div_type; 1756 u8 regd; 1757 u8 afe; 1758 1759 u8 lna_type_2g; 1760 u8 lna_type_5g; 1761 u8 glna_type; 1762 u8 alna_type; 1763 bool ext_lna_2g; 1764 bool ext_lna_5g; 1765 u8 pa_type_2g; 1766 u8 pa_type_5g; 1767 u8 gpa_type; 1768 u8 apa_type; 1769 bool ext_pa_2g; 1770 bool ext_pa_5g; 1771 u8 tx_bb_swing_setting_2g; 1772 u8 tx_bb_swing_setting_5g; 1773 1774 bool btcoex; 1775 /* bt share antenna with wifi */ 1776 bool share_ant; 1777 u8 bt_setting; 1778 1779 struct { 1780 u8 hci; 1781 u8 bw; 1782 u8 ptcl; 1783 u8 nss; 1784 u8 ant_num; 1785 } hw_cap; 1786 1787 struct rtw_txpwr_idx txpwr_idx_table[4]; 1788 }; 1789 1790 struct rtw_phy_cond { 1791 #ifdef __LITTLE_ENDIAN 1792 u32 rfe:8; 1793 u32 intf:4; 1794 u32 pkg:4; 1795 u32 plat:4; 1796 u32 intf_rsvd:4; 1797 u32 cut:4; 1798 u32 branch:2; 1799 u32 neg:1; 1800 u32 pos:1; 1801 #else 1802 u32 pos:1; 1803 u32 neg:1; 1804 u32 branch:2; 1805 u32 cut:4; 1806 u32 intf_rsvd:4; 1807 u32 plat:4; 1808 u32 pkg:4; 1809 u32 intf:4; 1810 u32 rfe:8; 1811 #endif 1812 /* for intf:4 */ 1813 #define INTF_PCIE BIT(0) 1814 #define INTF_USB BIT(1) 1815 #define INTF_SDIO BIT(2) 1816 /* for branch:2 */ 1817 #define BRANCH_IF 0 1818 #define BRANCH_ELIF 1 1819 #define BRANCH_ELSE 2 1820 #define BRANCH_ENDIF 3 1821 }; 1822 1823 struct rtw_fifo_conf { 1824 /* tx fifo information */ 1825 u16 rsvd_boundary; 1826 u16 rsvd_pg_num; 1827 u16 rsvd_drv_pg_num; 1828 u16 txff_pg_num; 1829 u16 acq_pg_num; 1830 u16 rsvd_drv_addr; 1831 u16 rsvd_h2c_info_addr; 1832 u16 rsvd_h2c_sta_info_addr; 1833 u16 rsvd_h2cq_addr; 1834 u16 rsvd_cpu_instr_addr; 1835 u16 rsvd_fw_txbuf_addr; 1836 u16 rsvd_csibuf_addr; 1837 const struct rtw_rqpn *rqpn; 1838 }; 1839 1840 struct rtw_fwcd_desc { 1841 u32 size; 1842 u8 *next; 1843 u8 *data; 1844 }; 1845 1846 struct rtw_fwcd_segs { 1847 const u32 *segs; 1848 u8 num; 1849 }; 1850 1851 #define FW_CD_TYPE 0xffff 1852 #define FW_CD_LEN 4 1853 #define FW_CD_VAL 0xaabbccdd 1854 struct rtw_fw_state { 1855 const struct firmware *firmware; 1856 struct rtw_dev *rtwdev; 1857 struct completion completion; 1858 struct rtw_fwcd_desc fwcd_desc; 1859 u16 version; 1860 u8 sub_version; 1861 u8 sub_index; 1862 u16 h2c_version; 1863 u32 feature; 1864 }; 1865 1866 enum rtw_sar_sources { 1867 RTW_SAR_SOURCE_NONE, 1868 RTW_SAR_SOURCE_COMMON, 1869 }; 1870 1871 enum rtw_sar_bands { 1872 RTW_SAR_BAND_0, 1873 RTW_SAR_BAND_1, 1874 /* RTW_SAR_BAND_2, not used now */ 1875 RTW_SAR_BAND_3, 1876 RTW_SAR_BAND_4, 1877 1878 RTW_SAR_BAND_NR, 1879 }; 1880 1881 /* the union is reserved for other knids of SAR sources 1882 * which might not re-use same format with array common. 1883 */ 1884 union rtw_sar_cfg { 1885 s8 common[RTW_SAR_BAND_NR]; 1886 }; 1887 1888 struct rtw_sar { 1889 enum rtw_sar_sources src; 1890 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1891 }; 1892 1893 struct rtw_hal { 1894 u32 rcr; 1895 1896 u32 chip_version; 1897 u8 cut_version; 1898 u8 mp_chip; 1899 u8 oem_id; 1900 struct rtw_phy_cond phy_cond; 1901 1902 u8 ps_mode; 1903 u8 current_channel; 1904 u8 current_primary_channel_index; 1905 u8 current_band_width; 1906 u8 current_band_type; 1907 1908 /* center channel for different available bandwidth, 1909 * val of (bw > current_band_width) is invalid 1910 */ 1911 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1912 1913 u8 sec_ch_offset; 1914 u8 rf_type; 1915 u8 rf_path_num; 1916 u8 rf_phy_num; 1917 u32 antenna_tx; 1918 u32 antenna_rx; 1919 u8 bfee_sts_cap; 1920 bool txrx_1ss; 1921 1922 /* protect tx power section */ 1923 struct mutex tx_power_mutex; 1924 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1925 [DESC_RATE_MAX]; 1926 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1927 [DESC_RATE_MAX]; 1928 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1929 [RTW_RATE_SECTION_MAX]; 1930 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1931 [RTW_RATE_SECTION_MAX]; 1932 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1933 [RTW_CHANNEL_WIDTH_MAX] 1934 [RTW_RATE_SECTION_MAX] 1935 [RTW_MAX_CHANNEL_NUM_2G]; 1936 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1937 [RTW_CHANNEL_WIDTH_MAX] 1938 [RTW_RATE_SECTION_MAX] 1939 [RTW_MAX_CHANNEL_NUM_5G]; 1940 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1941 [DESC_RATE_MAX]; 1942 1943 enum rtw_sar_bands sar_band; 1944 struct rtw_sar sar; 1945 1946 /* for 8821c set channel */ 1947 u32 ch_param[3]; 1948 }; 1949 1950 struct rtw_path_div { 1951 enum rtw_bb_path current_tx_path; 1952 u32 path_a_sum; 1953 u32 path_b_sum; 1954 u16 path_a_cnt; 1955 u16 path_b_cnt; 1956 }; 1957 1958 struct rtw_chan_info { 1959 int pri_ch_idx; 1960 int action_id; 1961 int bw; 1962 u8 extra_info; 1963 u8 channel; 1964 u16 timeout; 1965 }; 1966 1967 struct rtw_chan_list { 1968 u32 buf_size; 1969 u32 ch_num; 1970 u32 size; 1971 u16 addr; 1972 }; 1973 1974 struct rtw_hw_scan_info { 1975 struct ieee80211_vif *scanning_vif; 1976 u8 probe_pg_size; 1977 u8 op_pri_ch_idx; 1978 u8 op_chan; 1979 u8 op_bw; 1980 }; 1981 1982 struct rtw_dev { 1983 struct ieee80211_hw *hw; 1984 struct device *dev; 1985 1986 struct rtw_hci hci; 1987 1988 struct rtw_hw_scan_info scan_info; 1989 struct rtw_chip_info *chip; 1990 struct rtw_hal hal; 1991 struct rtw_fifo_conf fifo; 1992 struct rtw_fw_state fw; 1993 struct rtw_efuse efuse; 1994 struct rtw_sec_desc sec; 1995 struct rtw_traffic_stats stats; 1996 struct rtw_regd regd; 1997 struct rtw_bf_info bf_info; 1998 1999 struct rtw_dm_info dm_info; 2000 struct rtw_coex coex; 2001 2002 /* ensures exclusive access from mac80211 callbacks */ 2003 struct mutex mutex; 2004 2005 /* read/write rf register */ 2006 spinlock_t rf_lock; 2007 2008 /* watch dog every 2 sec */ 2009 struct delayed_work watch_dog_work; 2010 u32 watch_dog_cnt; 2011 2012 struct list_head rsvd_page_list; 2013 2014 /* c2h cmd queue & handler work */ 2015 struct sk_buff_head c2h_queue; 2016 struct work_struct c2h_work; 2017 struct work_struct ips_work; 2018 struct work_struct fw_recovery_work; 2019 struct work_struct update_beacon_work; 2020 2021 /* used to protect txqs list */ 2022 spinlock_t txq_lock; 2023 struct list_head txqs; 2024 struct workqueue_struct *tx_wq; 2025 struct work_struct tx_work; 2026 struct work_struct ba_work; 2027 2028 struct rtw_tx_report tx_report; 2029 2030 struct { 2031 /* incicate the mail box to use with fw */ 2032 u8 last_box_num; 2033 /* protect to send h2c to fw */ 2034 spinlock_t lock; 2035 u32 seq; 2036 } h2c; 2037 2038 /* lps power state & handler work */ 2039 struct rtw_lps_conf lps_conf; 2040 bool ps_enabled; 2041 bool beacon_loss; 2042 struct completion lps_leave_check; 2043 2044 struct dentry *debugfs; 2045 2046 u8 sta_cnt; 2047 u32 rts_threshold; 2048 2049 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2050 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2051 2052 u8 mp_mode; 2053 struct rtw_path_div dm_path_div; 2054 2055 struct rtw_fw_state wow_fw; 2056 struct rtw_wow_param wow; 2057 2058 bool need_rfk; 2059 struct completion fw_scan_density; 2060 2061 /* hci related data, must be last */ 2062 u8 priv[] __aligned(sizeof(void *)); 2063 }; 2064 2065 #include "hci.h" 2066 2067 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2068 { 2069 return !!rtwdev->sta_cnt; 2070 } 2071 2072 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2073 { 2074 void *p = rtwtxq; 2075 2076 return container_of(p, struct ieee80211_txq, drv_priv); 2077 } 2078 2079 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2080 { 2081 void *p = rtwvif; 2082 2083 return container_of(p, struct ieee80211_vif, drv_priv); 2084 } 2085 2086 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 2087 struct cfg80211_ssid *b) 2088 { 2089 if (!a || !b || a->ssid_len != b->ssid_len) 2090 return false; 2091 2092 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 2093 return false; 2094 2095 return true; 2096 } 2097 2098 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2099 { 2100 if (rtwdev->chip->ops->efuse_grant) 2101 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2102 } 2103 2104 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2105 { 2106 if (rtwdev->chip->ops->efuse_grant) 2107 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2108 } 2109 2110 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2111 { 2112 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2113 } 2114 2115 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2116 { 2117 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2118 } 2119 2120 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2121 { 2122 return rtwdev->chip->rx_ldpc; 2123 } 2124 2125 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2126 { 2127 return rtwdev->chip->tx_stbc; 2128 } 2129 2130 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2131 { 2132 clear_bit(mac_id, rtwdev->mac_id_map); 2133 } 2134 2135 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2136 { 2137 if (rtwdev->chip->ops->dump_fw_crash) 2138 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2139 2140 return 0; 2141 } 2142 2143 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2144 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2145 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2146 struct rtw_channel_params *ch_param); 2147 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2148 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2149 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2150 void rtw_restore_reg(struct rtw_dev *rtwdev, 2151 struct rtw_backup_info *bckp, u32 num); 2152 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2153 void rtw_set_channel(struct rtw_dev *rtwdev); 2154 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2155 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2156 u32 config); 2157 void rtw_tx_report_purge_timer(struct timer_list *t); 2158 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2159 bool reset_ra_mask); 2160 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2161 const u8 *mac_addr, bool hw_scan); 2162 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2163 bool hw_scan); 2164 int rtw_core_start(struct rtw_dev *rtwdev); 2165 void rtw_core_stop(struct rtw_dev *rtwdev); 2166 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2167 int rtw_core_init(struct rtw_dev *rtwdev); 2168 void rtw_core_deinit(struct rtw_dev *rtwdev); 2169 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2170 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2171 u16 rtw_desc_to_bitrate(u8 desc_rate); 2172 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2173 struct ieee80211_bss_conf *conf); 2174 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2175 struct ieee80211_vif *vif); 2176 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2177 bool fw_exist); 2178 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2179 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2180 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2181 u32 fwcd_item); 2182 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2183 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2184 #if defined(__linux__) 2185 #define rtw88_static_assert(_x) static_assert(_x) 2186 #elif defined(__FreeBSD__) 2187 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size") 2188 #endif 2189 2190 #endif 2191