1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT76_CONNAC_H 5 #define __MT76_CONNAC_H 6 7 #include "mt76.h" 8 9 #define MT76_CONNAC_SCAN_IE_LEN 600 10 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL 10 11 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX 12 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID 10 13 #define MT76_CONNAC_MAX_SCAN_MATCH 16 14 15 #define MT76_CONNAC_MAX_WMM_SETS 4 16 17 #define MT76_CONNAC_COREDUMP_TIMEOUT (HZ / 20) 18 #define MT76_CONNAC_COREDUMP_SZ (1300 * 1024) 19 20 #define MT_TXD_SIZE (8 * 4) 21 22 #define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 23 #define MT_USB_HDR_SIZE 4 24 #define MT_USB_TAIL_SIZE 4 25 26 #define MT_SDIO_TXD_SIZE (MT_TXD_SIZE + 8 * 4) 27 #define MT_SDIO_TAIL_SIZE 8 28 #define MT_SDIO_HDR_SIZE 4 29 30 #define MT_MSDU_ID_VALID BIT(15) 31 32 #define MT_TXD_LEN_LAST BIT(15) 33 #define MT_TXD_LEN_MASK GENMASK(11, 0) 34 #define MT_TXD_LEN_MSDU_LAST BIT(14) 35 #define MT_TXD_LEN_AMSDU_LAST BIT(15) 36 37 enum { 38 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 39 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 40 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 41 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 42 CMD_CBW_10MHZ, 43 CMD_CBW_5MHZ, 44 CMD_CBW_8080MHZ, 45 46 CMD_HE_MCS_BW80 = 0, 47 CMD_HE_MCS_BW160, 48 CMD_HE_MCS_BW8080, 49 CMD_HE_MCS_BW_NUM 50 }; 51 52 enum { 53 HW_BSSID_0 = 0x0, 54 HW_BSSID_1, 55 HW_BSSID_2, 56 HW_BSSID_3, 57 HW_BSSID_MAX = HW_BSSID_3, 58 EXT_BSSID_START = 0x10, 59 EXT_BSSID_1, 60 EXT_BSSID_15 = 0x1f, 61 EXT_BSSID_MAX = EXT_BSSID_15, 62 REPEATER_BSSID_START = 0x20, 63 REPEATER_BSSID_MAX = 0x3f, 64 }; 65 66 struct mt76_connac_reg_map { 67 u32 phys; 68 u32 maps; 69 u32 size; 70 }; 71 72 struct mt76_connac_pm { 73 bool enable:1; 74 bool enable_user:1; 75 bool ds_enable:1; 76 bool ds_enable_user:1; 77 bool suspended:1; 78 79 spinlock_t txq_lock; 80 struct { 81 struct mt76_wcid *wcid; 82 struct sk_buff *skb; 83 } tx_q[IEEE80211_NUM_ACS]; 84 85 struct work_struct wake_work; 86 wait_queue_head_t wait; 87 88 struct { 89 spinlock_t lock; 90 u32 count; 91 } wake; 92 struct mutex mutex; 93 94 struct delayed_work ps_work; 95 unsigned long last_activity; 96 unsigned long idle_timeout; 97 98 struct { 99 unsigned long last_wake_event; 100 unsigned long awake_time; 101 unsigned long last_doze_event; 102 unsigned long doze_time; 103 unsigned int lp_wake; 104 } stats; 105 }; 106 107 struct mt76_connac_coredump { 108 struct sk_buff_head msg_list; 109 struct delayed_work work; 110 unsigned long last_activity; 111 }; 112 113 struct mt76_connac_sta_key_conf { 114 s8 keyidx; 115 u8 key[16]; 116 }; 117 118 #define MT_TXP_MAX_BUF_NUM 6 119 120 struct mt76_connac_fw_txp { 121 __le16 flags; 122 __le16 token; 123 u8 bss_idx; 124 __le16 rept_wds_wcid; 125 u8 nbuf; 126 __le32 buf[MT_TXP_MAX_BUF_NUM]; 127 __le16 len[MT_TXP_MAX_BUF_NUM]; 128 } __packed __aligned(4); 129 130 #define MT_HW_TXP_MAX_MSDU_NUM 4 131 #define MT_HW_TXP_MAX_BUF_NUM 4 132 133 struct mt76_connac_txp_ptr { 134 __le32 buf0; 135 __le16 len0; 136 __le16 len1; 137 __le32 buf1; 138 } __packed __aligned(4); 139 140 struct mt76_connac_hw_txp { 141 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM]; 142 struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2]; 143 } __packed __aligned(4); 144 145 struct mt76_connac_txp_common { 146 union { 147 struct mt76_connac_fw_txp fw; 148 struct mt76_connac_hw_txp hw; 149 }; 150 }; 151 152 struct mt76_connac_tx_free { 153 __le16 rx_byte_cnt; 154 __le16 ctrl; 155 __le32 txd; 156 } __packed __aligned(4); 157 158 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support; 159 160 static inline bool is_mt7922(struct mt76_dev *dev) 161 { 162 return mt76_chip(dev) == 0x7922; 163 } 164 165 static inline bool is_mt7921(struct mt76_dev *dev) 166 { 167 return mt76_chip(dev) == 0x7961 || is_mt7922(dev); 168 } 169 170 static inline bool is_mt7663(struct mt76_dev *dev) 171 { 172 return mt76_chip(dev) == 0x7663; 173 } 174 175 static inline bool is_mt7915(struct mt76_dev *dev) 176 { 177 return mt76_chip(dev) == 0x7915; 178 } 179 180 static inline bool is_mt7916(struct mt76_dev *dev) 181 { 182 return mt76_chip(dev) == 0x7906; 183 } 184 185 static inline bool is_mt7986(struct mt76_dev *dev) 186 { 187 return mt76_chip(dev) == 0x7986; 188 } 189 190 static inline bool is_mt7622(struct mt76_dev *dev) 191 { 192 if (!IS_ENABLED(CONFIG_MT7622_WMAC)) 193 return false; 194 195 return mt76_chip(dev) == 0x7622; 196 } 197 198 static inline bool is_mt7615(struct mt76_dev *dev) 199 { 200 return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611; 201 } 202 203 static inline bool is_mt7611(struct mt76_dev *dev) 204 { 205 return mt76_chip(dev) == 0x7611; 206 } 207 208 static inline bool is_connac_v1(struct mt76_dev *dev) 209 { 210 return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev); 211 } 212 213 static inline bool is_mt76_fw_txp(struct mt76_dev *dev) 214 { 215 switch (mt76_chip(dev)) { 216 case 0x7961: 217 case 0x7922: 218 case 0x7663: 219 case 0x7622: 220 return false; 221 default: 222 return true; 223 } 224 } 225 226 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef) 227 { 228 static const u8 width_to_bw[] = { 229 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 230 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 231 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 232 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 233 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 234 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 235 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 236 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 237 }; 238 239 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 240 return 0; 241 242 return width_to_bw[chandef->width]; 243 } 244 245 static inline u8 mt76_connac_lmac_mapping(u8 ac) 246 { 247 /* LMAC uses the reverse order of mac80211 AC indexes */ 248 return 3 - ac; 249 } 250 251 static inline void * 252 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t) 253 { 254 u8 *txwi; 255 256 if (!t) 257 return NULL; 258 259 txwi = mt76_get_txwi_ptr(dev, t); 260 261 return (void *)(txwi + MT_TXD_SIZE); 262 } 263 264 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm); 265 void mt76_connac_power_save_sched(struct mt76_phy *phy, 266 struct mt76_connac_pm *pm); 267 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm, 268 struct mt76_wcid *wcid); 269 270 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev) 271 { 272 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false); 273 dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false); 274 } 275 276 static inline bool 277 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 278 { 279 bool ret = false; 280 281 spin_lock_bh(&pm->wake.lock); 282 if (test_bit(MT76_STATE_PM, &phy->state)) 283 goto out; 284 285 pm->wake.count++; 286 ret = true; 287 out: 288 spin_unlock_bh(&pm->wake.lock); 289 290 return ret; 291 } 292 293 static inline void 294 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm) 295 { 296 spin_lock_bh(&pm->wake.lock); 297 298 pm->last_activity = jiffies; 299 if (--pm->wake.count == 0 && 300 test_bit(MT76_STATE_MCU_RUNNING, &phy->state)) 301 mt76_connac_power_save_sched(phy, pm); 302 303 spin_unlock_bh(&pm->wake.lock); 304 } 305 306 static inline bool 307 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm) 308 { 309 struct mt76_dev *dev = phy->dev; 310 bool ret; 311 312 if (dev->token_count) 313 return true; 314 315 spin_lock_bh(&pm->wake.lock); 316 ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state); 317 spin_unlock_bh(&pm->wake.lock); 318 319 return ret; 320 } 321 322 static inline void 323 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm) 324 __acquires(&dev->mutex) 325 { 326 mutex_lock(&dev->mutex); 327 mt76_connac_pm_wake(&dev->phy, pm); 328 } 329 330 static inline void 331 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm) 332 __releases(&dev->mutex) 333 { 334 mt76_connac_power_save_sched(&dev->phy, pm); 335 mutex_unlock(&dev->mutex); 336 } 337 338 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc, 339 int ring_base, u32 flags); 340 void mt76_connac_write_hw_txp(struct mt76_dev *dev, 341 struct mt76_tx_info *tx_info, 342 void *txp_ptr, u32 id); 343 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev, 344 struct mt76_txwi_cache *txwi); 345 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev, 346 struct mt76_queue_entry *e); 347 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw, 348 struct mt76_connac_pm *pm, 349 struct mt76_wcid *wcid, 350 struct sk_buff *skb); 351 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy, 352 struct mt76_connac_pm *pm); 353 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 354 struct sk_buff *skb, struct mt76_wcid *wcid, 355 struct ieee80211_key_conf *key, int pid, 356 enum mt76_txq_id qid, u32 changed); 357 bool mt76_connac2_mac_fill_txs(struct mt76_dev *dev, struct mt76_wcid *wcid, 358 __le32 *txs_data); 359 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid, 360 int pid, __le32 *txs_data); 361 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev, 362 struct sk_buff *skb, 363 __le32 *rxv, u32 mode); 364 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif, 365 struct sk_buff *skb, u16 hdr_offset); 366 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev, 367 struct mt76_rx_status *status, 368 struct ieee80211_supported_band *sband, 369 __le32 *rxv, u8 *mode); 370 371 #endif /* __MT76_CONNAC_H */ 372