1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 #define MAX_RXDMA_PER_PDEV 2 12 13 struct ath11k_base; 14 struct ath11k_peer; 15 struct ath11k_dp; 16 struct ath11k_vif; 17 struct hal_tcl_status_ring; 18 struct ath11k_ext_irq_grp; 19 20 struct dp_rx_tid { 21 u8 tid; 22 u32 *vaddr; 23 dma_addr_t paddr; 24 u32 size; 25 u32 ba_win_sz; 26 bool active; 27 28 /* Info related to rx fragments */ 29 u32 cur_sn; 30 u16 last_frag_no; 31 u16 rx_frag_bitmap; 32 33 struct sk_buff_head rx_frags; 34 struct hal_reo_dest_ring *dst_ring_desc; 35 36 /* Timer info related to fragments */ 37 struct timer_list frag_timer; 38 struct ath11k_base *ab; 39 }; 40 41 #define DP_REO_DESC_FREE_THRESHOLD 64 42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 43 #define DP_MON_PURGE_TIMEOUT_MS 100 44 #define DP_MON_SERVICE_BUDGET 128 45 46 struct dp_reo_cache_flush_elem { 47 struct list_head list; 48 struct dp_rx_tid data; 49 unsigned long ts; 50 }; 51 52 struct dp_reo_cmd { 53 struct list_head list; 54 struct dp_rx_tid data; 55 int cmd_num; 56 void (*handler)(struct ath11k_dp *, void *, 57 enum hal_reo_cmd_status status); 58 }; 59 60 struct dp_srng { 61 u32 *vaddr_unaligned; 62 u32 *vaddr; 63 dma_addr_t paddr_unaligned; 64 dma_addr_t paddr; 65 int size; 66 u32 ring_id; 67 u8 cached; 68 }; 69 70 struct dp_rxdma_ring { 71 struct dp_srng refill_buf_ring; 72 struct idr bufs_idr; 73 /* Protects bufs_idr */ 74 spinlock_t idr_lock; 75 int bufs_max; 76 }; 77 78 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 79 80 struct dp_tx_ring { 81 u8 tcl_data_ring_id; 82 struct dp_srng tcl_data_ring; 83 struct dp_srng tcl_comp_ring; 84 struct idr txbuf_idr; 85 /* Protects txbuf_idr and num_pending */ 86 spinlock_t tx_idr_lock; 87 struct hal_wbm_release_ring *tx_status; 88 int tx_status_head; 89 int tx_status_tail; 90 }; 91 92 enum dp_mon_status_buf_state { 93 /* PPDU id matches in dst ring and status ring */ 94 DP_MON_STATUS_MATCH, 95 /* status ring dma is not done */ 96 DP_MON_STATUS_NO_DMA, 97 /* status ring is lagging, reap status ring */ 98 DP_MON_STATUS_LAG, 99 /* status ring is leading, reap dst ring and drop */ 100 DP_MON_STATUS_LEAD, 101 /* replinish monitor status ring */ 102 DP_MON_STATUS_REPLINISH, 103 }; 104 105 struct ath11k_pdev_mon_stats { 106 u32 status_ppdu_state; 107 u32 status_ppdu_start; 108 u32 status_ppdu_end; 109 u32 status_ppdu_compl; 110 u32 status_ppdu_start_mis; 111 u32 status_ppdu_end_mis; 112 u32 status_ppdu_done; 113 u32 dest_ppdu_done; 114 u32 dest_mpdu_done; 115 u32 dest_mpdu_drop; 116 u32 dup_mon_linkdesc_cnt; 117 u32 dup_mon_buf_cnt; 118 }; 119 120 struct dp_full_mon_mpdu { 121 struct list_head list; 122 struct sk_buff *head; 123 struct sk_buff *tail; 124 }; 125 126 struct dp_link_desc_bank { 127 void *vaddr_unaligned; 128 void *vaddr; 129 dma_addr_t paddr_unaligned; 130 dma_addr_t paddr; 131 u32 size; 132 }; 133 134 /* Size to enforce scatter idle list mode */ 135 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 136 #define DP_LINK_DESC_BANKS_MAX 8 137 138 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 139 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 140 #define DP_RX_DESC_COOKIE_MAX \ 141 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 142 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 143 144 enum ath11k_dp_ppdu_state { 145 DP_PPDU_STATUS_START, 146 DP_PPDU_STATUS_DONE, 147 }; 148 149 struct ath11k_mon_data { 150 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 151 struct hal_rx_mon_ppdu_info mon_ppdu_info; 152 153 u32 mon_ppdu_status; 154 u32 mon_last_buf_cookie; 155 u64 mon_last_linkdesc_paddr; 156 u16 chan_noise_floor; 157 bool hold_mon_dst_ring; 158 enum dp_mon_status_buf_state buf_state; 159 dma_addr_t mon_status_paddr; 160 struct dp_full_mon_mpdu *mon_mpdu; 161 struct hal_sw_mon_ring_entries sw_mon_entries; 162 struct ath11k_pdev_mon_stats rx_mon_stats; 163 /* lock for monitor data */ 164 spinlock_t mon_lock; 165 struct sk_buff_head rx_status_q; 166 }; 167 168 struct ath11k_pdev_dp { 169 u32 mac_id; 170 atomic_t num_tx_pending; 171 wait_queue_head_t tx_empty_waitq; 172 struct dp_rxdma_ring rx_refill_buf_ring; 173 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 174 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 175 struct dp_srng rxdma_mon_dst_ring; 176 struct dp_srng rxdma_mon_desc_ring; 177 178 struct dp_rxdma_ring rxdma_mon_buf_ring; 179 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 180 struct ieee80211_rx_status rx_status; 181 struct ath11k_mon_data mon_data; 182 }; 183 184 #define DP_NUM_CLIENTS_MAX 64 185 #define DP_AVG_TIDS_PER_CLIENT 2 186 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 187 #define DP_AVG_MSDUS_PER_FLOW 128 188 #define DP_AVG_FLOWS_PER_TID 2 189 #define DP_AVG_MPDUS_PER_TID_MAX 128 190 #define DP_AVG_MSDUS_PER_MPDU 4 191 192 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 193 194 #define DP_BA_WIN_SZ_MAX 256 195 196 #define DP_TCL_NUM_RING_MAX 3 197 #define DP_TCL_NUM_RING_MAX_QCA6390 1 198 199 #define DP_IDLE_SCATTER_BUFS_MAX 16 200 201 #define DP_WBM_RELEASE_RING_SIZE 64 202 #define DP_TCL_DATA_RING_SIZE 512 203 #define DP_TX_COMP_RING_SIZE 32768 204 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 205 #define DP_TCL_CMD_RING_SIZE 32 206 #define DP_TCL_STATUS_RING_SIZE 32 207 #define DP_REO_DST_RING_MAX 4 208 #define DP_REO_DST_RING_SIZE 2048 209 #define DP_REO_REINJECT_RING_SIZE 32 210 #define DP_RX_RELEASE_RING_SIZE 1024 211 #define DP_REO_EXCEPTION_RING_SIZE 128 212 #define DP_REO_CMD_RING_SIZE 128 213 #define DP_REO_STATUS_RING_SIZE 2048 214 #define DP_RXDMA_BUF_RING_SIZE 4096 215 #define DP_RXDMA_REFILL_RING_SIZE 2048 216 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 217 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 218 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 219 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 220 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 221 222 #define DP_RX_BUFFER_SIZE 2048 223 #define DP_RX_BUFFER_SIZE_LITE 1024 224 #define DP_RX_BUFFER_ALIGN_SIZE 128 225 226 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 227 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 228 229 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 230 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 231 232 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 233 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 234 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 235 236 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 237 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 238 239 struct ath11k_hp_update_timer { 240 struct timer_list timer; 241 bool started; 242 bool init; 243 u32 tx_num; 244 u32 timer_tx_num; 245 u32 ring_id; 246 u32 interval; 247 struct ath11k_base *ab; 248 }; 249 250 struct ath11k_dp { 251 struct ath11k_base *ab; 252 enum ath11k_htc_ep_id eid; 253 struct completion htt_tgt_version_received; 254 u8 htt_tgt_ver_major; 255 u8 htt_tgt_ver_minor; 256 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 257 struct dp_srng wbm_idle_ring; 258 struct dp_srng wbm_desc_rel_ring; 259 struct dp_srng tcl_cmd_ring; 260 struct dp_srng tcl_status_ring; 261 struct dp_srng reo_reinject_ring; 262 struct dp_srng rx_rel_ring; 263 struct dp_srng reo_except_ring; 264 struct dp_srng reo_cmd_ring; 265 struct dp_srng reo_status_ring; 266 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 267 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 268 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 269 struct list_head reo_cmd_list; 270 struct list_head reo_cmd_cache_flush_list; 271 struct list_head dp_full_mon_mpdu_list; 272 u32 reo_cmd_cache_flush_count; 273 /** 274 * protects access to below fields, 275 * - reo_cmd_list 276 * - reo_cmd_cache_flush_list 277 * - reo_cmd_cache_flush_count 278 */ 279 spinlock_t reo_cmd_lock; 280 struct ath11k_hp_update_timer reo_cmd_timer; 281 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 282 }; 283 284 /* HTT definitions */ 285 286 #define HTT_TCL_META_DATA_TYPE BIT(0) 287 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 288 289 /* vdev meta data */ 290 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 291 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 292 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 293 294 /* peer meta data */ 295 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 296 297 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 298 299 /* HTT tx completion is overlayed in wbm_release_ring */ 300 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 301 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 302 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 303 304 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 305 306 struct htt_tx_wbm_completion { 307 u32 info0; 308 u32 info1; 309 u32 info2; 310 u32 info3; 311 } __packed; 312 313 enum htt_h2t_msg_type { 314 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 315 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 316 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 317 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 318 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 319 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 320 }; 321 322 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 323 324 struct htt_ver_req_cmd { 325 u32 ver_reg_info; 326 } __packed; 327 328 enum htt_srng_ring_type { 329 HTT_HW_TO_SW_RING, 330 HTT_SW_TO_HW_RING, 331 HTT_SW_TO_SW_RING, 332 }; 333 334 enum htt_srng_ring_id { 335 HTT_RXDMA_HOST_BUF_RING, 336 HTT_RXDMA_MONITOR_STATUS_RING, 337 HTT_RXDMA_MONITOR_BUF_RING, 338 HTT_RXDMA_MONITOR_DESC_RING, 339 HTT_RXDMA_MONITOR_DEST_RING, 340 HTT_HOST1_TO_FW_RXBUF_RING, 341 HTT_HOST2_TO_FW_RXBUF_RING, 342 HTT_RXDMA_NON_MONITOR_DEST_RING, 343 }; 344 345 /* host -> target HTT_SRING_SETUP message 346 * 347 * After target is booted up, Host can send SRING setup message for 348 * each host facing LMAC SRING. Target setups up HW registers based 349 * on setup message and confirms back to Host if response_required is set. 350 * Host should wait for confirmation message before sending new SRING 351 * setup message 352 * 353 * The message would appear as follows: 354 * 355 * |31 24|23 20|19|18 16|15|14 8|7 0| 356 * |--------------- +-----------------+----------------+------------------| 357 * | ring_type | ring_id | pdev_id | msg_type | 358 * |----------------------------------------------------------------------| 359 * | ring_base_addr_lo | 360 * |----------------------------------------------------------------------| 361 * | ring_base_addr_hi | 362 * |----------------------------------------------------------------------| 363 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 364 * |----------------------------------------------------------------------| 365 * | ring_head_offset32_remote_addr_lo | 366 * |----------------------------------------------------------------------| 367 * | ring_head_offset32_remote_addr_hi | 368 * |----------------------------------------------------------------------| 369 * | ring_tail_offset32_remote_addr_lo | 370 * |----------------------------------------------------------------------| 371 * | ring_tail_offset32_remote_addr_hi | 372 * |----------------------------------------------------------------------| 373 * | ring_msi_addr_lo | 374 * |----------------------------------------------------------------------| 375 * | ring_msi_addr_hi | 376 * |----------------------------------------------------------------------| 377 * | ring_msi_data | 378 * |----------------------------------------------------------------------| 379 * | intr_timer_th |IM| intr_batch_counter_th | 380 * |----------------------------------------------------------------------| 381 * | reserved |RR|PTCF| intr_low_threshold | 382 * |----------------------------------------------------------------------| 383 * Where 384 * IM = sw_intr_mode 385 * RR = response_required 386 * PTCF = prefetch_timer_cfg 387 * 388 * The message is interpreted as follows: 389 * dword0 - b'0:7 - msg_type: This will be set to 390 * HTT_H2T_MSG_TYPE_SRING_SETUP 391 * b'8:15 - pdev_id: 392 * 0 (for rings at SOC/UMAC level), 393 * 1/2/3 mac id (for rings at LMAC level) 394 * b'16:23 - ring_id: identify which ring is to setup, 395 * more details can be got from enum htt_srng_ring_id 396 * b'24:31 - ring_type: identify type of host rings, 397 * more details can be got from enum htt_srng_ring_type 398 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 399 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 400 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 401 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 402 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 403 * SW_TO_HW_RING. 404 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 405 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 406 * Lower 32 bits of memory address of the remote variable 407 * storing the 4-byte word offset that identifies the head 408 * element within the ring. 409 * (The head offset variable has type u32.) 410 * Valid for HW_TO_SW and SW_TO_SW rings. 411 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 412 * Upper 32 bits of memory address of the remote variable 413 * storing the 4-byte word offset that identifies the head 414 * element within the ring. 415 * (The head offset variable has type u32.) 416 * Valid for HW_TO_SW and SW_TO_SW rings. 417 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 418 * Lower 32 bits of memory address of the remote variable 419 * storing the 4-byte word offset that identifies the tail 420 * element within the ring. 421 * (The tail offset variable has type u32.) 422 * Valid for HW_TO_SW and SW_TO_SW rings. 423 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 424 * Upper 32 bits of memory address of the remote variable 425 * storing the 4-byte word offset that identifies the tail 426 * element within the ring. 427 * (The tail offset variable has type u32.) 428 * Valid for HW_TO_SW and SW_TO_SW rings. 429 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 430 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 431 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 432 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 433 * dword10 - b'0:31 - ring_msi_data: MSI data 434 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 435 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 436 * dword11 - b'0:14 - intr_batch_counter_th: 437 * batch counter threshold is in units of 4-byte words. 438 * HW internally maintains and increments batch count. 439 * (see SRING spec for detail description). 440 * When batch count reaches threshold value, an interrupt 441 * is generated by HW. 442 * b'15 - sw_intr_mode: 443 * This configuration shall be static. 444 * Only programmed at power up. 445 * 0: generate pulse style sw interrupts 446 * 1: generate level style sw interrupts 447 * b'16:31 - intr_timer_th: 448 * The timer init value when timer is idle or is 449 * initialized to start downcounting. 450 * In 8us units (to cover a range of 0 to 524 ms) 451 * dword12 - b'0:15 - intr_low_threshold: 452 * Used only by Consumer ring to generate ring_sw_int_p. 453 * Ring entries low threshold water mark, that is used 454 * in combination with the interrupt timer as well as 455 * the clearing of the level interrupt. 456 * b'16:18 - prefetch_timer_cfg: 457 * Used only by Consumer ring to set timer mode to 458 * support Application prefetch handling. 459 * The external tail offset/pointer will be updated 460 * at following intervals: 461 * 3'b000: (Prefetch feature disabled; used only for debug) 462 * 3'b001: 1 usec 463 * 3'b010: 4 usec 464 * 3'b011: 8 usec (default) 465 * 3'b100: 16 usec 466 * Others: Reserverd 467 * b'19 - response_required: 468 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 469 * b'20:31 - reserved: reserved for future use 470 */ 471 472 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 473 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 474 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 475 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 476 477 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 478 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 479 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 480 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 481 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 482 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 483 484 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 485 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 486 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 487 488 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 489 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 490 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 491 492 struct htt_srng_setup_cmd { 493 u32 info0; 494 u32 ring_base_addr_lo; 495 u32 ring_base_addr_hi; 496 u32 info1; 497 u32 ring_head_off32_remote_addr_lo; 498 u32 ring_head_off32_remote_addr_hi; 499 u32 ring_tail_off32_remote_addr_lo; 500 u32 ring_tail_off32_remote_addr_hi; 501 u32 ring_msi_addr_lo; 502 u32 ring_msi_addr_hi; 503 u32 msi_data; 504 u32 intr_info; 505 u32 info2; 506 } __packed; 507 508 /* host -> target FW PPDU_STATS config message 509 * 510 * @details 511 * The following field definitions describe the format of the HTT host 512 * to target FW for PPDU_STATS_CFG msg. 513 * The message allows the host to configure the PPDU_STATS_IND messages 514 * produced by the target. 515 * 516 * |31 24|23 16|15 8|7 0| 517 * |-----------------------------------------------------------| 518 * | REQ bit mask | pdev_mask | msg type | 519 * |-----------------------------------------------------------| 520 * Header fields: 521 * - MSG_TYPE 522 * Bits 7:0 523 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 524 * Value: 0x11 525 * - PDEV_MASK 526 * Bits 8:15 527 * Purpose: identifies which pdevs this PPDU stats configuration applies to 528 * Value: This is a overloaded field, refer to usage and interpretation of 529 * PDEV in interface document. 530 * Bit 8 : Reserved for SOC stats 531 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 532 * Indicates MACID_MASK in DBS 533 * - REQ_TLV_BIT_MASK 534 * Bits 16:31 535 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 536 * needs to be included in the target's PPDU_STATS_IND messages. 537 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 538 * 539 */ 540 541 struct htt_ppdu_stats_cfg_cmd { 542 u32 msg; 543 } __packed; 544 545 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 546 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 547 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 548 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 549 550 enum htt_ppdu_stats_tag_type { 551 HTT_PPDU_STATS_TAG_COMMON, 552 HTT_PPDU_STATS_TAG_USR_COMMON, 553 HTT_PPDU_STATS_TAG_USR_RATE, 554 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 555 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 556 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 557 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 558 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 559 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 560 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 561 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 562 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 563 HTT_PPDU_STATS_TAG_INFO, 564 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 565 566 /* New TLV's are added above to this line */ 567 HTT_PPDU_STATS_TAG_MAX, 568 }; 569 570 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 571 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 572 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 573 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 574 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 575 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 576 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 577 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 578 579 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 580 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 581 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 582 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 583 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 584 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 585 HTT_PPDU_STATS_TAG_DEFAULT) 586 587 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 588 * 589 * details: 590 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 591 * configure RXDMA rings. 592 * The configuration is per ring based and includes both packet subtypes 593 * and PPDU/MPDU TLVs. 594 * 595 * The message would appear as follows: 596 * 597 * |31 26|25|24|23 16|15 8|7 0| 598 * |-----------------+----------------+----------------+---------------| 599 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 600 * |-------------------------------------------------------------------| 601 * | rsvd2 | ring_buffer_size | 602 * |-------------------------------------------------------------------| 603 * | packet_type_enable_flags_0 | 604 * |-------------------------------------------------------------------| 605 * | packet_type_enable_flags_1 | 606 * |-------------------------------------------------------------------| 607 * | packet_type_enable_flags_2 | 608 * |-------------------------------------------------------------------| 609 * | packet_type_enable_flags_3 | 610 * |-------------------------------------------------------------------| 611 * | tlv_filter_in_flags | 612 * |-------------------------------------------------------------------| 613 * Where: 614 * PS = pkt_swap 615 * SS = status_swap 616 * The message is interpreted as follows: 617 * dword0 - b'0:7 - msg_type: This will be set to 618 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 619 * b'8:15 - pdev_id: 620 * 0 (for rings at SOC/UMAC level), 621 * 1/2/3 mac id (for rings at LMAC level) 622 * b'16:23 - ring_id : Identify the ring to configure. 623 * More details can be got from enum htt_srng_ring_id 624 * b'24 - status_swap: 1 is to swap status TLV 625 * b'25 - pkt_swap: 1 is to swap packet TLV 626 * b'26:31 - rsvd1: reserved for future use 627 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 628 * in byte units. 629 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 630 * - b'16:31 - rsvd2: Reserved for future use 631 * dword2 - b'0:31 - packet_type_enable_flags_0: 632 * Enable MGMT packet from 0b0000 to 0b1001 633 * bits from low to high: FP, MD, MO - 3 bits 634 * FP: Filter_Pass 635 * MD: Monitor_Direct 636 * MO: Monitor_Other 637 * 10 mgmt subtypes * 3 bits -> 30 bits 638 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 639 * dword3 - b'0:31 - packet_type_enable_flags_1: 640 * Enable MGMT packet from 0b1010 to 0b1111 641 * bits from low to high: FP, MD, MO - 3 bits 642 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 643 * dword4 - b'0:31 - packet_type_enable_flags_2: 644 * Enable CTRL packet from 0b0000 to 0b1001 645 * bits from low to high: FP, MD, MO - 3 bits 646 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 647 * dword5 - b'0:31 - packet_type_enable_flags_3: 648 * Enable CTRL packet from 0b1010 to 0b1111, 649 * MCAST_DATA, UCAST_DATA, NULL_DATA 650 * bits from low to high: FP, MD, MO - 3 bits 651 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 652 * dword6 - b'0:31 - tlv_filter_in_flags: 653 * Filter in Attention/MPDU/PPDU/Header/User tlvs 654 * Refer to CFG_TLV_FILTER_IN_FLAG defs 655 */ 656 657 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 658 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 659 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 660 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 661 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 662 663 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 664 665 enum htt_rx_filter_tlv_flags { 666 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 667 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 668 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 669 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 670 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 671 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 672 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 673 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 674 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 675 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 676 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 677 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 678 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 679 }; 680 681 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 682 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 683 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 684 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 685 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 686 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 687 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 688 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 689 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 690 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 691 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 692 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 693 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 694 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 695 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 696 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 697 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 698 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 699 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 700 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 701 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 702 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 703 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 704 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 705 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 706 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 707 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 708 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 709 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 710 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 711 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 712 }; 713 714 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 715 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 716 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 717 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 718 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 719 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 720 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 721 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 722 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 723 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 724 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 725 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 726 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 727 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 728 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 729 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 730 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 731 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 732 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 733 }; 734 735 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 736 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 737 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 738 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 739 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 740 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 741 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 742 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 743 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 744 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 745 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 746 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 747 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 748 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 749 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 750 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 751 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 752 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 753 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 754 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 755 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 756 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 757 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 758 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 759 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 760 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 761 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 762 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 763 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 764 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 765 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 766 }; 767 768 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 769 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 770 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 771 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 772 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 773 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 774 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 775 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 776 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 777 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 778 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 779 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 780 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 781 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 782 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 783 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 784 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 785 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 786 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 787 }; 788 789 enum htt_rx_data_pkt_filter_tlv_flasg3 { 790 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 791 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 792 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 793 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 794 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 795 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 796 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 797 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 798 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 799 }; 800 801 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 802 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 803 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 804 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 805 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 806 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 807 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 808 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 809 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 810 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 811 812 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 813 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 814 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 815 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 816 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 817 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 818 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 819 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 820 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 821 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 822 823 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 824 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 825 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 826 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 827 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 828 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 829 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 830 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 831 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 832 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 833 834 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 835 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 836 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 837 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 838 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 839 840 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 841 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 842 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 843 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 844 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 845 846 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 847 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 848 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 849 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 850 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 851 852 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 853 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 854 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 855 856 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 857 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 858 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 859 860 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 861 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 862 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 863 864 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 865 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 866 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 867 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 868 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 869 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 870 871 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 872 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 873 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 874 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 875 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 876 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 877 878 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 879 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 880 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 881 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 882 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 883 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 884 885 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 886 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 887 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 888 889 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 890 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 891 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 892 893 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 894 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 895 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 896 897 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 898 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 899 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 900 901 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 902 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 903 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 904 905 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 906 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 907 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 908 909 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 910 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 911 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 912 913 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 914 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 915 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 916 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 917 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 918 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 919 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 920 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 921 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 922 923 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 924 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 925 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 926 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 927 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 928 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 929 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 930 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 931 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 932 933 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 934 935 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 936 937 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 938 939 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 940 941 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 942 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 943 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 944 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 945 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 946 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 947 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 948 949 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 950 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 951 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 952 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 953 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 954 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 955 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 956 957 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 958 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 959 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 960 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 961 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 962 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 963 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 964 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 965 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 966 967 struct htt_rx_ring_selection_cfg_cmd { 968 u32 info0; 969 u32 info1; 970 u32 pkt_type_en_flags0; 971 u32 pkt_type_en_flags1; 972 u32 pkt_type_en_flags2; 973 u32 pkt_type_en_flags3; 974 u32 rx_filter_tlv; 975 } __packed; 976 977 struct htt_rx_ring_tlv_filter { 978 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 979 u32 pkt_filter_flags0; /* MGMT */ 980 u32 pkt_filter_flags1; /* MGMT */ 981 u32 pkt_filter_flags2; /* CTRL */ 982 u32 pkt_filter_flags3; /* DATA */ 983 }; 984 985 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 986 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 987 988 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 989 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 990 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 991 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 992 993 /** 994 * Enumeration for full monitor mode destination ring select 995 * 0 - REO destination ring select 996 * 1 - FW destination ring select 997 * 2 - SW destination ring select 998 * 3 - Release destination ring select 999 */ 1000 enum htt_rx_full_mon_release_ring { 1001 HTT_RX_MON_RING_REO, 1002 HTT_RX_MON_RING_FW, 1003 HTT_RX_MON_RING_SW, 1004 HTT_RX_MON_RING_RELEASE, 1005 }; 1006 1007 struct htt_rx_full_monitor_mode_cfg_cmd { 1008 u32 info0; 1009 u32 cfg; 1010 } __packed; 1011 1012 /* HTT message target->host */ 1013 1014 enum htt_t2h_msg_type { 1015 HTT_T2H_MSG_TYPE_VERSION_CONF, 1016 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1017 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1018 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1019 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1020 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1021 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1022 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1023 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1024 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1025 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1026 }; 1027 1028 #define HTT_TARGET_VERSION_MAJOR 3 1029 1030 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1031 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1032 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1033 1034 struct htt_t2h_version_conf_msg { 1035 u32 version; 1036 } __packed; 1037 1038 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1039 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1040 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1041 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1042 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1043 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1044 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1045 1046 struct htt_t2h_peer_map_event { 1047 u32 info; 1048 u32 mac_addr_l32; 1049 u32 info1; 1050 u32 info2; 1051 } __packed; 1052 1053 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1054 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1055 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1056 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1057 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1058 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1059 1060 struct htt_t2h_peer_unmap_event { 1061 u32 info; 1062 u32 mac_addr_l32; 1063 u32 info1; 1064 } __packed; 1065 1066 struct htt_resp_msg { 1067 union { 1068 struct htt_t2h_version_conf_msg version_msg; 1069 struct htt_t2h_peer_map_event peer_map_ev; 1070 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1071 }; 1072 } __packed; 1073 1074 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1075 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1076 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1077 1078 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1079 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1080 1081 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1082 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1083 1084 enum htt_backpressure_umac_ringid { 1085 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1086 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1087 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1088 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1089 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1090 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1091 HTT_SW_RING_IDX_REO_REO2FW_RING, 1092 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1093 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1094 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1095 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1096 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1097 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1098 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1099 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1100 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1101 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1102 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1103 HTT_SW_UMAC_RING_IDX_MAX, 1104 }; 1105 1106 enum htt_backpressure_lmac_ringid { 1107 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1108 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1109 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1110 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1111 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1112 HTT_SW_RING_IDX_RXDMA2FW_RING, 1113 HTT_SW_RING_IDX_RXDMA2SW_RING, 1114 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1115 HTT_SW_RING_IDX_RXDMA2REO_RING, 1116 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1117 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1118 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1119 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1120 HTT_SW_LMAC_RING_IDX_MAX, 1121 }; 1122 1123 /* ppdu stats 1124 * 1125 * @details 1126 * The following field definitions describe the format of the HTT target 1127 * to host ppdu stats indication message. 1128 * 1129 * 1130 * |31 16|15 12|11 10|9 8|7 0 | 1131 * |----------------------------------------------------------------------| 1132 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1133 * |----------------------------------------------------------------------| 1134 * | ppdu_id | 1135 * |----------------------------------------------------------------------| 1136 * | Timestamp in us | 1137 * |----------------------------------------------------------------------| 1138 * | reserved | 1139 * |----------------------------------------------------------------------| 1140 * | type-specific stats info | 1141 * | (see htt_ppdu_stats.h) | 1142 * |----------------------------------------------------------------------| 1143 * Header fields: 1144 * - MSG_TYPE 1145 * Bits 7:0 1146 * Purpose: Identifies this is a PPDU STATS indication 1147 * message. 1148 * Value: 0x1d 1149 * - mac_id 1150 * Bits 9:8 1151 * Purpose: mac_id of this ppdu_id 1152 * Value: 0-3 1153 * - pdev_id 1154 * Bits 11:10 1155 * Purpose: pdev_id of this ppdu_id 1156 * Value: 0-3 1157 * 0 (for rings at SOC level), 1158 * 1/2/3 PDEV -> 0/1/2 1159 * - payload_size 1160 * Bits 31:16 1161 * Purpose: total tlv size 1162 * Value: payload_size in bytes 1163 */ 1164 1165 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1166 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1167 1168 struct ath11k_htt_ppdu_stats_msg { 1169 u32 info; 1170 u32 ppdu_id; 1171 u32 timestamp; 1172 u32 rsvd; 1173 u8 data[0]; 1174 } __packed; 1175 1176 struct htt_tlv { 1177 u32 header; 1178 u8 value[0]; 1179 } __packed; 1180 1181 #define HTT_TLV_TAG GENMASK(11, 0) 1182 #define HTT_TLV_LEN GENMASK(23, 12) 1183 1184 enum HTT_PPDU_STATS_BW { 1185 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1186 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1187 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1188 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1189 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1190 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1191 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1192 }; 1193 1194 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1195 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1196 /* bw - HTT_PPDU_STATS_BW */ 1197 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1198 1199 struct htt_ppdu_stats_common { 1200 u32 ppdu_id; 1201 u16 sched_cmdid; 1202 u8 ring_id; 1203 u8 num_users; 1204 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1205 u32 chain_mask; 1206 u32 fes_duration_us; /* frame exchange sequence */ 1207 u32 ppdu_sch_eval_start_tstmp_us; 1208 u32 ppdu_sch_end_tstmp_us; 1209 u32 ppdu_start_tstmp_us; 1210 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1211 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1212 */ 1213 u16 phy_mode; 1214 u16 bw_mhz; 1215 } __packed; 1216 1217 enum htt_ppdu_stats_gi { 1218 HTT_PPDU_STATS_SGI_0_8_US, 1219 HTT_PPDU_STATS_SGI_0_4_US, 1220 HTT_PPDU_STATS_SGI_1_6_US, 1221 HTT_PPDU_STATS_SGI_3_2_US, 1222 }; 1223 1224 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1225 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1226 1227 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1228 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1229 1230 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1231 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1232 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1233 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1234 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1235 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1236 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1237 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1238 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1239 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1240 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1241 1242 #define HTT_USR_RATE_PREAMBLE(_val) \ 1243 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1244 #define HTT_USR_RATE_BW(_val) \ 1245 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1246 #define HTT_USR_RATE_NSS(_val) \ 1247 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1248 #define HTT_USR_RATE_MCS(_val) \ 1249 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1250 #define HTT_USR_RATE_GI(_val) \ 1251 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1252 #define HTT_USR_RATE_DCM(_val) \ 1253 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1254 1255 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1256 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1257 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1258 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1259 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1260 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1261 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1262 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1263 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1264 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1265 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1266 1267 struct htt_ppdu_stats_user_rate { 1268 u8 tid_num; 1269 u8 reserved0; 1270 u16 sw_peer_id; 1271 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1272 u16 ru_end; 1273 u16 ru_start; 1274 u16 resp_ru_end; 1275 u16 resp_ru_start; 1276 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1277 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1278 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1279 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1280 } __packed; 1281 1282 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1283 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1284 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1285 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1286 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1287 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1288 1289 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1290 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1291 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1292 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1293 #define HTT_TX_INFO_RATECODE(_flags) \ 1294 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1295 #define HTT_TX_INFO_PEERID(_flags) \ 1296 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1297 1298 struct htt_tx_ppdu_stats_info { 1299 struct htt_tlv tlv_hdr; 1300 u32 tx_success_bytes; 1301 u32 tx_retry_bytes; 1302 u32 tx_failed_bytes; 1303 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1304 u16 tx_success_msdus; 1305 u16 tx_retry_msdus; 1306 u16 tx_failed_msdus; 1307 u16 tx_duration; /* united in us */ 1308 } __packed; 1309 1310 enum htt_ppdu_stats_usr_compln_status { 1311 HTT_PPDU_STATS_USER_STATUS_OK, 1312 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1313 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1314 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1315 HTT_PPDU_STATS_USER_STATUS_ABORT, 1316 }; 1317 1318 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1319 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1320 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1321 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1322 1323 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1324 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1325 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1326 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1327 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1328 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1329 1330 struct htt_ppdu_stats_usr_cmpltn_cmn { 1331 u8 status; 1332 u8 tid_num; 1333 u16 sw_peer_id; 1334 /* RSSI value of last ack packet (units = dB above noise floor) */ 1335 u32 ack_rssi; 1336 u16 mpdu_tried; 1337 u16 mpdu_success; 1338 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1339 } __packed; 1340 1341 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1342 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1343 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1344 1345 #define HTT_PPDU_STATS_NON_QOS_TID 16 1346 1347 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1348 u32 ppdu_id; 1349 u16 sw_peer_id; 1350 u16 reserved0; 1351 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1352 u16 current_seq; 1353 u16 start_seq; 1354 u32 success_bytes; 1355 } __packed; 1356 1357 struct htt_ppdu_stats_usr_cmn_array { 1358 struct htt_tlv tlv_hdr; 1359 u32 num_ppdu_stats; 1360 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1361 * elements. 1362 * tx_ppdu_stats_info is variable length, with length = 1363 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1364 */ 1365 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1366 } __packed; 1367 1368 struct htt_ppdu_user_stats { 1369 u16 peer_id; 1370 u32 tlv_flags; 1371 bool is_valid_peer_id; 1372 struct htt_ppdu_stats_user_rate rate; 1373 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1374 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1375 }; 1376 1377 #define HTT_PPDU_STATS_MAX_USERS 8 1378 #define HTT_PPDU_DESC_MAX_DEPTH 16 1379 1380 struct htt_ppdu_stats { 1381 struct htt_ppdu_stats_common common; 1382 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1383 }; 1384 1385 struct htt_ppdu_stats_info { 1386 u32 ppdu_id; 1387 struct htt_ppdu_stats ppdu_stats; 1388 struct list_head list; 1389 }; 1390 1391 /** 1392 * @brief target -> host packet log message 1393 * 1394 * @details 1395 * The following field definitions describe the format of the packet log 1396 * message sent from the target to the host. 1397 * The message consists of a 4-octet header,followed by a variable number 1398 * of 32-bit character values. 1399 * 1400 * |31 16|15 12|11 10|9 8|7 0| 1401 * |------------------------------------------------------------------| 1402 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1403 * |------------------------------------------------------------------| 1404 * | payload | 1405 * |------------------------------------------------------------------| 1406 * - MSG_TYPE 1407 * Bits 7:0 1408 * Purpose: identifies this as a pktlog message 1409 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1410 * - mac_id 1411 * Bits 9:8 1412 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1413 * Value: 0-3 1414 * - pdev_id 1415 * Bits 11:10 1416 * Purpose: pdev_id 1417 * Value: 0-3 1418 * 0 (for rings at SOC level), 1419 * 1/2/3 PDEV -> 0/1/2 1420 * - payload_size 1421 * Bits 31:16 1422 * Purpose: explicitly specify the payload size 1423 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1424 */ 1425 struct htt_pktlog_msg { 1426 u32 hdr; 1427 u8 payload[0]; 1428 }; 1429 1430 /** 1431 * @brief host -> target FW extended statistics retrieve 1432 * 1433 * @details 1434 * The following field definitions describe the format of the HTT host 1435 * to target FW extended stats retrieve message. 1436 * The message specifies the type of stats the host wants to retrieve. 1437 * 1438 * |31 24|23 16|15 8|7 0| 1439 * |-----------------------------------------------------------| 1440 * | reserved | stats type | pdev_mask | msg type | 1441 * |-----------------------------------------------------------| 1442 * | config param [0] | 1443 * |-----------------------------------------------------------| 1444 * | config param [1] | 1445 * |-----------------------------------------------------------| 1446 * | config param [2] | 1447 * |-----------------------------------------------------------| 1448 * | config param [3] | 1449 * |-----------------------------------------------------------| 1450 * | reserved | 1451 * |-----------------------------------------------------------| 1452 * | cookie LSBs | 1453 * |-----------------------------------------------------------| 1454 * | cookie MSBs | 1455 * |-----------------------------------------------------------| 1456 * Header fields: 1457 * - MSG_TYPE 1458 * Bits 7:0 1459 * Purpose: identifies this is a extended stats upload request message 1460 * Value: 0x10 1461 * - PDEV_MASK 1462 * Bits 8:15 1463 * Purpose: identifies the mask of PDEVs to retrieve stats from 1464 * Value: This is a overloaded field, refer to usage and interpretation of 1465 * PDEV in interface document. 1466 * Bit 8 : Reserved for SOC stats 1467 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1468 * Indicates MACID_MASK in DBS 1469 * - STATS_TYPE 1470 * Bits 23:16 1471 * Purpose: identifies which FW statistics to upload 1472 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1473 * - Reserved 1474 * Bits 31:24 1475 * - CONFIG_PARAM [0] 1476 * Bits 31:0 1477 * Purpose: give an opaque configuration value to the specified stats type 1478 * Value: stats-type specific configuration value 1479 * Refer to htt_stats.h for interpretation for each stats sub_type 1480 * - CONFIG_PARAM [1] 1481 * Bits 31:0 1482 * Purpose: give an opaque configuration value to the specified stats type 1483 * Value: stats-type specific configuration value 1484 * Refer to htt_stats.h for interpretation for each stats sub_type 1485 * - CONFIG_PARAM [2] 1486 * Bits 31:0 1487 * Purpose: give an opaque configuration value to the specified stats type 1488 * Value: stats-type specific configuration value 1489 * Refer to htt_stats.h for interpretation for each stats sub_type 1490 * - CONFIG_PARAM [3] 1491 * Bits 31:0 1492 * Purpose: give an opaque configuration value to the specified stats type 1493 * Value: stats-type specific configuration value 1494 * Refer to htt_stats.h for interpretation for each stats sub_type 1495 * - Reserved [31:0] for future use. 1496 * - COOKIE_LSBS 1497 * Bits 31:0 1498 * Purpose: Provide a mechanism to match a target->host stats confirmation 1499 * message with its preceding host->target stats request message. 1500 * Value: LSBs of the opaque cookie specified by the host-side requestor 1501 * - COOKIE_MSBS 1502 * Bits 31:0 1503 * Purpose: Provide a mechanism to match a target->host stats confirmation 1504 * message with its preceding host->target stats request message. 1505 * Value: MSBs of the opaque cookie specified by the host-side requestor 1506 */ 1507 1508 struct htt_ext_stats_cfg_hdr { 1509 u8 msg_type; 1510 u8 pdev_mask; 1511 u8 stats_type; 1512 u8 reserved; 1513 } __packed; 1514 1515 struct htt_ext_stats_cfg_cmd { 1516 struct htt_ext_stats_cfg_hdr hdr; 1517 u32 cfg_param0; 1518 u32 cfg_param1; 1519 u32 cfg_param2; 1520 u32 cfg_param3; 1521 u32 reserved; 1522 u32 cookie_lsb; 1523 u32 cookie_msb; 1524 } __packed; 1525 1526 /* htt stats config default params */ 1527 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1528 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1529 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1530 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1531 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1532 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1533 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1534 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1535 1536 /* HTT_DBG_EXT_STATS_PEER_INFO 1537 * PARAMS: 1538 * @config_param0: 1539 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1540 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1541 * [Bit31 : Bit16] sw_peer_id 1542 * @config_param1: 1543 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1544 * 0 bit htt_peer_stats_cmn_tlv 1545 * 1 bit htt_peer_details_tlv 1546 * 2 bit htt_tx_peer_rate_stats_tlv 1547 * 3 bit htt_rx_peer_rate_stats_tlv 1548 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1549 * 5 bit htt_rx_tid_stats_tlv 1550 * 6 bit htt_msdu_flow_stats_tlv 1551 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1552 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1553 * [Bit31 : Bit16] reserved 1554 */ 1555 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1556 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1557 1558 /* Used to set different configs to the specified stats type.*/ 1559 struct htt_ext_stats_cfg_params { 1560 u32 cfg0; 1561 u32 cfg1; 1562 u32 cfg2; 1563 u32 cfg3; 1564 }; 1565 1566 /** 1567 * @brief target -> host extended statistics upload 1568 * 1569 * @details 1570 * The following field definitions describe the format of the HTT target 1571 * to host stats upload confirmation message. 1572 * The message contains a cookie echoed from the HTT host->target stats 1573 * upload request, which identifies which request the confirmation is 1574 * for, and a single stats can span over multiple HTT stats indication 1575 * due to the HTT message size limitation so every HTT ext stats indication 1576 * will have tag-length-value stats information elements. 1577 * The tag-length header for each HTT stats IND message also includes a 1578 * status field, to indicate whether the request for the stat type in 1579 * question was fully met, partially met, unable to be met, or invalid 1580 * (if the stat type in question is disabled in the target). 1581 * A Done bit 1's indicate the end of the of stats info elements. 1582 * 1583 * 1584 * |31 16|15 12|11|10 8|7 5|4 0| 1585 * |--------------------------------------------------------------| 1586 * | reserved | msg type | 1587 * |--------------------------------------------------------------| 1588 * | cookie LSBs | 1589 * |--------------------------------------------------------------| 1590 * | cookie MSBs | 1591 * |--------------------------------------------------------------| 1592 * | stats entry length | rsvd | D| S | stat type | 1593 * |--------------------------------------------------------------| 1594 * | type-specific stats info | 1595 * | (see htt_stats.h) | 1596 * |--------------------------------------------------------------| 1597 * Header fields: 1598 * - MSG_TYPE 1599 * Bits 7:0 1600 * Purpose: Identifies this is a extended statistics upload confirmation 1601 * message. 1602 * Value: 0x1c 1603 * - COOKIE_LSBS 1604 * Bits 31:0 1605 * Purpose: Provide a mechanism to match a target->host stats confirmation 1606 * message with its preceding host->target stats request message. 1607 * Value: LSBs of the opaque cookie specified by the host-side requestor 1608 * - COOKIE_MSBS 1609 * Bits 31:0 1610 * Purpose: Provide a mechanism to match a target->host stats confirmation 1611 * message with its preceding host->target stats request message. 1612 * Value: MSBs of the opaque cookie specified by the host-side requestor 1613 * 1614 * Stats Information Element tag-length header fields: 1615 * - STAT_TYPE 1616 * Bits 7:0 1617 * Purpose: identifies the type of statistics info held in the 1618 * following information element 1619 * Value: htt_dbg_ext_stats_type 1620 * - STATUS 1621 * Bits 10:8 1622 * Purpose: indicate whether the requested stats are present 1623 * Value: htt_dbg_ext_stats_status 1624 * - DONE 1625 * Bits 11 1626 * Purpose: 1627 * Indicates the completion of the stats entry, this will be the last 1628 * stats conf HTT segment for the requested stats type. 1629 * Value: 1630 * 0 -> the stats retrieval is ongoing 1631 * 1 -> the stats retrieval is complete 1632 * - LENGTH 1633 * Bits 31:16 1634 * Purpose: indicate the stats information size 1635 * Value: This field specifies the number of bytes of stats information 1636 * that follows the element tag-length header. 1637 * It is expected but not required that this length is a multiple of 1638 * 4 bytes. 1639 */ 1640 1641 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1642 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1643 1644 struct ath11k_htt_extd_stats_msg { 1645 u32 info0; 1646 u64 cookie; 1647 u32 info1; 1648 u8 data[0]; 1649 } __packed; 1650 1651 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1652 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1653 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1654 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1655 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1656 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1657 1658 struct htt_mac_addr { 1659 u32 mac_addr_l32; 1660 u32 mac_addr_h16; 1661 }; 1662 1663 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1664 { 1665 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1666 addr_l32 = swab32(addr_l32); 1667 addr_h16 = swab16(addr_h16); 1668 } 1669 1670 memcpy(addr, &addr_l32, 4); 1671 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1672 } 1673 1674 int ath11k_dp_service_srng(struct ath11k_base *ab, 1675 struct ath11k_ext_irq_grp *irq_grp, 1676 int budget); 1677 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1678 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1679 void ath11k_dp_free(struct ath11k_base *ab); 1680 int ath11k_dp_alloc(struct ath11k_base *ab); 1681 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1682 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1683 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1684 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1685 int mac_id, enum hal_ring_type ring_type); 1686 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1687 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1688 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1689 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1690 enum hal_ring_type type, int ring_num, 1691 int mac_id, int num_entries); 1692 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1693 struct dp_link_desc_bank *desc_bank, 1694 u32 ring_type, struct dp_srng *ring); 1695 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1696 struct dp_link_desc_bank *link_desc_banks, 1697 u32 ring_type, struct hal_srng *srng, 1698 u32 n_link_desc); 1699 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1700 struct hal_srng *srng, 1701 struct ath11k_hp_update_timer *update_timer); 1702 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1703 struct ath11k_hp_update_timer *update_timer); 1704 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1705 struct ath11k_hp_update_timer *update_timer, 1706 u32 interval, u32 ring_id); 1707 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1708 1709 #endif 1710