1 /******************************************************************************* 2 Copyright (C) 2015 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /** 37 * @defgroup group_udma_config UDMA Config 38 * @ingroup group_udma_api 39 * UDMA Config API 40 * @{ 41 * @file al_hal_udma_config.h 42 * 43 * @brief C Header file for the Universal DMA HAL driver for configuration APIs 44 * 45 */ 46 47 #ifndef __AL_HAL_UDMA_CONFIG_H__ 48 #define __AL_HAL_UDMA_CONFIG_H__ 49 50 #include <al_hal_udma.h> 51 52 53 /* *INDENT-OFF* */ 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 /* *INDENT-ON* */ 58 59 /** Scheduling mode */ 60 enum al_udma_sch_mode { 61 STRICT, /* Strict */ 62 SRR, /* Simple Sound Rubin */ 63 DWRR /* Deficit Weighted Round Rubin */ 64 }; 65 66 /** AXI configuration */ 67 struct al_udma_axi_conf { 68 uint32_t axi_timeout; /* Timeout for AXI transactions */ 69 uint8_t arb_promotion; /* arbitration promotion */ 70 al_bool swap_8_bytes; /* enable 8 bytes swap instead of 4 bytes */ 71 al_bool swap_s2m_data; 72 al_bool swap_s2m_desc; 73 al_bool swap_m2s_data; 74 al_bool swap_m2s_desc; 75 }; 76 77 /** UDMA AXI M2S configuration */ 78 struct al_udma_axi_submaster { 79 uint8_t id; /* AXI ID */ 80 uint8_t cache_type; 81 uint8_t burst; 82 uint16_t used_ext; 83 uint8_t bus_size; 84 uint8_t qos; 85 uint8_t prot; 86 uint8_t max_beats; 87 }; 88 89 /** UDMA AXI M2S configuration */ 90 struct al_udma_m2s_axi_conf { 91 struct al_udma_axi_submaster comp_write; 92 struct al_udma_axi_submaster data_read; 93 struct al_udma_axi_submaster desc_read; 94 al_bool break_on_max_boundary; /* Data read break on max boundary */ 95 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */ 96 uint8_t ostand_max_data_read; 97 uint8_t ostand_max_desc_read; 98 uint8_t ostand_max_comp_req; 99 uint8_t ostand_max_comp_write; 100 }; 101 102 /** UDMA AXI S2M configuration */ 103 struct al_udma_s2m_axi_conf { 104 struct al_udma_axi_submaster data_write; 105 struct al_udma_axi_submaster desc_read; 106 struct al_udma_axi_submaster comp_write; 107 al_bool break_on_max_boundary; /* Data read break on max boundary */ 108 uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */ 109 uint8_t ostand_max_data_req; 110 uint8_t ostand_max_data_write; 111 uint8_t ostand_max_comp_req; 112 uint8_t ostand_max_comp_write; 113 uint8_t ostand_max_desc_read; 114 uint8_t ack_fifo_depth; /* size of the stream application ack fifo */ 115 }; 116 117 /** M2S error logging */ 118 struct al_udma_err_log { 119 uint32_t error_status; 120 uint32_t header[4]; 121 }; 122 123 /** M2S max packet size configuration */ 124 struct al_udma_m2s_pkt_len_conf { 125 uint32_t max_pkt_size; 126 al_bool encode_64k_as_zero; 127 }; 128 129 /** M2S Descriptor Prefetch configuration */ 130 struct al_udma_m2s_desc_pref_conf { 131 uint8_t desc_fifo_depth; 132 enum al_udma_sch_mode sch_mode; /* Scheduling mode 133 * (either strict or RR) */ 134 135 uint8_t max_desc_per_packet; /* max number of descriptors to 136 * prefetch */ 137 /* in one burst (5b) */ 138 uint8_t pref_thr; 139 uint8_t min_burst_above_thr; /* min burst size when fifo above 140 * pref_thr (4b) 141 */ 142 uint8_t min_burst_below_thr; /* min burst size when fifo below 143 * pref_thr (4b) 144 */ 145 uint8_t max_pkt_limit; /* maximum number of packets in the data 146 * read FIFO, defined based on header 147 * FIFO size 148 */ 149 uint16_t data_fifo_depth; /* maximum number of data beats in the 150 * data read FIFO, 151 * defined based on header FIFO size 152 */ 153 }; 154 155 /** S2M Descriptor Prefetch configuration */ 156 struct al_udma_s2m_desc_pref_conf { 157 uint8_t desc_fifo_depth; 158 enum al_udma_sch_mode sch_mode; /* Scheduling mode * 159 * (either strict or RR) 160 */ 161 162 al_bool q_promotion; /* enable promotion */ 163 al_bool force_promotion; /* force promotion */ 164 al_bool en_pref_prediction; /* enable prefetch prediction */ 165 uint8_t promotion_th; /* Threshold for queue promotion */ 166 167 uint8_t pref_thr; 168 uint8_t min_burst_above_thr; /* min burst size when fifo above 169 * pref_thr (4b) 170 */ 171 uint8_t min_burst_below_thr; /* min burst size when fifo below 172 * pref_thr (4b) 173 */ 174 uint8_t a_full_thr; /* almost full threshold */ 175 }; 176 177 /** S2M Data write configuration */ 178 struct al_udma_s2m_data_write_conf { 179 uint16_t data_fifo_depth; /* maximum number of data beats in the 180 * data write FIFO, defined based on 181 * header FIFO size 182 */ 183 uint8_t max_pkt_limit; /* maximum number of packets in the 184 * data write FIFO,defined based on 185 * header FIFO size 186 */ 187 uint8_t fifo_margin; 188 uint32_t desc_wait_timer; /* waiting time for the host to write 189 * new descriptor to the queue 190 * (for the current packet in process) 191 */ 192 uint32_t flags; /* bitwise of flags of s2m 193 * data_cfg_2 register 194 */ 195 }; 196 197 /** S2M Completion configuration */ 198 struct al_udma_s2m_completion_conf { 199 uint8_t desc_size; /* Size of completion descriptor 200 * in words 201 */ 202 al_bool cnt_words; /* Completion fifo in use counter: 203 * AL_TRUE words, AL_FALS descriptors 204 */ 205 al_bool q_promotion; /* Enable promotion of the current 206 * unack in progress */ 207 /* in the completion write scheduler */ 208 al_bool force_rr; /* force RR arbitration in the 209 * scheduler 210 */ 211 // uint8_t ack_fifo_depth; /* size of the stream application ack fifo */ 212 uint8_t q_free_min; /* minimum number of free completion 213 * entries 214 */ 215 /* to qualify for promotion */ 216 217 uint16_t comp_fifo_depth; /* Size of completion fifo in words */ 218 uint16_t unack_fifo_depth; /* Size of unacked fifo in descs */ 219 uint32_t timeout; /* Ack timout from stream interface */ 220 }; 221 222 /** M2S UDMA DWRR configuration */ 223 struct al_udma_m2s_dwrr_conf { 224 al_bool enable_dwrr; 225 uint8_t inc_factor; 226 uint8_t weight; 227 al_bool pkt_mode; 228 uint32_t deficit_init_val; 229 }; 230 231 /** M2S DMA Rate Limitation mode */ 232 struct al_udma_m2s_rlimit_mode { 233 al_bool pkt_mode_en; 234 uint16_t short_cycle_sz; 235 uint32_t token_init_val; 236 }; 237 238 /** M2S Stream/Q Rate Limitation */ 239 struct al_udma_m2s_rlimit_cfg { 240 uint32_t max_burst_sz; /* maximum number of accumulated bytes in the 241 * token counter 242 */ 243 uint16_t long_cycle_sz; /* number of short cycles between token fill */ 244 uint32_t long_cycle; /* number of bits to add in each long cycle */ 245 uint32_t short_cycle; /* number of bits to add in each cycle */ 246 uint32_t mask; /* mask the different types of rate limiters */ 247 }; 248 249 enum al_udma_m2s_rlimit_action { 250 AL_UDMA_STRM_RLIMIT_ENABLE, 251 AL_UDMA_STRM_RLIMIT_PAUSE, 252 AL_UDMA_STRM_RLIMIT_RESET 253 }; 254 255 /** M2S UDMA Q scheduling configuration */ 256 struct al_udma_m2s_q_dwrr_conf { 257 uint32_t max_deficit_cnt_sz; /*maximum number of accumulated bytes 258 * in the deficit counter 259 */ 260 al_bool strict; /* bypass DWRR */ 261 uint8_t axi_qos; 262 uint16_t q_qos; 263 uint8_t weight; 264 }; 265 266 /** M2S UDMA / UDMA Q scheduling configuration */ 267 struct al_udma_m2s_sc { 268 enum al_udma_sch_mode sch_mode; /* Scheduling Mode */ 269 struct al_udma_m2s_dwrr_conf dwrr; /* DWRR configuration */ 270 }; 271 272 /** UDMA / UDMA Q rate limitation configuration */ 273 struct al_udma_m2s_rlimit { 274 struct al_udma_m2s_rlimit_mode rlimit_mode; 275 /* rate limitation enablers */ 276 #if 0 277 struct al_udma_tkn_bkt_conf token_bkt; /* Token Bucket configuration */ 278 #endif 279 }; 280 281 /** UDMA Data read configuration */ 282 struct al_udma_m2s_data_rd_conf { 283 uint8_t max_rd_d_beats; /* max burst size for reading data 284 * (in AXI beats-128b) (5b) 285 */ 286 uint8_t max_rd_d_out_req; /* max number of outstanding data 287 * read requests (6b) 288 */ 289 uint16_t max_rd_d_out_beats; /* max num. of data read beats (10b) */ 290 }; 291 292 /** M2S UDMA completion and application timeouts */ 293 struct al_udma_m2s_comp_timeouts { 294 enum al_udma_sch_mode sch_mode; /* Scheduling mode 295 * (either strict or RR) 296 */ 297 al_bool enable_q_promotion; 298 uint8_t unack_fifo_depth; /* unacked desc fifo size */ 299 uint8_t comp_fifo_depth; /* desc fifo size */ 300 uint32_t coal_timeout; /* (24b) */ 301 uint32_t app_timeout; /* (24b) */ 302 }; 303 304 /** S2M UDMA per queue completion configuration */ 305 struct al_udma_s2m_q_comp_conf { 306 al_bool dis_comp_coal; /* disable completion coalescing */ 307 al_bool en_comp_ring_update; /* enable writing completion descs */ 308 uint32_t comp_timer; /* completion coalescing timer */ 309 al_bool en_hdr_split; /* enable header split */ 310 al_bool force_hdr_split; /* force header split */ 311 uint16_t hdr_split_size; /* size used for the header split */ 312 uint8_t q_qos; /* queue QoS */ 313 }; 314 315 /** UDMA per queue Target-ID control configuration */ 316 struct al_udma_gen_tgtid_q_conf { 317 /* Enable usage of the Target-ID per queue according to 'tgtid' */ 318 al_bool queue_en; 319 320 /* Enable usage of the Target-ID from the descriptor buffer address 63:48 */ 321 al_bool desc_en; 322 323 /* Target-ID to be applied when 'queue_en' is asserted */ 324 uint16_t tgtid; 325 326 /* TGTADDR to be applied to msbs when 'desc_en' is asserted. 327 * Relevant for revisions >= AL_UDMA_REV_ID_REV2 */ 328 uint16_t tgtaddr; 329 }; 330 331 /** UDMA Target-ID control configuration */ 332 struct al_udma_gen_tgtid_conf { 333 /* TX queue configuration */ 334 struct al_udma_gen_tgtid_q_conf tx_q_conf[DMA_MAX_Q]; 335 336 /* RX queue configuration */ 337 struct al_udma_gen_tgtid_q_conf rx_q_conf[DMA_MAX_Q]; 338 }; 339 340 /** UDMA Target-ID MSIX control configuration */ 341 struct al_udma_gen_tgtid_msix_conf { 342 /* Enable write to all TGTID_n registers in the MSI-X Controller */ 343 al_bool access_en; 344 345 /* use TGTID_n [7:0] from MSI-X Controller for MSI-X message */ 346 al_bool sel; 347 }; 348 349 /* Report Error - to be used for abort */ 350 void al_udma_err_report(struct al_udma *udma); 351 352 /* Statistics - TBD */ 353 void al_udma_stats_get(struct al_udma *udma); 354 355 /* Misc configurations */ 356 /* Configure AXI configuration */ 357 int al_udma_axi_set(struct udma_gen_axi *axi_regs, 358 struct al_udma_axi_conf *axi); 359 360 /* Configure UDMA AXI M2S configuration */ 361 int al_udma_m2s_axi_set(struct al_udma *udma, 362 struct al_udma_m2s_axi_conf *axi_m2s); 363 364 /* Configure UDMA AXI S2M configuration */ 365 int al_udma_s2m_axi_set(struct al_udma *udma, 366 struct al_udma_s2m_axi_conf *axi_s2m); 367 368 /* Configure M2S packet len */ 369 int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma, 370 struct al_udma_m2s_pkt_len_conf *conf); 371 372 /* Configure M2S UDMA descriptor prefetch */ 373 int al_udma_m2s_pref_set(struct al_udma *udma, 374 struct al_udma_m2s_desc_pref_conf *conf); 375 int al_udma_m2s_pref_get(struct al_udma *udma, 376 struct al_udma_m2s_desc_pref_conf *conf); 377 378 /* set m2s packet's max descriptors (including meta descriptors) */ 379 #define AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET 31 380 int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs); 381 382 /* set s2m packets' max descriptors */ 383 #define AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET 31 384 int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs); 385 386 387 /* Configure S2M UDMA descriptor prefetch */ 388 int al_udma_s2m_pref_set(struct al_udma *udma, 389 struct al_udma_s2m_desc_pref_conf *conf); 390 int al_udma_m2s_pref_get(struct al_udma *udma, 391 struct al_udma_m2s_desc_pref_conf *conf); 392 393 /* Configure S2M UDMA data write */ 394 int al_udma_s2m_data_write_set(struct al_udma *udma, 395 struct al_udma_s2m_data_write_conf *conf); 396 397 /* Configure the s2m full line write feature */ 398 int al_udma_s2m_full_line_write_set(struct al_udma *umda, al_bool enable); 399 400 /* Configure S2M UDMA completion */ 401 int al_udma_s2m_completion_set(struct al_udma *udma, 402 struct al_udma_s2m_completion_conf *conf); 403 404 /* Configure the M2S UDMA scheduling mode */ 405 int al_udma_m2s_sc_set(struct al_udma *udma, 406 struct al_udma_m2s_dwrr_conf *sched); 407 408 /* Configure the M2S UDMA rate limitation */ 409 int al_udma_m2s_rlimit_set(struct al_udma *udma, 410 struct al_udma_m2s_rlimit_mode *mode); 411 int al_udma_m2s_rlimit_reset(struct al_udma *udma); 412 413 /* Configure the M2S Stream rate limitation */ 414 int al_udma_m2s_strm_rlimit_set(struct al_udma *udma, 415 struct al_udma_m2s_rlimit_cfg *conf); 416 int al_udma_m2s_strm_rlimit_act(struct al_udma *udma, 417 enum al_udma_m2s_rlimit_action act); 418 419 /* Configure the M2S UDMA Q rate limitation */ 420 int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q, 421 struct al_udma_m2s_rlimit_cfg *conf); 422 int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q, 423 enum al_udma_m2s_rlimit_action act); 424 425 /* Configure the M2S UDMA Q scheduling mode */ 426 int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q, 427 struct al_udma_m2s_q_dwrr_conf *conf); 428 int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set); 429 int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q); 430 431 /* M2S UDMA completion and application timeouts */ 432 int al_udma_m2s_comp_timeouts_set(struct al_udma *udma, 433 struct al_udma_m2s_comp_timeouts *conf); 434 int al_udma_m2s_comp_timeouts_get(struct al_udma *udma, 435 struct al_udma_m2s_comp_timeouts *conf); 436 437 /* UDMA get revision */ 438 static INLINE unsigned int al_udma_get_revision(struct unit_regs __iomem *unit_regs) 439 { 440 return (al_reg_read32(&unit_regs->gen.dma_misc.revision) 441 & UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK) >> 442 UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT; 443 } 444 445 /** 446 * S2M UDMA Configure the expected behavior of Rx/S2M UDMA when there are no Rx Descriptors. 447 * 448 * @param udma 449 * @param drop_packet when set to true, the UDMA will drop packet. 450 * @param gen_interrupt when set to true, the UDMA will generate 451 * no_desc_hint interrupt when a packet received and the UDMA 452 * doesn't find enough free descriptors for it. 453 * @param wait_for_desc_timeout timeout in SB cycles to wait for new 454 * descriptors before dropping the packets. 455 * Notes: 456 * - The hint interrupt is raised immediately without waiting 457 * for new descs. 458 * - value 0 means wait for ever. 459 * 460 * Notes: 461 * - When get_interrupt is set, the API won't program the iofic to unmask this 462 * interrupt, in this case the callee should take care for doing that unmask 463 * using the al_udma_iofic_config() API. 464 * 465 * - The hardware's default configuration is: no drop packet, generate hint 466 * interrupt. 467 * - This API must be called once and before enabling the UDMA 468 * 469 * @return 0 if no error found. 470 */ 471 int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout); 472 473 /** 474 * S2M UDMA configure a queue's completion update 475 * 476 * @param q_udma 477 * @param enable set to true to enable completion update 478 * 479 * completion update better be disabled for tx queues as those descriptors 480 * doesn't carry useful information, thus disabling it saves DMA accesses. 481 * 482 * @return 0 if no error found. 483 */ 484 int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable); 485 486 /** 487 * S2M UDMA configure a queue's completion descriptors coalescing 488 * 489 * @param q_udma 490 * @param enable set to true to enable completion coalescing 491 * @param coal_timeout in South Bridge cycles. 492 * 493 * @return 0 if no error found. 494 */ 495 int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t coal_timeout); 496 497 /** 498 * S2M UDMA configure completion descriptors write burst parameters 499 * 500 * @param udma 501 * @param burst_size completion descriptors write burst size in bytes. 502 * 503 * @return 0 if no error found. 504 */int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t 505 burst_size); 506 507 /** 508 * S2M UDMA configure a queue's completion header split 509 * 510 * @param q_udma 511 * @param enable set to true to enable completion header split 512 * @param force_hdr_split the header split length will be taken from the queue configuration 513 * @param hdr_len header split length. 514 * 515 * @return 0 if no error found. 516 */ 517 int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q, 518 al_bool enable, 519 al_bool force_hdr_split, 520 uint32_t hdr_len); 521 522 /* S2M UDMA per queue completion configuration */ 523 int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q, 524 struct al_udma_s2m_q_comp_conf *conf); 525 526 /** UDMA Target-ID control configuration per queue */ 527 void al_udma_gen_tgtid_conf_queue_set( 528 struct unit_regs *unit_regs, 529 struct al_udma_gen_tgtid_conf *conf, 530 uint32_t qid); 531 532 /** UDMA Target-ID control configuration */ 533 void al_udma_gen_tgtid_conf_set( 534 struct unit_regs __iomem *unit_regs, 535 struct al_udma_gen_tgtid_conf *conf); 536 537 /** UDMA Target-ID MSIX control configuration */ 538 void al_udma_gen_tgtid_msix_conf_set( 539 struct unit_regs __iomem *unit_regs, 540 struct al_udma_gen_tgtid_msix_conf *conf); 541 542 /* *INDENT-OFF* */ 543 #ifdef __cplusplus 544 } 545 #endif 546 /* *INDENT-ON* */ 547 /** @} end of UDMA config group */ 548 #endif /* __AL_HAL_UDMA_CONFIG_H__ */ 549