1 /******************************************************************************* 2 Copyright (C) 2015 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /** 37 * @{ 38 * @file al_hal_serdes_regs.h 39 * 40 * @brief ... registers 41 * 42 */ 43 44 #ifndef __AL_HAL_SERDES_REGS_H__ 45 #define __AL_HAL_SERDES_REGS_H__ 46 47 #include "al_hal_plat_types.h" 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 /* 53 * Unit Registers 54 */ 55 56 struct serdes_gen { 57 /* [0x0] SerDes Registers Version */ 58 uint32_t version; 59 uint32_t rsrvd_0[3]; 60 /* [0x10] SerDes register file address */ 61 uint32_t reg_addr; 62 /* [0x14] SerDes register file data */ 63 uint32_t reg_data; 64 uint32_t rsrvd_1[2]; 65 /* [0x20] SerDes control */ 66 uint32_t ictl_multi_bist; 67 /* [0x24] SerDes control */ 68 uint32_t ictl_pcs; 69 /* [0x28] SerDes control */ 70 uint32_t ictl_pma; 71 uint32_t rsrvd_2; 72 /* [0x30] SerDes control */ 73 uint32_t ipd_multi_synth; 74 /* [0x34] SerDes control */ 75 uint32_t irst; 76 /* [0x38] SerDes control */ 77 uint32_t octl_multi_synthready; 78 /* [0x3c] SerDes control */ 79 uint32_t octl_multi_synthstatus; 80 /* [0x40] SerDes control */ 81 uint32_t clk_out; 82 uint32_t rsrvd[47]; 83 }; 84 struct serdes_lane { 85 uint32_t rsrvd1[4]; 86 /* [0x10] SerDes status */ 87 uint32_t octl_pma; 88 /* [0x14] SerDes control */ 89 uint32_t ictl_multi_andme; 90 /* [0x18] SerDes control */ 91 uint32_t ictl_multi_lb; 92 /* [0x1c] SerDes control */ 93 uint32_t ictl_multi_rxbist; 94 /* [0x20] SerDes control */ 95 uint32_t ictl_multi_txbist; 96 /* [0x24] SerDes control */ 97 uint32_t ictl_multi; 98 /* [0x28] SerDes control */ 99 uint32_t ictl_multi_rxeq; 100 /* [0x2c] SerDes control */ 101 uint32_t ictl_multi_rxeq_l_low; 102 /* [0x30] SerDes control */ 103 uint32_t ictl_multi_rxeq_l_high; 104 /* [0x34] SerDes control */ 105 uint32_t ictl_multi_rxeyediag; 106 /* [0x38] SerDes control */ 107 uint32_t ictl_multi_txdeemph; 108 /* [0x3c] SerDes control */ 109 uint32_t ictl_multi_txmargin; 110 /* [0x40] SerDes control */ 111 uint32_t ictl_multi_txswing; 112 /* [0x44] SerDes control */ 113 uint32_t idat_multi; 114 /* [0x48] SerDes control */ 115 uint32_t ipd_multi; 116 /* [0x4c] SerDes control */ 117 uint32_t octl_multi_rxbist; 118 /* [0x50] SerDes control */ 119 uint32_t octl_multi; 120 /* [0x54] SerDes control */ 121 uint32_t octl_multi_rxeyediag; 122 /* [0x58] SerDes control */ 123 uint32_t odat_multi_rxbist; 124 /* [0x5c] SerDes control */ 125 uint32_t odat_multi_rxeq; 126 /* [0x60] SerDes control */ 127 uint32_t multi_rx_dvalid; 128 /* [0x64] SerDes control */ 129 uint32_t reserved; 130 uint32_t rsrvd[6]; 131 }; 132 133 struct al_serdes_regs { 134 uint32_t rsrvd_0[64]; 135 struct serdes_gen gen; /* [0x100] */ 136 struct serdes_lane lane[4]; /* [0x200] */ 137 }; 138 139 140 /* 141 * Registers Fields 142 */ 143 144 145 /**** version register ****/ 146 /* Revision number (Minor) */ 147 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 148 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 149 /* Revision number (Major) */ 150 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 151 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 152 /* Date of release */ 153 #define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000 154 #define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16 155 /* Month of release */ 156 #define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 157 #define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21 158 /* Year of release (starting from 2000) */ 159 #define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 160 #define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25 161 /* Reserved */ 162 #define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000 163 #define SERDES_GEN_VERSION_RESERVED_SHIFT 30 164 165 /**** reg_addr register ****/ 166 /* Address value */ 167 #define SERDES_GEN_REG_ADDR_VAL_MASK 0x0000FFFF 168 #define SERDES_GEN_REG_ADDR_VAL_SHIFT 0 169 170 /**** reg_data register ****/ 171 /* Data value */ 172 #define SERDES_GEN_REG_DATA_VAL_MASK 0x000000FF 173 #define SERDES_GEN_REG_DATA_VAL_SHIFT 0 174 175 /**** ICTL_MULTI_BIST register ****/ 176 177 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007 178 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0 179 180 /**** ICTL_PCS register ****/ 181 182 #define SERDES_GEN_ICTL_PCS_EN_NT (1 << 0) 183 184 /**** ICTL_PMA register ****/ 185 186 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007 187 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0 188 189 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \ 190 (0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 191 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \ 192 (3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 193 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \ 194 (4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT)) 195 196 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070 197 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4 198 199 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \ 200 (0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 201 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \ 202 (2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 203 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \ 204 (3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT)) 205 206 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700 207 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8 208 209 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \ 210 (0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 211 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \ 212 (2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 213 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \ 214 (3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT)) 215 216 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC (1 << 11) 217 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS (0 << 11) 218 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER (1 << 11) 219 220 #define SERDES_GEN_ICTL_PMA_TXENABLE_A (1 << 12) 221 222 #define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13) 223 224 /**** IPD_MULTI_SYNTH register ****/ 225 226 #define SERDES_GEN_IPD_MULTI_SYNTH_B (1 << 0) 227 228 /**** IRST register ****/ 229 230 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A (1 << 0) 231 232 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A (1 << 1) 233 234 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A (1 << 2) 235 236 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A (1 << 3) 237 238 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4) 239 240 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5) 241 242 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6) 243 244 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7) 245 246 #define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8) 247 248 #define SERDES_GEN_IRST_POR_B_A (1 << 12) 249 250 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16) 251 252 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17) 253 254 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18) 255 256 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19) 257 258 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20) 259 260 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21) 261 262 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22) 263 264 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23) 265 266 /**** OCTL_MULTI_SYNTHREADY register ****/ 267 268 #define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0) 269 270 /**** OCTL_MULTI_SYNTHSTATUS register ****/ 271 272 #define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0) 273 274 /**** clk_out register ****/ 275 276 #define SERDES_GEN_CLK_OUT_SEL_MASK 0x0000003F 277 #define SERDES_GEN_CLK_OUT_SEL_SHIFT 0 278 279 /**** OCTL_PMA register ****/ 280 281 #define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0) 282 283 /**** ICTL_MULTI_ANDME register ****/ 284 285 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0) 286 287 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1) 288 289 /**** ICTL_MULTI_LB register ****/ 290 291 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0) 292 293 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1) 294 295 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2) 296 297 #define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3) 298 299 #define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4) 300 301 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8) 302 303 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9) 304 305 /**** ICTL_MULTI_RXBIST register ****/ 306 307 #define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0) 308 309 /**** ICTL_MULTI_TXBIST register ****/ 310 311 #define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0) 312 313 /**** ICTL_MULTI register ****/ 314 315 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003 316 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0 317 318 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2) 319 320 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070 321 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4 322 323 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8) 324 325 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9) 326 327 #define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12) 328 329 #define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13) 330 331 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000 332 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16 333 334 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19) 335 336 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000 337 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20 338 339 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23) 340 341 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000 342 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24 343 344 #define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27) 345 346 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000 347 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28 348 349 /**** ICTL_MULTI_RXEQ register ****/ 350 351 #define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0) 352 353 #define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1) 354 355 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070 356 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4 357 358 /**** ICTL_MULTI_RXEQ_L_high register ****/ 359 360 #define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0) 361 362 /**** ICTL_MULTI_RXEYEDIAG register ****/ 363 364 #define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0) 365 366 /**** ICTL_MULTI_TXDEEMPH register ****/ 367 368 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF 369 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0 370 371 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK 0x7c0 372 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT 6 373 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK 0xf000 374 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT 12 375 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK 0x7 376 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT 0 377 378 /**** ICTL_MULTI_TXMARGIN register ****/ 379 380 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007 381 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0 382 383 /**** ICTL_MULTI_TXSWING register ****/ 384 385 #define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0) 386 387 /**** IDAT_MULTI register ****/ 388 389 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F 390 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0 391 392 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4) 393 394 /**** IPD_MULTI register ****/ 395 396 #define SERDES_LANE_IPD_MULTI_TX_L_B (1 << 0) 397 398 #define SERDES_LANE_IPD_MULTI_RX_L_B (1 << 1) 399 400 /**** OCTL_MULTI_RXBIST register ****/ 401 402 #define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0) 403 404 #define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1) 405 406 /**** OCTL_MULTI register ****/ 407 408 #define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0) 409 410 #define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1) 411 412 #define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2) 413 414 #define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3) 415 416 #define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4) 417 418 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5) 419 420 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6) 421 422 #define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7) 423 424 /**** OCTL_MULTI_RXEYEDIAG register ****/ 425 426 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF 427 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0 428 429 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16) 430 431 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17) 432 433 /**** ODAT_MULTI_RXBIST register ****/ 434 435 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF 436 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0 437 438 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16) 439 440 /**** ODAT_MULTI_RXEQ register ****/ 441 442 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF 443 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0 444 445 /**** MULTI_RX_DVALID register ****/ 446 447 #define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0) 448 449 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1) 450 451 #define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2) 452 453 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3) 454 455 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4) 456 457 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5) 458 459 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000 460 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16 461 462 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24) 463 464 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25) 465 466 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26) 467 468 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27) 469 470 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28) 471 472 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29) 473 474 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30) 475 476 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31) 477 478 /**** reserved register ****/ 479 480 #define SERDES_LANE_RESERVED_OUT_MASK 0x000000FF 481 #define SERDES_LANE_RESERVED_OUT_SHIFT 0 482 483 #define SERDES_LANE_RESERVED_IN_MASK 0x00FF0000 484 #define SERDES_LANE_RESERVED_IN_SHIFT 16 485 486 #ifdef __cplusplus 487 } 488 #endif 489 490 #endif /* __AL_HAL_serdes_REGS_H__ */ 491 492 /** @} end of ... group */ 493 494 495