1 /*- 2 * Data structures and definitions for CAM Control Blocks (CCBs). 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _CAM_CAM_CCB_H 32 #define _CAM_CAM_CCB_H 1 33 34 #include <sys/queue.h> 35 #include <sys/time.h> 36 #include <sys/limits.h> 37 #ifndef _KERNEL 38 #include <sys/callout.h> 39 #endif 40 #include <cam/cam_debug.h> 41 #include <cam/scsi/scsi_all.h> 42 #include <cam/ata/ata_all.h> 43 #include <cam/nvme/nvme_all.h> 44 #include <cam/mmc/mmc_all.h> 45 46 /* General allocation length definitions for CCB structures */ 47 #define IOCDBLEN CAM_MAX_CDBLEN /* Space for CDB bytes/pointer */ 48 #define VUHBALEN 14 /* Vendor Unique HBA length */ 49 #define SIM_IDLEN 16 /* ASCII string len for SIM ID */ 50 #define HBA_IDLEN 16 /* ASCII string len for HBA ID */ 51 #define DEV_IDLEN 16 /* ASCII string len for device names */ 52 #define CCB_PERIPH_PRIV_SIZE 2 /* size of peripheral private area */ 53 #define CCB_SIM_PRIV_SIZE 2 /* size of sim private area */ 54 55 /* Struct definitions for CAM control blocks */ 56 57 /* Common CCB header */ 58 59 /* CCB memory allocation flags */ 60 typedef enum { 61 CAM_CCB_FROM_UMA = 0x00000001,/* CCB from a periph UMA zone */ 62 } ccb_alloc_flags; 63 64 /* CAM CCB flags */ 65 typedef enum { 66 CAM_CDB_POINTER = 0x00000001,/* The CDB field is a pointer */ 67 CAM_unused1 = 0x00000002, 68 CAM_unused2 = 0x00000004, 69 CAM_NEGOTIATE = 0x00000008,/* 70 * Perform transport negotiation 71 * with this command. 72 */ 73 CAM_DATA_ISPHYS = 0x00000010,/* Data type with physical addrs */ 74 CAM_DIS_AUTOSENSE = 0x00000020,/* Disable autosense feature */ 75 CAM_DIR_BOTH = 0x00000000,/* Data direction (00:IN/OUT) */ 76 CAM_DIR_IN = 0x00000040,/* Data direction (01:DATA IN) */ 77 CAM_DIR_OUT = 0x00000080,/* Data direction (10:DATA OUT) */ 78 CAM_DIR_NONE = 0x000000C0,/* Data direction (11:no data) */ 79 CAM_DIR_MASK = 0x000000C0,/* Data direction Mask */ 80 CAM_DATA_VADDR = 0x00000000,/* Data type (000:Virtual) */ 81 CAM_DATA_PADDR = 0x00000010,/* Data type (001:Physical) */ 82 CAM_DATA_SG = 0x00040000,/* Data type (010:sglist) */ 83 CAM_DATA_SG_PADDR = 0x00040010,/* Data type (011:sglist phys) */ 84 CAM_DATA_BIO = 0x00200000,/* Data type (100:bio) */ 85 CAM_DATA_MASK = 0x00240010,/* Data type mask */ 86 CAM_unused3 = 0x00000100, 87 CAM_unused4 = 0x00000200, 88 CAM_DEV_QFRZDIS = 0x00000400,/* Disable DEV Q freezing */ 89 CAM_DEV_QFREEZE = 0x00000800,/* Freeze DEV Q on execution */ 90 CAM_HIGH_POWER = 0x00001000,/* Command takes a lot of power */ 91 CAM_SENSE_PTR = 0x00002000,/* Sense data is a pointer */ 92 CAM_SENSE_PHYS = 0x00004000,/* Sense pointer is physical addr*/ 93 CAM_TAG_ACTION_VALID = 0x00008000,/* Use the tag action in this ccb*/ 94 CAM_PASS_ERR_RECOVER = 0x00010000,/* Pass driver does err. recovery*/ 95 CAM_DIS_DISCONNECT = 0x00020000,/* Disable disconnect */ 96 CAM_unused5 = 0x00080000, 97 CAM_unused6 = 0x00100000, 98 CAM_CDB_PHYS = 0x00400000,/* CDB poiner is physical */ 99 CAM_unused7 = 0x00800000, 100 101 /* Phase cognizant mode flags */ 102 CAM_unused8 = 0x01000000, 103 CAM_unused9 = 0x02000000, 104 CAM_unused10 = 0x04000000, 105 CAM_unused11 = 0x08000000, 106 CAM_unused12 = 0x10000000, 107 CAM_unused13 = 0x20000000, 108 CAM_unused14 = 0x40000000, 109 110 /* Host target Mode flags */ 111 CAM_SEND_SENSE = 0x08000000,/* Send sense data with status */ 112 CAM_unused15 = 0x10000000, 113 CAM_unused16 = 0x20000000, 114 CAM_SEND_STATUS = 0x40000000,/* Send status after data phase */ 115 116 CAM_UNLOCKED = 0x80000000 /* Call callback without lock. */ 117 } ccb_flags; 118 119 typedef enum { 120 CAM_USER_DATA_ADDR = 0x00000002,/* Userspace data pointers */ 121 CAM_SG_FORMAT_IOVEC = 0x00000004,/* iovec instead of busdma S/G*/ 122 CAM_UNMAPPED_BUF = 0x00000008 /* use unmapped I/O */ 123 } ccb_xflags; 124 125 /* XPT Opcodes for xpt_action */ 126 typedef enum { 127 /* Function code flags are bits greater than 0xff */ 128 XPT_FC_QUEUED = 0x100, 129 /* Non-immediate function code */ 130 XPT_FC_USER_CCB = 0x200, 131 XPT_FC_XPT_ONLY = 0x400, 132 /* Only for the transport layer device */ 133 XPT_FC_DEV_QUEUED = 0x800 | XPT_FC_QUEUED, 134 /* Passes through the device queues */ 135 /* Common function commands: 0x00->0x0F */ 136 XPT_NOOP = 0x00, 137 /* Execute Nothing */ 138 XPT_SCSI_IO = 0x01 | XPT_FC_DEV_QUEUED, 139 /* Execute the requested I/O operation */ 140 XPT_GDEV_TYPE = 0x02, 141 /* Get type information for specified device */ 142 XPT_GDEVLIST = 0x03, 143 /* Get a list of peripheral devices */ 144 XPT_PATH_INQ = 0x04, 145 /* Path routing inquiry */ 146 XPT_REL_SIMQ = 0x05, 147 /* Release a frozen device queue */ 148 XPT_SASYNC_CB = 0x06, 149 /* Set Asynchronous Callback Parameters */ 150 XPT_SDEV_TYPE = 0x07, 151 /* Set device type information */ 152 XPT_SCAN_BUS = 0x08 | XPT_FC_QUEUED | XPT_FC_USER_CCB 153 | XPT_FC_XPT_ONLY, 154 /* (Re)Scan the SCSI Bus */ 155 XPT_DEV_MATCH = 0x09 | XPT_FC_XPT_ONLY, 156 /* Get EDT entries matching the given pattern */ 157 XPT_DEBUG = 0x0a, 158 /* Turn on debugging for a bus, target or lun */ 159 XPT_PATH_STATS = 0x0b, 160 /* Path statistics (error counts, etc.) */ 161 XPT_GDEV_STATS = 0x0c, 162 /* Device statistics (error counts, etc.) */ 163 XPT_DEV_ADVINFO = 0x0e, 164 /* Get/Set Device advanced information */ 165 XPT_ASYNC = 0x0f | XPT_FC_QUEUED | XPT_FC_USER_CCB 166 | XPT_FC_XPT_ONLY, 167 /* Asynchronous event */ 168 /* SCSI Control Functions: 0x10->0x1F */ 169 XPT_ABORT = 0x10, 170 /* Abort the specified CCB */ 171 XPT_RESET_BUS = 0x11 | XPT_FC_XPT_ONLY, 172 /* Reset the specified SCSI bus */ 173 XPT_RESET_DEV = 0x12 | XPT_FC_DEV_QUEUED, 174 /* Bus Device Reset the specified SCSI device */ 175 XPT_TERM_IO = 0x13, 176 /* Terminate the I/O process */ 177 XPT_SCAN_LUN = 0x14 | XPT_FC_QUEUED | XPT_FC_USER_CCB 178 | XPT_FC_XPT_ONLY, 179 /* Scan Logical Unit */ 180 XPT_GET_TRAN_SETTINGS = 0x15, 181 /* 182 * Get default/user transfer settings 183 * for the target 184 */ 185 XPT_SET_TRAN_SETTINGS = 0x16, 186 /* 187 * Set transfer rate/width 188 * negotiation settings 189 */ 190 XPT_CALC_GEOMETRY = 0x17, 191 /* 192 * Calculate the geometry parameters for 193 * a device give the sector size and 194 * volume size. 195 */ 196 XPT_ATA_IO = 0x18 | XPT_FC_DEV_QUEUED, 197 /* Execute the requested ATA I/O operation */ 198 199 XPT_GET_SIM_KNOB_OLD = 0x18, /* Compat only */ 200 201 XPT_SET_SIM_KNOB = 0x19, 202 /* 203 * Set SIM specific knob values. 204 */ 205 206 XPT_GET_SIM_KNOB = 0x1a, 207 /* 208 * Get SIM specific knob values. 209 */ 210 211 XPT_SMP_IO = 0x1b | XPT_FC_DEV_QUEUED, 212 /* Serial Management Protocol */ 213 214 XPT_NVME_IO = 0x1c | XPT_FC_DEV_QUEUED, 215 /* Execute the requested NVMe I/O operation */ 216 217 XPT_MMC_IO = 0x1d | XPT_FC_DEV_QUEUED, 218 /* Placeholder for MMC / SD / SDIO I/O stuff */ 219 220 XPT_SCAN_TGT = 0x1e | XPT_FC_QUEUED | XPT_FC_USER_CCB 221 | XPT_FC_XPT_ONLY, 222 /* Scan Target */ 223 224 XPT_NVME_ADMIN = 0x1f | XPT_FC_DEV_QUEUED, 225 /* Execute the requested NVMe Admin operation */ 226 227 /* HBA engine commands 0x20->0x2F */ 228 XPT_ENG_INQ = 0x20 | XPT_FC_XPT_ONLY, 229 /* HBA engine feature inquiry */ 230 XPT_ENG_EXEC = 0x21 | XPT_FC_DEV_QUEUED, 231 /* HBA execute engine request */ 232 233 /* Target mode commands: 0x30->0x3F */ 234 XPT_EN_LUN = 0x30, 235 /* Enable LUN as a target */ 236 XPT_TARGET_IO = 0x31 | XPT_FC_DEV_QUEUED, 237 /* Execute target I/O request */ 238 XPT_ACCEPT_TARGET_IO = 0x32 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 239 /* Accept Host Target Mode CDB */ 240 XPT_CONT_TARGET_IO = 0x33 | XPT_FC_DEV_QUEUED, 241 /* Continue Host Target I/O Connection */ 242 XPT_IMMED_NOTIFY = 0x34 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 243 /* Notify Host Target driver of event (obsolete) */ 244 XPT_NOTIFY_ACK = 0x35, 245 /* Acknowledgement of event (obsolete) */ 246 XPT_IMMEDIATE_NOTIFY = 0x36 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 247 /* Notify Host Target driver of event */ 248 XPT_NOTIFY_ACKNOWLEDGE = 0x37 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 249 /* Acknowledgement of event */ 250 XPT_REPROBE_LUN = 0x38 | XPT_FC_QUEUED | XPT_FC_USER_CCB, 251 /* Query device capacity and notify GEOM */ 252 253 XPT_MMC_SET_TRAN_SETTINGS = 0x40 | XPT_FC_DEV_QUEUED, 254 XPT_MMC_GET_TRAN_SETTINGS = 0x41 | XPT_FC_DEV_QUEUED, 255 256 /* Vendor Unique codes: 0x80->0x8F */ 257 XPT_VUNIQUE = 0x80 258 } xpt_opcode; 259 260 #define XPT_FC_GROUP_MASK 0xF0 261 #define XPT_FC_GROUP(op) ((op) & XPT_FC_GROUP_MASK) 262 #define XPT_FC_GROUP_COMMON 0x00 263 #define XPT_FC_GROUP_SCSI_CONTROL 0x10 264 #define XPT_FC_GROUP_HBA_ENGINE 0x20 265 #define XPT_FC_GROUP_TMODE 0x30 266 #define XPT_FC_GROUP_VENDOR_UNIQUE 0x80 267 268 #define XPT_FC_IS_DEV_QUEUED(ccb) \ 269 (((ccb)->ccb_h.func_code & XPT_FC_DEV_QUEUED) == XPT_FC_DEV_QUEUED) 270 #define XPT_FC_IS_QUEUED(ccb) \ 271 (((ccb)->ccb_h.func_code & XPT_FC_QUEUED) != 0) 272 273 typedef enum { 274 PROTO_UNKNOWN, 275 PROTO_UNSPECIFIED, 276 PROTO_SCSI, /* Small Computer System Interface */ 277 PROTO_ATA, /* AT Attachment */ 278 PROTO_ATAPI, /* AT Attachment Packetized Interface */ 279 PROTO_SATAPM, /* SATA Port Multiplier */ 280 PROTO_SEMB, /* SATA Enclosure Management Bridge */ 281 PROTO_NVME, /* NVME */ 282 PROTO_MMCSD, /* MMC, SD, SDIO */ 283 } cam_proto; 284 285 typedef enum { 286 XPORT_UNKNOWN, 287 XPORT_UNSPECIFIED, 288 XPORT_SPI, /* SCSI Parallel Interface */ 289 XPORT_FC, /* Fiber Channel */ 290 XPORT_SSA, /* Serial Storage Architecture */ 291 XPORT_USB, /* Universal Serial Bus */ 292 XPORT_PPB, /* Parallel Port Bus */ 293 XPORT_ATA, /* AT Attachment */ 294 XPORT_SAS, /* Serial Attached SCSI */ 295 XPORT_SATA, /* Serial AT Attachment */ 296 XPORT_ISCSI, /* iSCSI */ 297 XPORT_SRP, /* SCSI RDMA Protocol */ 298 XPORT_NVME, /* NVMe over PCIe */ 299 XPORT_MMCSD, /* MMC, SD, SDIO card */ 300 XPORT_NVMF, /* NVMe over Fabrics */ 301 } cam_xport; 302 303 #define XPORT_IS_NVME(t) ((t) == XPORT_NVME || (t) == XPORT_NVMF) 304 #define XPORT_IS_ATA(t) ((t) == XPORT_ATA || (t) == XPORT_SATA) 305 #define XPORT_IS_SCSI(t) ((t) != XPORT_UNKNOWN && \ 306 (t) != XPORT_UNSPECIFIED && \ 307 !XPORT_IS_ATA(t) && !XPORT_IS_NVME(t)) 308 #define XPORT_DEVSTAT_TYPE(t) (XPORT_IS_ATA(t) ? DEVSTAT_TYPE_IF_IDE : \ 309 XPORT_IS_SCSI(t) ? DEVSTAT_TYPE_IF_SCSI : \ 310 XPORT_IS_NVME(t) ? DEVSTAT_TYPE_IF_NVME : \ 311 DEVSTAT_TYPE_IF_OTHER) 312 313 #define PROTO_VERSION_UNKNOWN (UINT_MAX - 1) 314 #define PROTO_VERSION_UNSPECIFIED UINT_MAX 315 #define XPORT_VERSION_UNKNOWN (UINT_MAX - 1) 316 #define XPORT_VERSION_UNSPECIFIED UINT_MAX 317 318 typedef union { 319 LIST_ENTRY(ccb_hdr) le; 320 SLIST_ENTRY(ccb_hdr) sle; 321 TAILQ_ENTRY(ccb_hdr) tqe; 322 STAILQ_ENTRY(ccb_hdr) stqe; 323 } camq_entry; 324 325 typedef union { 326 void *ptr; 327 u_long field; 328 uint8_t bytes[sizeof(uintptr_t)]; 329 } ccb_priv_entry; 330 331 typedef union { 332 ccb_priv_entry entries[CCB_PERIPH_PRIV_SIZE]; 333 uint8_t bytes[CCB_PERIPH_PRIV_SIZE * sizeof(ccb_priv_entry)]; 334 } ccb_ppriv_area; 335 336 typedef union { 337 ccb_priv_entry entries[CCB_SIM_PRIV_SIZE]; 338 uint8_t bytes[CCB_SIM_PRIV_SIZE * sizeof(ccb_priv_entry)]; 339 } ccb_spriv_area; 340 341 typedef struct { 342 struct timeval *etime; 343 uintptr_t sim_data; 344 uintptr_t periph_data; 345 } ccb_qos_area; 346 347 struct ccb_hdr { 348 cam_pinfo pinfo; /* Info for priority scheduling */ 349 camq_entry xpt_links; /* For chaining in the XPT layer */ 350 camq_entry sim_links; /* For chaining in the SIM layer */ 351 camq_entry periph_links; /* For chaining in the type driver */ 352 #if BYTE_ORDER == LITTLE_ENDIAN 353 uint16_t retry_count; 354 uint16_t alloc_flags; /* ccb_alloc_flags */ 355 #else 356 uint16_t alloc_flags; /* ccb_alloc_flags */ 357 uint16_t retry_count; 358 #endif 359 void (*cbfcnp)(struct cam_periph *, union ccb *); 360 /* Callback on completion function */ 361 xpt_opcode func_code; /* XPT function code */ 362 uint32_t status; /* Status returned by CAM subsystem */ 363 struct cam_path *path; /* Compiled path for this ccb */ 364 path_id_t path_id; /* Path ID for the request */ 365 target_id_t target_id; /* Target device ID */ 366 lun_id_t target_lun; /* Target LUN number */ 367 uint32_t flags; /* ccb_flags */ 368 uint32_t xflags; /* Extended flags */ 369 ccb_ppriv_area periph_priv; 370 ccb_spriv_area sim_priv; 371 ccb_qos_area qos; 372 uint32_t timeout; /* Hard timeout value in mseconds */ 373 struct timeval softtimeout; /* Soft timeout value in sec + usec */ 374 }; 375 376 /* Get Device Information CCB */ 377 struct ccb_getdev { 378 struct ccb_hdr ccb_h; 379 cam_proto protocol; 380 struct scsi_inquiry_data inq_data; 381 struct ata_params ident_data; 382 uint8_t serial_num[252]; 383 uint8_t inq_flags; 384 uint8_t serial_num_len; 385 void *padding[2]; 386 }; 387 388 /* Device Statistics CCB */ 389 struct ccb_getdevstats { 390 struct ccb_hdr ccb_h; 391 int dev_openings; /* Space left for more work on device*/ 392 int dev_active; /* Transactions running on the device */ 393 int allocated; /* CCBs allocated for the device */ 394 int queued; /* CCBs queued to be sent to the device */ 395 int held; /* 396 * CCBs held by peripheral drivers 397 * for this device 398 */ 399 int maxtags; /* 400 * Boundary conditions for number of 401 * tagged operations 402 */ 403 int mintags; 404 struct timeval last_reset; /* Time of last bus reset/loop init */ 405 }; 406 407 typedef enum { 408 CAM_GDEVLIST_LAST_DEVICE, 409 CAM_GDEVLIST_LIST_CHANGED, 410 CAM_GDEVLIST_MORE_DEVS, 411 CAM_GDEVLIST_ERROR 412 } ccb_getdevlist_status_e; 413 414 struct ccb_getdevlist { 415 struct ccb_hdr ccb_h; 416 char periph_name[DEV_IDLEN]; 417 uint32_t unit_number; 418 unsigned int generation; 419 uint32_t index; 420 ccb_getdevlist_status_e status; 421 }; 422 423 typedef enum { 424 PERIPH_MATCH_ANY = 0x000, 425 PERIPH_MATCH_PATH = 0x001, 426 PERIPH_MATCH_TARGET = 0x002, 427 PERIPH_MATCH_LUN = 0x004, 428 PERIPH_MATCH_NAME = 0x008, 429 PERIPH_MATCH_UNIT = 0x010, 430 } periph_pattern_flags; 431 432 struct periph_match_pattern { 433 char periph_name[DEV_IDLEN]; 434 uint32_t unit_number; 435 path_id_t path_id; 436 target_id_t target_id; 437 lun_id_t target_lun; 438 periph_pattern_flags flags; 439 }; 440 441 typedef enum { 442 DEV_MATCH_ANY = 0x000, 443 DEV_MATCH_PATH = 0x001, 444 DEV_MATCH_TARGET = 0x002, 445 DEV_MATCH_LUN = 0x004, 446 DEV_MATCH_INQUIRY = 0x008, 447 DEV_MATCH_DEVID = 0x010, 448 } dev_pattern_flags; 449 450 struct device_id_match_pattern { 451 uint8_t id_len; 452 uint8_t id[256]; 453 }; 454 455 struct device_match_pattern { 456 path_id_t path_id; 457 target_id_t target_id; 458 lun_id_t target_lun; 459 dev_pattern_flags flags; 460 union { 461 struct scsi_static_inquiry_pattern inq_pat; 462 struct device_id_match_pattern devid_pat; 463 } data; 464 }; 465 466 typedef enum { 467 BUS_MATCH_ANY = 0x000, 468 BUS_MATCH_PATH = 0x001, 469 BUS_MATCH_NAME = 0x002, 470 BUS_MATCH_UNIT = 0x004, 471 BUS_MATCH_BUS_ID = 0x008, 472 } bus_pattern_flags; 473 474 struct bus_match_pattern { 475 path_id_t path_id; 476 char dev_name[DEV_IDLEN]; 477 uint32_t unit_number; 478 uint32_t bus_id; 479 bus_pattern_flags flags; 480 }; 481 482 union match_pattern { 483 struct periph_match_pattern periph_pattern; 484 struct device_match_pattern device_pattern; 485 struct bus_match_pattern bus_pattern; 486 }; 487 488 typedef enum { 489 DEV_MATCH_PERIPH, 490 DEV_MATCH_DEVICE, 491 DEV_MATCH_BUS 492 } dev_match_type; 493 494 struct dev_match_pattern { 495 dev_match_type type; 496 union match_pattern pattern; 497 }; 498 499 struct periph_match_result { 500 char periph_name[DEV_IDLEN]; 501 uint32_t unit_number; 502 path_id_t path_id; 503 target_id_t target_id; 504 lun_id_t target_lun; 505 }; 506 507 typedef enum { 508 DEV_RESULT_NOFLAG = 0x00, 509 DEV_RESULT_UNCONFIGURED = 0x01 510 } dev_result_flags; 511 512 struct device_match_result { 513 path_id_t path_id; 514 target_id_t target_id; 515 lun_id_t target_lun; 516 cam_proto protocol; 517 struct scsi_inquiry_data inq_data; 518 struct ata_params ident_data; 519 dev_result_flags flags; 520 }; 521 522 struct bus_match_result { 523 path_id_t path_id; 524 char dev_name[DEV_IDLEN]; 525 uint32_t unit_number; 526 uint32_t bus_id; 527 }; 528 529 union match_result { 530 struct periph_match_result periph_result; 531 struct device_match_result device_result; 532 struct bus_match_result bus_result; 533 }; 534 535 struct dev_match_result { 536 dev_match_type type; 537 union match_result result; 538 }; 539 540 typedef enum { 541 CAM_DEV_MATCH_LAST, 542 CAM_DEV_MATCH_MORE, 543 CAM_DEV_MATCH_LIST_CHANGED, 544 CAM_DEV_MATCH_SIZE_ERROR, 545 CAM_DEV_MATCH_ERROR 546 } ccb_dev_match_status; 547 548 typedef enum { 549 CAM_DEV_POS_NONE = 0x000, 550 CAM_DEV_POS_BUS = 0x001, 551 CAM_DEV_POS_TARGET = 0x002, 552 CAM_DEV_POS_DEVICE = 0x004, 553 CAM_DEV_POS_PERIPH = 0x008, 554 CAM_DEV_POS_PDPTR = 0x010, 555 CAM_DEV_POS_TYPEMASK = 0xf00, 556 CAM_DEV_POS_EDT = 0x100, 557 CAM_DEV_POS_PDRV = 0x200 558 } dev_pos_type; 559 560 struct ccb_dm_cookie { 561 void *bus; 562 void *target; 563 void *device; 564 void *periph; 565 void *pdrv; 566 }; 567 568 struct ccb_dev_position { 569 u_int generations[4]; 570 #define CAM_BUS_GENERATION 0x00 571 #define CAM_TARGET_GENERATION 0x01 572 #define CAM_DEV_GENERATION 0x02 573 #define CAM_PERIPH_GENERATION 0x03 574 dev_pos_type position_type; 575 struct ccb_dm_cookie cookie; 576 }; 577 578 struct ccb_dev_match { 579 struct ccb_hdr ccb_h; 580 ccb_dev_match_status status; 581 uint32_t num_patterns; 582 uint32_t pattern_buf_len; 583 struct dev_match_pattern *patterns; 584 uint32_t num_matches; 585 uint32_t match_buf_len; 586 struct dev_match_result *matches; 587 struct ccb_dev_position pos; 588 }; 589 590 /* 591 * Definitions for the path inquiry CCB fields. 592 */ 593 #define CAM_VERSION 0x1a /* Hex value for current version */ 594 595 typedef enum { 596 PI_MDP_ABLE = 0x80, /* Supports MDP message */ 597 PI_WIDE_32 = 0x40, /* Supports 32 bit wide SCSI */ 598 PI_WIDE_16 = 0x20, /* Supports 16 bit wide SCSI */ 599 PI_SDTR_ABLE = 0x10, /* Supports SDTR message */ 600 PI_LINKED_CDB = 0x08, /* Supports linked CDBs */ 601 PI_SATAPM = 0x04, /* Supports SATA PM */ 602 PI_TAG_ABLE = 0x02, /* Supports tag queue messages */ 603 PI_SOFT_RST = 0x01 /* Supports soft reset alternative */ 604 } pi_inqflag; 605 606 typedef enum { 607 PIT_PROCESSOR = 0x80, /* Target mode processor mode */ 608 PIT_PHASE = 0x40, /* Target mode phase cog. mode */ 609 PIT_DISCONNECT = 0x20, /* Disconnects supported in target mode */ 610 PIT_TERM_IO = 0x10, /* Terminate I/O message supported in TM */ 611 PIT_GRP_6 = 0x08, /* Group 6 commands supported */ 612 PIT_GRP_7 = 0x04 /* Group 7 commands supported */ 613 } pi_tmflag; 614 615 typedef enum { 616 PIM_ATA_EXT = 0x200,/* ATA requests can understand ata_ext requests */ 617 PIM_EXTLUNS = 0x100,/* 64bit extended LUNs supported */ 618 PIM_SCANHILO = 0x80, /* Bus scans from high ID to low ID */ 619 PIM_NOREMOVE = 0x40, /* Removeable devices not included in scan */ 620 PIM_NOINITIATOR = 0x20, /* Initiator role not supported. */ 621 PIM_NOBUSRESET = 0x10, /* User has disabled initial BUS RESET */ 622 PIM_NO_6_BYTE = 0x08, /* Do not send 6-byte commands */ 623 PIM_SEQSCAN = 0x04, /* Do bus scans sequentially, not in parallel */ 624 PIM_UNMAPPED = 0x02, 625 PIM_NOSCAN = 0x01 /* SIM does its own scanning */ 626 } pi_miscflag; 627 628 /* Path Inquiry CCB */ 629 struct ccb_pathinq_settings_spi { 630 uint8_t ppr_options; 631 }; 632 633 struct ccb_pathinq_settings_fc { 634 uint64_t wwnn; /* world wide node name */ 635 uint64_t wwpn; /* world wide port name */ 636 uint32_t port; /* 24 bit port id, if known */ 637 uint32_t bitrate; /* Mbps */ 638 }; 639 640 struct ccb_pathinq_settings_sas { 641 uint32_t bitrate; /* Mbps */ 642 }; 643 644 #define NVME_DEV_NAME_LEN 52 645 struct ccb_pathinq_settings_nvme { 646 uint32_t nsid; /* Namespace ID for this path */ 647 uint32_t domain; 648 uint8_t bus; 649 uint8_t slot; 650 uint8_t function; 651 uint8_t extra; 652 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */ 653 }; 654 _Static_assert(sizeof(struct ccb_pathinq_settings_nvme) == 64, 655 "ccb_pathinq_settings_nvme too big"); 656 657 struct ccb_pathinq_settings_nvmf { 658 uint32_t nsid; /* Namespace ID for this path */ 659 uint8_t trtype; 660 char dev_name[NVME_DEV_NAME_LEN]; /* nvme controller dev name for this device */ 661 }; 662 663 #define PATHINQ_SETTINGS_SIZE 128 664 665 struct ccb_pathinq { 666 struct ccb_hdr ccb_h; 667 uint8_t version_num; /* Version number for the SIM/HBA */ 668 uint8_t hba_inquiry; /* Mimic of INQ byte 7 for the HBA */ 669 uint16_t target_sprt; /* Flags for target mode support */ 670 uint32_t hba_misc; /* Misc HBA features */ 671 uint16_t hba_eng_cnt; /* HBA engine count */ 672 /* Vendor Unique capabilities */ 673 uint8_t vuhba_flags[VUHBALEN]; 674 uint32_t max_target; /* Maximum supported Target */ 675 uint32_t max_lun; /* Maximum supported Lun */ 676 uint32_t async_flags; /* Installed Async handlers */ 677 path_id_t hpath_id; /* Highest Path ID in the subsystem */ 678 target_id_t initiator_id; /* ID of the HBA on the SCSI bus */ 679 char sim_vid[SIM_IDLEN]; /* Vendor ID of the SIM */ 680 char hba_vid[HBA_IDLEN]; /* Vendor ID of the HBA */ 681 char dev_name[DEV_IDLEN];/* Device name for SIM */ 682 uint32_t unit_number; /* Unit number for SIM */ 683 uint32_t bus_id; /* Bus ID for SIM */ 684 uint32_t base_transfer_speed;/* Base bus speed in KB/sec */ 685 cam_proto protocol; 686 u_int protocol_version; 687 cam_xport transport; 688 u_int transport_version; 689 union { 690 struct ccb_pathinq_settings_spi spi; 691 struct ccb_pathinq_settings_fc fc; 692 struct ccb_pathinq_settings_sas sas; 693 struct ccb_pathinq_settings_nvme nvme; 694 struct ccb_pathinq_settings_nvmf nvmf; 695 char ccb_pathinq_settings_opaque[PATHINQ_SETTINGS_SIZE]; 696 } xport_specific; 697 u_int maxio; /* Max supported I/O size, in bytes. */ 698 uint16_t hba_vendor; /* HBA vendor ID */ 699 uint16_t hba_device; /* HBA device ID */ 700 uint16_t hba_subvendor; /* HBA subvendor ID */ 701 uint16_t hba_subdevice; /* HBA subdevice ID */ 702 }; 703 704 /* Path Statistics CCB */ 705 struct ccb_pathstats { 706 struct ccb_hdr ccb_h; 707 struct timeval last_reset; /* Time of last bus reset/loop init */ 708 }; 709 710 typedef enum { 711 SMP_FLAG_NONE = 0x00, 712 SMP_FLAG_REQ_SG = 0x01, 713 SMP_FLAG_RSP_SG = 0x02 714 } ccb_smp_pass_flags; 715 716 /* 717 * Serial Management Protocol CCB 718 * XXX Currently the semantics for this CCB are that it is executed either 719 * by the addressed device, or that device's parent (i.e. an expander for 720 * any device on an expander) if the addressed device doesn't support SMP. 721 * Later, once we have the ability to probe SMP-only devices and put them 722 * in CAM's topology, the CCB will only be executed by the addressed device 723 * if possible. 724 */ 725 struct ccb_smpio { 726 struct ccb_hdr ccb_h; 727 uint8_t *smp_request; 728 int smp_request_len; 729 uint16_t smp_request_sglist_cnt; 730 uint8_t *smp_response; 731 int smp_response_len; 732 uint16_t smp_response_sglist_cnt; 733 ccb_smp_pass_flags flags; 734 }; 735 736 typedef union { 737 uint8_t *sense_ptr; /* 738 * Pointer to storage 739 * for sense information 740 */ 741 /* Storage Area for sense information */ 742 struct scsi_sense_data sense_buf; 743 } sense_t; 744 745 typedef union { 746 uint8_t *cdb_ptr; /* Pointer to the CDB bytes to send */ 747 /* Area for the CDB send */ 748 uint8_t cdb_bytes[IOCDBLEN]; 749 } cdb_t; 750 751 /* 752 * SCSI I/O Request CCB used for the XPT_SCSI_IO and XPT_CONT_TARGET_IO 753 * function codes. 754 */ 755 struct ccb_scsiio { 756 struct ccb_hdr ccb_h; 757 union ccb *next_ccb; /* Ptr for next CCB for action */ 758 uint8_t *req_map; /* Ptr to mapping info */ 759 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 760 uint32_t dxfer_len; /* Data transfer length */ 761 /* Autosense storage */ 762 struct scsi_sense_data sense_data; 763 uint8_t sense_len; /* Number of bytes to autosense */ 764 uint8_t cdb_len; /* Number of bytes for the CDB */ 765 uint16_t sglist_cnt; /* Number of SG list entries */ 766 uint8_t scsi_status; /* Returned SCSI status */ 767 uint8_t sense_resid; /* Autosense resid length: 2's comp */ 768 uint32_t resid; /* Transfer residual length: 2's comp */ 769 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 770 uint8_t *msg_ptr; /* Pointer to the message buffer */ 771 uint16_t msg_len; /* Number of bytes for the Message */ 772 uint8_t tag_action; /* What to do for tag queueing */ 773 /* 774 * The tag action should be either the define below (to send a 775 * non-tagged transaction) or one of the defined scsi tag messages 776 * from scsi_message.h. 777 */ 778 #define CAM_TAG_ACTION_NONE 0x00 779 uint8_t priority; /* Command priority for SIMPLE tag */ 780 u_int tag_id; /* tag id from initator (target mode) */ 781 u_int init_id; /* initiator id of who selected */ 782 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 783 struct bio *bio; /* Associated bio */ 784 #endif 785 }; 786 787 static __inline uint8_t * 788 scsiio_cdb_ptr(struct ccb_scsiio *ccb) 789 { 790 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 791 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 792 } 793 794 /* 795 * ATA I/O Request CCB used for the XPT_ATA_IO function code. 796 */ 797 struct ccb_ataio { 798 struct ccb_hdr ccb_h; 799 union ccb *next_ccb; /* Ptr for next CCB for action */ 800 struct ata_cmd cmd; /* ATA command register set */ 801 struct ata_res res; /* ATA result register set */ 802 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 803 uint32_t dxfer_len; /* Data transfer length */ 804 uint32_t resid; /* Transfer residual length: 2's comp */ 805 uint8_t ata_flags; /* Flags for the rest of the buffer */ 806 #define ATA_FLAG_AUX 0x1 807 #define ATA_FLAG_ICC 0x2 808 uint8_t icc; /* Isochronous Command Completion */ 809 uint32_t aux; 810 uint32_t unused; 811 }; 812 813 /* 814 * MMC I/O Request CCB used for the XPT_MMC_IO function code. 815 */ 816 struct ccb_mmcio { 817 struct ccb_hdr ccb_h; 818 union ccb *next_ccb; /* Ptr for next CCB for action */ 819 struct mmc_command cmd; 820 struct mmc_command stop; 821 }; 822 823 struct ccb_accept_tio { 824 struct ccb_hdr ccb_h; 825 cdb_t cdb_io; /* Union for CDB bytes/pointer */ 826 uint8_t cdb_len; /* Number of bytes for the CDB */ 827 uint8_t tag_action; /* What to do for tag queueing */ 828 uint8_t sense_len; /* Number of bytes of Sense Data */ 829 uint8_t priority; /* Command priority for SIMPLE tag */ 830 u_int tag_id; /* tag id from initator (target mode) */ 831 u_int init_id; /* initiator id of who selected */ 832 struct scsi_sense_data sense_data; 833 }; 834 835 static __inline uint8_t * 836 atio_cdb_ptr(struct ccb_accept_tio *ccb) 837 { 838 return ((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 839 ccb->cdb_io.cdb_ptr : ccb->cdb_io.cdb_bytes); 840 } 841 842 /* Release SIM Queue */ 843 struct ccb_relsim { 844 struct ccb_hdr ccb_h; 845 uint32_t release_flags; 846 #define RELSIM_ADJUST_OPENINGS 0x01 847 #define RELSIM_RELEASE_AFTER_TIMEOUT 0x02 848 #define RELSIM_RELEASE_AFTER_CMDCMPLT 0x04 849 #define RELSIM_RELEASE_AFTER_QEMPTY 0x08 850 uint32_t openings; 851 uint32_t release_timeout; /* Abstract argument. */ 852 uint32_t qfrozen_cnt; 853 }; 854 855 /* 856 * NVMe I/O Request CCB used for the XPT_NVME_IO and XPT_NVME_ADMIN function codes. 857 */ 858 struct ccb_nvmeio { 859 struct ccb_hdr ccb_h; 860 union ccb *next_ccb; /* Ptr for next CCB for action */ 861 struct nvme_command cmd; /* NVME command, per NVME standard */ 862 struct nvme_completion cpl; /* NVME completion, per NVME standard */ 863 uint8_t *data_ptr; /* Ptr to the data buf/SG list */ 864 uint32_t dxfer_len; /* Data transfer length */ 865 uint16_t sglist_cnt; /* Number of SG list entries */ 866 uint16_t unused; /* padding for removed uint32_t */ 867 }; 868 869 /* 870 * Definitions for the asynchronous callback CCB fields. 871 */ 872 typedef enum { 873 AC_UNIT_ATTENTION = 0x4000,/* Device reported UNIT ATTENTION */ 874 AC_ADVINFO_CHANGED = 0x2000,/* Advance info might have changes */ 875 AC_CONTRACT = 0x1000,/* A contractual callback */ 876 AC_GETDEV_CHANGED = 0x800,/* Getdev info might have changed */ 877 AC_INQ_CHANGED = 0x400,/* Inquiry info might have changed */ 878 AC_TRANSFER_NEG = 0x200,/* New transfer settings in effect */ 879 AC_LOST_DEVICE = 0x100,/* A device went away */ 880 AC_FOUND_DEVICE = 0x080,/* A new device was found */ 881 AC_PATH_DEREGISTERED = 0x040,/* A path has de-registered */ 882 AC_PATH_REGISTERED = 0x020,/* A new path has been registered */ 883 AC_SENT_BDR = 0x010,/* A BDR message was sent to target */ 884 AC_SCSI_AEN = 0x008,/* A SCSI AEN has been received */ 885 AC_UNSOL_RESEL = 0x002,/* Unsolicited reselection occurred */ 886 AC_BUS_RESET = 0x001 /* A SCSI bus reset occurred */ 887 } ac_code; 888 889 typedef void ac_callback_t (void *softc, uint32_t code, 890 struct cam_path *path, void *args); 891 892 /* 893 * Generic Asynchronous callbacks. 894 * 895 * Generic arguments passed bac which are then interpreted between a per-system 896 * contract number. 897 */ 898 #define AC_CONTRACT_DATA_MAX (128 - sizeof (uint64_t)) 899 struct ac_contract { 900 uint64_t contract_number; 901 uint8_t contract_data[AC_CONTRACT_DATA_MAX]; 902 }; 903 904 #define AC_CONTRACT_DEV_CHG 1 905 struct ac_device_changed { 906 uint64_t wwpn; 907 uint32_t port; 908 target_id_t target; 909 uint8_t arrived; 910 }; 911 912 /* Set Asynchronous Callback CCB */ 913 struct ccb_setasync { 914 struct ccb_hdr ccb_h; 915 uint32_t event_enable; /* Async Event enables */ 916 ac_callback_t *callback; 917 void *callback_arg; 918 }; 919 920 /* Set Device Type CCB */ 921 struct ccb_setdev { 922 struct ccb_hdr ccb_h; 923 uint8_t dev_type; /* Value for dev type field in EDT */ 924 }; 925 926 /* SCSI Control Functions */ 927 928 /* Abort XPT request CCB */ 929 struct ccb_abort { 930 struct ccb_hdr ccb_h; 931 union ccb *abort_ccb; /* Pointer to CCB to abort */ 932 }; 933 934 /* Reset SCSI Bus CCB */ 935 struct ccb_resetbus { 936 struct ccb_hdr ccb_h; 937 }; 938 939 /* Reset SCSI Device CCB */ 940 struct ccb_resetdev { 941 struct ccb_hdr ccb_h; 942 }; 943 944 /* Terminate I/O Process Request CCB */ 945 struct ccb_termio { 946 struct ccb_hdr ccb_h; 947 union ccb *termio_ccb; /* Pointer to CCB to terminate */ 948 }; 949 950 typedef enum { 951 CTS_TYPE_CURRENT_SETTINGS, 952 CTS_TYPE_USER_SETTINGS 953 } cts_type; 954 955 struct ccb_trans_settings_scsi 956 { 957 u_int valid; /* Which fields to honor */ 958 #define CTS_SCSI_VALID_TQ 0x01 959 u_int flags; 960 #define CTS_SCSI_FLAGS_TAG_ENB 0x01 961 }; 962 963 struct ccb_trans_settings_ata 964 { 965 u_int valid; /* Which fields to honor */ 966 #define CTS_ATA_VALID_TQ 0x01 967 u_int flags; 968 #define CTS_ATA_FLAGS_TAG_ENB 0x01 969 }; 970 971 struct ccb_trans_settings_spi 972 { 973 u_int valid; /* Which fields to honor */ 974 #define CTS_SPI_VALID_SYNC_RATE 0x01 975 #define CTS_SPI_VALID_SYNC_OFFSET 0x02 976 #define CTS_SPI_VALID_BUS_WIDTH 0x04 977 #define CTS_SPI_VALID_DISC 0x08 978 #define CTS_SPI_VALID_PPR_OPTIONS 0x10 979 u_int flags; 980 #define CTS_SPI_FLAGS_DISC_ENB 0x01 981 u_int sync_period; 982 u_int sync_offset; 983 u_int bus_width; 984 u_int ppr_options; 985 }; 986 987 struct ccb_trans_settings_fc { 988 u_int valid; /* Which fields to honor */ 989 #define CTS_FC_VALID_WWNN 0x8000 990 #define CTS_FC_VALID_WWPN 0x4000 991 #define CTS_FC_VALID_PORT 0x2000 992 #define CTS_FC_VALID_SPEED 0x1000 993 uint64_t wwnn; /* world wide node name */ 994 uint64_t wwpn; /* world wide port name */ 995 uint32_t port; /* 24 bit port id, if known */ 996 uint32_t bitrate; /* Mbps */ 997 }; 998 999 struct ccb_trans_settings_sas { 1000 u_int valid; /* Which fields to honor */ 1001 #define CTS_SAS_VALID_SPEED 0x1000 1002 uint32_t bitrate; /* Mbps */ 1003 }; 1004 1005 struct ccb_trans_settings_pata { 1006 u_int valid; /* Which fields to honor */ 1007 #define CTS_ATA_VALID_MODE 0x01 1008 #define CTS_ATA_VALID_BYTECOUNT 0x02 1009 #define CTS_ATA_VALID_ATAPI 0x20 1010 #define CTS_ATA_VALID_CAPS 0x40 1011 int mode; /* Mode */ 1012 u_int bytecount; /* Length of PIO transaction */ 1013 u_int atapi; /* Length of ATAPI CDB */ 1014 u_int caps; /* Device and host SATA caps. */ 1015 #define CTS_ATA_CAPS_H 0x0000ffff 1016 #define CTS_ATA_CAPS_H_DMA48 0x00000001 /* 48-bit DMA */ 1017 #define CTS_ATA_CAPS_D 0xffff0000 1018 }; 1019 1020 struct ccb_trans_settings_sata { 1021 u_int valid; /* Which fields to honor */ 1022 #define CTS_SATA_VALID_MODE 0x01 1023 #define CTS_SATA_VALID_BYTECOUNT 0x02 1024 #define CTS_SATA_VALID_REVISION 0x04 1025 #define CTS_SATA_VALID_PM 0x08 1026 #define CTS_SATA_VALID_TAGS 0x10 1027 #define CTS_SATA_VALID_ATAPI 0x20 1028 #define CTS_SATA_VALID_CAPS 0x40 1029 int mode; /* Legacy PATA mode */ 1030 u_int bytecount; /* Length of PIO transaction */ 1031 int revision; /* SATA revision */ 1032 u_int pm_present; /* PM is present (XPT->SIM) */ 1033 u_int tags; /* Number of allowed tags */ 1034 u_int atapi; /* Length of ATAPI CDB */ 1035 u_int caps; /* Device and host SATA caps. */ 1036 #define CTS_SATA_CAPS_H 0x0000ffff 1037 #define CTS_SATA_CAPS_H_PMREQ 0x00000001 1038 #define CTS_SATA_CAPS_H_APST 0x00000002 1039 #define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */ 1040 #define CTS_SATA_CAPS_H_AN 0x00000020 /* Async. notification */ 1041 #define CTS_SATA_CAPS_D 0xffff0000 1042 #define CTS_SATA_CAPS_D_PMREQ 0x00010000 1043 #define CTS_SATA_CAPS_D_APST 0x00020000 1044 }; 1045 1046 struct ccb_trans_settings_nvme 1047 { 1048 u_int valid; /* Which fields to honor */ 1049 #define CTS_NVME_VALID_SPEC 0x01 1050 #define CTS_NVME_VALID_CAPS 0x02 1051 #define CTS_NVME_VALID_LINK 0x04 1052 uint32_t spec; /* NVMe spec implemented -- same as vs register */ 1053 uint32_t max_xfer; /* Max transfer size (0 -> unlimited */ 1054 uint32_t caps; 1055 uint8_t lanes; /* Number of PCIe lanes */ 1056 uint8_t speed; /* PCIe generation for each lane */ 1057 uint8_t max_lanes; /* Number of PCIe lanes */ 1058 uint8_t max_speed; /* PCIe generation for each lane */ 1059 }; 1060 1061 struct ccb_trans_settings_nvmf 1062 { 1063 u_int valid; /* Which fields to honor */ 1064 #define CTS_NVMF_VALID_TRTYPE 0x01 1065 uint8_t trtype; 1066 }; 1067 1068 #include <cam/mmc/mmc_bus.h> 1069 struct ccb_trans_settings_mmc { 1070 struct mmc_ios ios; 1071 #define MMC_CLK (1 << 1) 1072 #define MMC_VDD (1 << 2) 1073 #define MMC_CS (1 << 3) 1074 #define MMC_BW (1 << 4) 1075 #define MMC_PM (1 << 5) 1076 #define MMC_BT (1 << 6) 1077 #define MMC_BM (1 << 7) 1078 #define MMC_VCCQ (1 << 8) 1079 uint32_t ios_valid; 1080 /* The folowing is used only for GET_TRAN_SETTINGS */ 1081 uint32_t host_ocr; 1082 int host_f_min; 1083 int host_f_max; 1084 /* Copied from sys/dev/mmc/bridge.h */ 1085 #define MMC_CAP_4_BIT_DATA (1 << 0) /* Can do 4-bit data transfers */ 1086 #define MMC_CAP_8_BIT_DATA (1 << 1) /* Can do 8-bit data transfers */ 1087 #define MMC_CAP_HSPEED (1 << 2) /* Can do High Speed transfers */ 1088 #define MMC_CAP_BOOT_NOACC (1 << 4) /* Cannot access boot partitions */ 1089 #define MMC_CAP_WAIT_WHILE_BUSY (1 << 5) /* Host waits for busy responses */ 1090 #define MMC_CAP_UHS_SDR12 (1 << 6) /* Can do UHS SDR12 */ 1091 #define MMC_CAP_UHS_SDR25 (1 << 7) /* Can do UHS SDR25 */ 1092 #define MMC_CAP_UHS_SDR50 (1 << 8) /* Can do UHS SDR50 */ 1093 #define MMC_CAP_UHS_SDR104 (1 << 9) /* Can do UHS SDR104 */ 1094 #define MMC_CAP_UHS_DDR50 (1 << 10) /* Can do UHS DDR50 */ 1095 #define MMC_CAP_MMC_DDR52_120 (1 << 11) /* Can do eMMC DDR52 at 1.2 V */ 1096 #define MMC_CAP_MMC_DDR52_180 (1 << 12) /* Can do eMMC DDR52 at 1.8 V */ 1097 #define MMC_CAP_MMC_DDR52 (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180) 1098 #define MMC_CAP_MMC_HS200_120 (1 << 13) /* Can do eMMC HS200 at 1.2 V */ 1099 #define MMC_CAP_MMC_HS200_180 (1 << 14) /* Can do eMMC HS200 at 1.8 V */ 1100 #define MMC_CAP_MMC_HS200 (MMC_CAP_MMC_HS200_120| MMC_CAP_MMC_HS200_180) 1101 #define MMC_CAP_MMC_HS400_120 (1 << 15) /* Can do eMMC HS400 at 1.2 V */ 1102 #define MMC_CAP_MMC_HS400_180 (1 << 16) /* Can do eMMC HS400 at 1.8 V */ 1103 #define MMC_CAP_MMC_HS400 (MMC_CAP_MMC_HS400_120 | MMC_CAP_MMC_HS400_180) 1104 #define MMC_CAP_MMC_HSX00_120 (MMC_CAP_MMC_HS200_120 | MMC_CAP_MMC_HS400_120) 1105 #define MMC_CAP_MMC_ENH_STROBE (1 << 17) /* Can do eMMC Enhanced Strobe */ 1106 #define MMC_CAP_SIGNALING_120 (1 << 18) /* Can do signaling at 1.2 V */ 1107 #define MMC_CAP_SIGNALING_180 (1 << 19) /* Can do signaling at 1.8 V */ 1108 #define MMC_CAP_SIGNALING_330 (1 << 20) /* Can do signaling at 3.3 V */ 1109 #define MMC_CAP_DRIVER_TYPE_A (1 << 21) /* Can do Driver Type A */ 1110 #define MMC_CAP_DRIVER_TYPE_C (1 << 22) /* Can do Driver Type C */ 1111 #define MMC_CAP_DRIVER_TYPE_D (1 << 23) /* Can do Driver Type D */ 1112 1113 uint32_t host_caps; 1114 uint32_t host_max_data; 1115 }; 1116 1117 /* Get/Set transfer rate/width/disconnection/tag queueing settings */ 1118 struct ccb_trans_settings { 1119 struct ccb_hdr ccb_h; 1120 cts_type type; /* Current or User settings */ 1121 cam_proto protocol; 1122 u_int protocol_version; 1123 cam_xport transport; 1124 u_int transport_version; 1125 union { 1126 u_int valid; /* Which fields to honor */ 1127 struct ccb_trans_settings_ata ata; 1128 struct ccb_trans_settings_scsi scsi; 1129 struct ccb_trans_settings_nvme nvme; 1130 struct ccb_trans_settings_mmc mmc; 1131 } proto_specific; 1132 union { 1133 u_int valid; /* Which fields to honor */ 1134 struct ccb_trans_settings_spi spi; 1135 struct ccb_trans_settings_fc fc; 1136 struct ccb_trans_settings_sas sas; 1137 struct ccb_trans_settings_pata ata; 1138 struct ccb_trans_settings_sata sata; 1139 struct ccb_trans_settings_nvme nvme; 1140 struct ccb_trans_settings_nvmf nvmf; 1141 } xport_specific; 1142 }; 1143 1144 /* 1145 * Calculate the geometry parameters for a device 1146 * give the block size and volume size in blocks. 1147 */ 1148 struct ccb_calc_geometry { 1149 struct ccb_hdr ccb_h; 1150 uint32_t block_size; 1151 uint64_t volume_size; 1152 uint32_t cylinders; 1153 uint8_t heads; 1154 uint8_t secs_per_track; 1155 }; 1156 1157 /* 1158 * Set or get SIM (and transport) specific knobs 1159 */ 1160 1161 #define KNOB_VALID_ADDRESS 0x1 1162 #define KNOB_VALID_ROLE 0x2 1163 1164 #define KNOB_ROLE_NONE 0x0 1165 #define KNOB_ROLE_INITIATOR 0x1 1166 #define KNOB_ROLE_TARGET 0x2 1167 #define KNOB_ROLE_BOTH 0x3 1168 1169 struct ccb_sim_knob_settings_spi { 1170 u_int valid; 1171 u_int initiator_id; 1172 u_int role; 1173 }; 1174 1175 struct ccb_sim_knob_settings_fc { 1176 u_int valid; 1177 uint64_t wwnn; /* world wide node name */ 1178 uint64_t wwpn; /* world wide port name */ 1179 u_int role; 1180 }; 1181 1182 struct ccb_sim_knob_settings_sas { 1183 u_int valid; 1184 uint64_t wwnn; /* world wide node name */ 1185 u_int role; 1186 }; 1187 #define KNOB_SETTINGS_SIZE 128 1188 1189 struct ccb_sim_knob { 1190 struct ccb_hdr ccb_h; 1191 union { 1192 u_int valid; /* Which fields to honor */ 1193 struct ccb_sim_knob_settings_spi spi; 1194 struct ccb_sim_knob_settings_fc fc; 1195 struct ccb_sim_knob_settings_sas sas; 1196 char pad[KNOB_SETTINGS_SIZE]; 1197 } xport_specific; 1198 }; 1199 1200 /* 1201 * Rescan the given bus, or bus/target/lun 1202 */ 1203 struct ccb_rescan { 1204 struct ccb_hdr ccb_h; 1205 cam_flags flags; 1206 }; 1207 1208 /* 1209 * Turn on debugging for the given bus, bus/target, or bus/target/lun. 1210 */ 1211 struct ccb_debug { 1212 struct ccb_hdr ccb_h; 1213 cam_debug_flags flags; 1214 }; 1215 1216 /* Target mode structures. */ 1217 1218 struct ccb_en_lun { 1219 struct ccb_hdr ccb_h; 1220 uint16_t grp6_len; /* Group 6 VU CDB length */ 1221 uint16_t grp7_len; /* Group 7 VU CDB length */ 1222 uint8_t enable; 1223 }; 1224 1225 /* old, barely used immediate notify, binary compatibility */ 1226 struct ccb_immed_notify { 1227 struct ccb_hdr ccb_h; 1228 struct scsi_sense_data sense_data; 1229 uint8_t sense_len; /* Number of bytes in sense buffer */ 1230 uint8_t initiator_id; /* Id of initiator that selected */ 1231 uint8_t message_args[7]; /* Message Arguments */ 1232 }; 1233 1234 struct ccb_notify_ack { 1235 struct ccb_hdr ccb_h; 1236 uint16_t seq_id; /* Sequence identifier */ 1237 uint8_t event; /* Event flags */ 1238 }; 1239 1240 struct ccb_immediate_notify { 1241 struct ccb_hdr ccb_h; 1242 u_int tag_id; /* Tag for immediate notify */ 1243 u_int seq_id; /* Tag for target of notify */ 1244 u_int initiator_id; /* Initiator Identifier */ 1245 u_int arg; /* Function specific */ 1246 }; 1247 1248 struct ccb_notify_acknowledge { 1249 struct ccb_hdr ccb_h; 1250 u_int tag_id; /* Tag for immediate notify */ 1251 u_int seq_id; /* Tar for target of notify */ 1252 u_int initiator_id; /* Initiator Identifier */ 1253 u_int arg; /* Response information */ 1254 /* 1255 * Lower byte of arg is one of RESPONSE CODE values defined below 1256 * (subset of response codes from SPL-4 and FCP-4 specifications), 1257 * upper 3 bytes is code-specific ADDITIONAL RESPONSE INFORMATION. 1258 */ 1259 #define CAM_RSP_TMF_COMPLETE 0x00 1260 #define CAM_RSP_TMF_REJECTED 0x04 1261 #define CAM_RSP_TMF_FAILED 0x05 1262 #define CAM_RSP_TMF_SUCCEEDED 0x08 1263 #define CAM_RSP_TMF_INCORRECT_LUN 0x09 1264 }; 1265 1266 /* HBA engine structures. */ 1267 1268 typedef enum { 1269 EIT_BUFFER, /* Engine type: buffer memory */ 1270 EIT_LOSSLESS, /* Engine type: lossless compression */ 1271 EIT_LOSSY, /* Engine type: lossy compression */ 1272 EIT_ENCRYPT /* Engine type: encryption */ 1273 } ei_type; 1274 1275 typedef enum { 1276 EAD_VUNIQUE, /* Engine algorithm ID: vendor unique */ 1277 EAD_LZ1V1, /* Engine algorithm ID: LZ1 var.1 */ 1278 EAD_LZ2V1, /* Engine algorithm ID: LZ2 var.1 */ 1279 EAD_LZ2V2 /* Engine algorithm ID: LZ2 var.2 */ 1280 } ei_algo; 1281 1282 struct ccb_eng_inq { 1283 struct ccb_hdr ccb_h; 1284 uint16_t eng_num; /* The engine number for this inquiry */ 1285 ei_type eng_type; /* Returned engine type */ 1286 ei_algo eng_algo; /* Returned engine algorithm type */ 1287 uint32_t eng_memeory; /* Returned engine memory size */ 1288 }; 1289 1290 struct ccb_eng_exec { /* This structure must match SCSIIO size */ 1291 struct ccb_hdr ccb_h; 1292 uint8_t *pdrv_ptr; /* Ptr used by the peripheral driver */ 1293 uint8_t *req_map; /* Ptr for mapping info on the req. */ 1294 uint8_t *data_ptr; /* Pointer to the data buf/SG list */ 1295 uint32_t dxfer_len; /* Data transfer length */ 1296 uint8_t *engdata_ptr; /* Pointer to the engine buffer data */ 1297 uint16_t sglist_cnt; /* Num of scatter gather list entries */ 1298 uint32_t dmax_len; /* Destination data maximum length */ 1299 uint32_t dest_len; /* Destination data length */ 1300 int32_t src_resid; /* Source residual length: 2's comp */ 1301 uint32_t timeout; /* Timeout value */ 1302 uint16_t eng_num; /* Engine number for this request */ 1303 uint16_t vu_flags; /* Vendor Unique flags */ 1304 }; 1305 1306 /* 1307 * Definitions for the timeout field in the SCSI I/O CCB. 1308 */ 1309 #define CAM_TIME_DEFAULT 0x00000000 /* Use SIM default value */ 1310 #define CAM_TIME_INFINITY 0xFFFFFFFF /* Infinite timeout */ 1311 1312 #define CAM_SUCCESS 0 /* For signaling general success */ 1313 1314 #define XPT_CCB_INVALID -1 /* for signaling a bad CCB to free */ 1315 1316 /* 1317 * CCB for working with advanced device information. This operates in a fashion 1318 * similar to XPT_GDEV_TYPE. Specify the target in ccb_h, the buffer 1319 * type requested, and provide a buffer size/buffer to write to. If the 1320 * buffer is too small, provsiz will be larger than bufsiz. 1321 */ 1322 struct ccb_dev_advinfo { 1323 struct ccb_hdr ccb_h; 1324 uint32_t flags; 1325 #define CDAI_FLAG_NONE 0x0 /* No flags set */ 1326 #define CDAI_FLAG_STORE 0x1 /* If set, action becomes store */ 1327 uint32_t buftype; /* IN: Type of data being requested */ 1328 /* NB: buftype is interpreted on a per-transport basis */ 1329 #define CDAI_TYPE_SCSI_DEVID 1 1330 #define CDAI_TYPE_SERIAL_NUM 2 1331 #define CDAI_TYPE_PHYS_PATH 3 1332 #define CDAI_TYPE_RCAPLONG 4 1333 #define CDAI_TYPE_EXT_INQ 5 1334 #define CDAI_TYPE_NVME_CNTRL 6 /* NVMe Identify Controller data */ 1335 #define CDAI_TYPE_NVME_NS 7 /* NVMe Identify Namespace data */ 1336 #define CDAI_TYPE_MMC_PARAMS 8 /* MMC/SD ident */ 1337 off_t bufsiz; /* IN: Size of external buffer */ 1338 #define CAM_SCSI_DEVID_MAXLEN 65536 /* length in buffer is an uint16_t */ 1339 off_t provsiz; /* OUT: Size required/used */ 1340 uint8_t *buf; /* IN/OUT: Buffer for requested data */ 1341 }; 1342 1343 /* 1344 * CCB for sending async events 1345 */ 1346 struct ccb_async { 1347 struct ccb_hdr ccb_h; 1348 uint32_t async_code; 1349 off_t async_arg_size; 1350 void *async_arg_ptr; 1351 }; 1352 1353 /* 1354 * Union of all CCB types for kernel space allocation. This union should 1355 * never be used for manipulating CCBs - its only use is for the allocation 1356 * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 1357 * and the argument to xpt_ccb_free. 1358 */ 1359 union ccb { 1360 struct ccb_hdr ccb_h; /* For convenience */ 1361 struct ccb_scsiio csio; 1362 struct ccb_getdev cgd; 1363 struct ccb_getdevlist cgdl; 1364 struct ccb_pathinq cpi; 1365 struct ccb_relsim crs; 1366 struct ccb_setasync csa; 1367 struct ccb_setdev csd; 1368 struct ccb_pathstats cpis; 1369 struct ccb_getdevstats cgds; 1370 struct ccb_dev_match cdm; 1371 struct ccb_trans_settings cts; 1372 struct ccb_calc_geometry ccg; 1373 struct ccb_sim_knob knob; 1374 struct ccb_abort cab; 1375 struct ccb_resetbus crb; 1376 struct ccb_resetdev crd; 1377 struct ccb_termio tio; 1378 struct ccb_accept_tio atio; 1379 struct ccb_scsiio ctio; 1380 struct ccb_en_lun cel; 1381 struct ccb_immed_notify cin; 1382 struct ccb_notify_ack cna; 1383 struct ccb_immediate_notify cin1; 1384 struct ccb_notify_acknowledge cna2; 1385 struct ccb_eng_inq cei; 1386 struct ccb_eng_exec cee; 1387 struct ccb_smpio smpio; 1388 struct ccb_rescan crcn; 1389 struct ccb_debug cdbg; 1390 struct ccb_ataio ataio; 1391 struct ccb_dev_advinfo cdai; 1392 struct ccb_async casync; 1393 struct ccb_nvmeio nvmeio; 1394 struct ccb_mmcio mmcio; 1395 }; 1396 1397 #define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \ 1398 bzero((char *)(ccbp) + sizeof((ccbp)->ccb_h), \ 1399 sizeof(*(ccbp)) - sizeof((ccbp)->ccb_h)) 1400 1401 __BEGIN_DECLS 1402 static __inline void 1403 cam_fill_csio(struct ccb_scsiio *csio, uint32_t retries, 1404 void (*cbfcnp)(struct cam_periph *, union ccb *), 1405 uint32_t flags, uint8_t tag_action, 1406 uint8_t *data_ptr, uint32_t dxfer_len, 1407 uint8_t sense_len, uint8_t cdb_len, 1408 uint32_t timeout) 1409 { 1410 csio->ccb_h.func_code = XPT_SCSI_IO; 1411 csio->ccb_h.flags = flags; 1412 csio->ccb_h.xflags = 0; 1413 csio->ccb_h.retry_count = retries; 1414 csio->ccb_h.cbfcnp = cbfcnp; 1415 csio->ccb_h.timeout = timeout; 1416 csio->data_ptr = data_ptr; 1417 csio->dxfer_len = dxfer_len; 1418 csio->sense_len = sense_len; 1419 csio->cdb_len = cdb_len; 1420 csio->tag_action = tag_action; 1421 csio->priority = 0; 1422 #if defined(BUF_TRACKING) || defined(FULL_BUF_TRACKING) 1423 csio->bio = NULL; 1424 #endif 1425 } 1426 1427 static __inline void 1428 cam_fill_ctio(struct ccb_scsiio *csio, uint32_t retries, 1429 void (*cbfcnp)(struct cam_periph *, union ccb *), 1430 uint32_t flags, u_int tag_action, u_int tag_id, 1431 u_int init_id, u_int scsi_status, uint8_t *data_ptr, 1432 uint32_t dxfer_len, uint32_t timeout) 1433 { 1434 csio->ccb_h.func_code = XPT_CONT_TARGET_IO; 1435 csio->ccb_h.flags = flags; 1436 csio->ccb_h.xflags = 0; 1437 csio->ccb_h.retry_count = retries; 1438 csio->ccb_h.cbfcnp = cbfcnp; 1439 csio->ccb_h.timeout = timeout; 1440 csio->data_ptr = data_ptr; 1441 csio->dxfer_len = dxfer_len; 1442 csio->scsi_status = scsi_status; 1443 csio->tag_action = tag_action; 1444 csio->priority = 0; 1445 csio->tag_id = tag_id; 1446 csio->init_id = init_id; 1447 } 1448 1449 static __inline void 1450 cam_fill_ataio(struct ccb_ataio *ataio, uint32_t retries, 1451 void (*cbfcnp)(struct cam_periph *, union ccb *), 1452 uint32_t flags, u_int tag_action __unused, 1453 uint8_t *data_ptr, uint32_t dxfer_len, 1454 uint32_t timeout) 1455 { 1456 ataio->ccb_h.func_code = XPT_ATA_IO; 1457 ataio->ccb_h.flags = flags; 1458 ataio->ccb_h.retry_count = retries; 1459 ataio->ccb_h.cbfcnp = cbfcnp; 1460 ataio->ccb_h.timeout = timeout; 1461 ataio->data_ptr = data_ptr; 1462 ataio->dxfer_len = dxfer_len; 1463 ataio->ata_flags = 0; 1464 } 1465 1466 static __inline void 1467 cam_fill_smpio(struct ccb_smpio *smpio, uint32_t retries, 1468 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1469 uint8_t *smp_request, int smp_request_len, 1470 uint8_t *smp_response, int smp_response_len, 1471 uint32_t timeout) 1472 { 1473 #ifdef _KERNEL 1474 KASSERT((flags & CAM_DIR_MASK) == CAM_DIR_BOTH, 1475 ("direction != CAM_DIR_BOTH")); 1476 KASSERT((smp_request != NULL) && (smp_response != NULL), 1477 ("need valid request and response buffers")); 1478 KASSERT((smp_request_len != 0) && (smp_response_len != 0), 1479 ("need non-zero request and response lengths")); 1480 #endif /*_KERNEL*/ 1481 smpio->ccb_h.func_code = XPT_SMP_IO; 1482 smpio->ccb_h.flags = flags; 1483 smpio->ccb_h.retry_count = retries; 1484 smpio->ccb_h.cbfcnp = cbfcnp; 1485 smpio->ccb_h.timeout = timeout; 1486 smpio->smp_request = smp_request; 1487 smpio->smp_request_len = smp_request_len; 1488 smpio->smp_response = smp_response; 1489 smpio->smp_response_len = smp_response_len; 1490 } 1491 1492 static __inline void 1493 cam_fill_mmcio(struct ccb_mmcio *mmcio, uint32_t retries, 1494 void (*cbfcnp)(struct cam_periph *, union ccb *), uint32_t flags, 1495 uint32_t mmc_opcode, uint32_t mmc_arg, uint32_t mmc_flags, 1496 struct mmc_data *mmc_d, 1497 uint32_t timeout) 1498 { 1499 mmcio->ccb_h.func_code = XPT_MMC_IO; 1500 mmcio->ccb_h.flags = flags; 1501 mmcio->ccb_h.retry_count = retries; 1502 mmcio->ccb_h.cbfcnp = cbfcnp; 1503 mmcio->ccb_h.timeout = timeout; 1504 mmcio->cmd.opcode = mmc_opcode; 1505 mmcio->cmd.arg = mmc_arg; 1506 mmcio->cmd.flags = mmc_flags; 1507 mmcio->stop.opcode = 0; 1508 mmcio->stop.arg = 0; 1509 mmcio->stop.flags = 0; 1510 if (mmc_d != NULL) { 1511 mmcio->cmd.data = mmc_d; 1512 } else 1513 mmcio->cmd.data = NULL; 1514 mmcio->cmd.resp[0] = 0; 1515 mmcio->cmd.resp[1] = 0; 1516 mmcio->cmd.resp[2] = 0; 1517 mmcio->cmd.resp[3] = 0; 1518 } 1519 1520 static __inline void 1521 cam_set_ccbstatus(union ccb *ccb, cam_status status) 1522 { 1523 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1524 ccb->ccb_h.status |= status; 1525 } 1526 1527 static __inline cam_status 1528 cam_ccb_status(union ccb *ccb) 1529 { 1530 return ((cam_status)(ccb->ccb_h.status & CAM_STATUS_MASK)); 1531 } 1532 1533 static inline bool 1534 cam_ccb_success(union ccb *ccb) 1535 { 1536 return (cam_ccb_status(ccb) == CAM_REQ_CMP); 1537 } 1538 1539 void cam_calc_geometry(struct ccb_calc_geometry *ccg, int extended); 1540 1541 static __inline void 1542 cam_fill_nvmeio(struct ccb_nvmeio *nvmeio, uint32_t retries, 1543 void (*cbfcnp)(struct cam_periph *, union ccb *), 1544 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len, 1545 uint32_t timeout) 1546 { 1547 nvmeio->ccb_h.func_code = XPT_NVME_IO; 1548 nvmeio->ccb_h.flags = flags; 1549 nvmeio->ccb_h.retry_count = retries; 1550 nvmeio->ccb_h.cbfcnp = cbfcnp; 1551 nvmeio->ccb_h.timeout = timeout; 1552 nvmeio->data_ptr = data_ptr; 1553 nvmeio->dxfer_len = dxfer_len; 1554 } 1555 1556 static __inline void 1557 cam_fill_nvmeadmin(struct ccb_nvmeio *nvmeio, uint32_t retries, 1558 void (*cbfcnp)(struct cam_periph *, union ccb *), 1559 uint32_t flags, uint8_t *data_ptr, uint32_t dxfer_len, 1560 uint32_t timeout) 1561 { 1562 nvmeio->ccb_h.func_code = XPT_NVME_ADMIN; 1563 nvmeio->ccb_h.flags = flags; 1564 nvmeio->ccb_h.retry_count = retries; 1565 nvmeio->ccb_h.cbfcnp = cbfcnp; 1566 nvmeio->ccb_h.timeout = timeout; 1567 nvmeio->data_ptr = data_ptr; 1568 nvmeio->dxfer_len = dxfer_len; 1569 } 1570 __END_DECLS 1571 1572 #endif /* _CAM_CAM_CCB_H */ 1573