1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2015 Mihai Carabas <mihai.carabas@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _VMM_VGIC_V3_H_ 30 #define _VMM_VGIC_V3_H_ 31 32 #define VGIC_ICH_LR_NUM_MAX 16 33 #define VGIC_ICH_APR_NUM_MAX 4 34 35 /* Registers accessed by EL2 */ 36 struct vgic_v3_regs { 37 uint32_t ich_eisr_el2; /* End of Interrupt Status Register */ 38 uint32_t ich_elrsr_el2; /* Empty List register Status Register (ICH_ELRSR_EL2) */ 39 uint32_t ich_hcr_el2; /* Hyp Control Register */ 40 uint32_t ich_misr_el2; /* Maintenance Interrupt State Register */ 41 uint32_t ich_vmcr_el2; /* Virtual Machine Control Register */ 42 43 /* 44 * The List Registers are part of the VM context and are modified on a 45 * world switch. They need to be allocated statically so they are 46 * mapped in the EL2 translation tables when struct hypctx is mapped. 47 */ 48 uint64_t ich_lr_el2[VGIC_ICH_LR_NUM_MAX]; 49 uint16_t ich_lr_num; 50 51 /* Active Priorities Registers for Group 0 and 1 interrupts */ 52 uint16_t ich_apr_num; 53 uint32_t ich_ap0r_el2[VGIC_ICH_APR_NUM_MAX]; 54 uint32_t ich_ap1r_el2[VGIC_ICH_APR_NUM_MAX]; 55 }; 56 57 #endif /* !_VMM_VGIC_V3_H_ */ 58