1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ganbold Tsagaankhuu <ganbold@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Rockchip RK3399 eMMC PHY 31 */ 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/rman.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/gpio.h> 41 #include <machine/bus.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/extres/clk/clk.h> 48 #include <dev/extres/syscon/syscon.h> 49 #include <dev/extres/phy/phy.h> 50 51 #include "syscon_if.h" 52 53 #define GRF_EMMCPHY_BASE 0xf780 54 #define GRF_EMMCPHY_CON0 (GRF_EMMCPHY_BASE + 0x00) 55 #define PHYCTRL_FRQSEL (1 << 13) | (1 << 12) 56 #define PHYCTRL_FRQSEL_200M 0 57 #define PHYCTRL_FRQSEL_50M 1 58 #define PHYCTRL_FRQSEL_100M 2 59 #define PHYCTRL_FRQSEL_150M 3 60 #define PHYCTRL_OTAPDLYENA (1 << 11) 61 #define PHYCTRL_OTAPDLYSEL (1 << 10) | (1 << 9) | (1 << 8) | (1 << 7) 62 #define PHYCTRL_ITAPCHGWIN (1 << 6) 63 #define PHYCTRL_ITAPDLYSEL (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) | \ 64 (1 << 1) 65 #define PHYCTRL_ITAPDLYENA (1 << 0) 66 #define GRF_EMMCPHY_CON1 (GRF_EMMCPHY_BASE + 0x04) 67 #define PHYCTRL_CLKBUFSEL (1 << 8) | (1 << 7) | (1 << 6) 68 #define PHYCTRL_SELDLYTXCLK (1 << 5) 69 #define PHYCTRL_SELDLYRXCLK (1 << 4) 70 #define PHYCTRL_STRBSEL 0xf 71 #define GRF_EMMCPHY_CON2 (GRF_EMMCPHY_BASE + 0x08) 72 #define PHYCTRL_REN_STRB (1 << 9) 73 #define PHYCTRL_REN_CMD (1 << 8) 74 #define PHYCTRL_REN_DAT 0xff 75 #define GRF_EMMCPHY_CON3 (GRF_EMMCPHY_BASE + 0x0c) 76 #define PHYCTRL_PU_STRB (1 << 9) 77 #define PHYCTRL_PU_CMD (1 << 8) 78 #define PHYCTRL_PU_DAT 0xff 79 #define GRF_EMMCPHY_CON4 (GRF_EMMCPHY_BASE + 0x10) 80 #define PHYCTRL_OD_RELEASE_CMD (1 << 9) 81 #define PHYCTRL_OD_RELEASE_STRB (1 << 8) 82 #define PHYCTRL_OD_RELEASE_DAT 0xff 83 #define GRF_EMMCPHY_CON5 (GRF_EMMCPHY_BASE + 0x14) 84 #define PHYCTRL_ODEN_STRB (1 << 9) 85 #define PHYCTRL_ODEN_CMD (1 << 8) 86 #define PHYCTRL_ODEN_DAT 0xff 87 #define GRF_EMMCPHY_CON6 (GRF_EMMCPHY_BASE + 0x18) 88 #define PHYCTRL_DLL_TRM_ICP (1 << 12) | (1 << 11) | (1 << 10) | (1 << 9) 89 #define PHYCTRL_EN_RTRIM (1 << 8) 90 #define PHYCTRL_RETRIM (1 << 7) 91 #define PHYCTRL_DR_TY (1 << 6) | (1 << 5) | (1 << 4) 92 #define PHYCTRL_RETENB (1 << 3) 93 #define PHYCTRL_RETEN (1 << 2) 94 #define PHYCTRL_ENDLL (1 << 1) 95 #define PHYCTRL_PDB (1 << 0) 96 #define GRF_EMMCPHY_STATUS (GRF_EMMCPHY_BASE + 0x20) 97 #define PHYCTRL_CALDONE (1 << 6) 98 #define PHYCTRL_DLLRDY (1 << 5) 99 #define PHYCTRL_RTRIM (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1) 100 #define PHYCTRL_EXR_NINST (1 << 0) 101 102 static struct ofw_compat_data compat_data[] = { 103 { "rockchip,rk3399-emmc-phy", 1 }, 104 { NULL, 0 } 105 }; 106 107 struct rk_emmcphy_softc { 108 struct syscon *syscon; 109 struct rk_emmcphy_conf *phy_conf; 110 clk_t clk; 111 }; 112 113 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask)) 114 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask)) 115 116 /* Phy class and methods. */ 117 static int rk_emmcphy_enable(struct phynode *phynode, bool enable); 118 static phynode_method_t rk_emmcphy_phynode_methods[] = { 119 PHYNODEMETHOD(phynode_enable, rk_emmcphy_enable), 120 PHYNODEMETHOD_END 121 }; 122 123 DEFINE_CLASS_1(rk_emmcphy_phynode, rk_emmcphy_phynode_class, 124 rk_emmcphy_phynode_methods, 0, phynode_class); 125 126 static int 127 rk_emmcphy_enable(struct phynode *phynode, bool enable) 128 { 129 struct rk_emmcphy_softc *sc; 130 device_t dev; 131 intptr_t phy; 132 uint64_t rate, frqsel; 133 uint32_t mask, val; 134 int error; 135 136 dev = phynode_get_device(phynode); 137 phy = phynode_get_id(phynode); 138 sc = device_get_softc(dev); 139 140 if (bootverbose) 141 device_printf(dev, "Phy id: %ld\n", phy); 142 143 if (phy != 0) { 144 device_printf(dev, "Unknown phy: %ld\n", phy); 145 return (ERANGE); 146 } 147 if (enable) { 148 /* Drive strength */ 149 mask = PHYCTRL_DR_TY; 150 val = SHIFTIN(0, PHYCTRL_DR_TY); 151 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, 152 (mask << 16) | val); 153 154 /* Enable output tap delay */ 155 mask = PHYCTRL_OTAPDLYENA | PHYCTRL_OTAPDLYSEL; 156 val = PHYCTRL_OTAPDLYENA | SHIFTIN(4, PHYCTRL_OTAPDLYSEL); 157 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0, 158 (mask << 16) | val); 159 } 160 161 /* Power down PHY and disable DLL before making changes */ 162 mask = PHYCTRL_ENDLL | PHYCTRL_PDB; 163 val = 0; 164 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val); 165 166 if (enable == false) 167 return (0); 168 169 sc->phy_conf = (struct rk_emmcphy_conf *)ofw_bus_search_compatible(dev, 170 compat_data)->ocd_data; 171 172 /* Get clock */ 173 error = clk_get_by_ofw_name(dev, 0, "emmcclk", &sc->clk); 174 if (error != 0) { 175 device_printf(dev, "cannot get emmcclk clock, continue\n"); 176 sc->clk = NULL; 177 } else 178 device_printf(dev, "got emmcclk clock\n"); 179 180 if (sc->clk) { 181 error = clk_get_freq(sc->clk, &rate); 182 if (error != 0) { 183 device_printf(dev, "cannot get clock frequency\n"); 184 return (ENXIO); 185 } 186 } else 187 rate = 0; 188 189 if (rate != 0) { 190 if (rate < 75000000) 191 frqsel = PHYCTRL_FRQSEL_50M; 192 else if (rate < 125000000) 193 frqsel = PHYCTRL_FRQSEL_100M; 194 else if (rate < 175000000) 195 frqsel = PHYCTRL_FRQSEL_150M; 196 else 197 frqsel = PHYCTRL_FRQSEL_200M; 198 } else 199 frqsel = PHYCTRL_FRQSEL_200M; 200 201 DELAY(3); 202 203 /* Power up PHY */ 204 mask = PHYCTRL_PDB; 205 val = PHYCTRL_PDB; 206 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val); 207 208 /* Wait for calibration */ 209 DELAY(10); 210 val = SYSCON_READ_4(sc->syscon, GRF_EMMCPHY_STATUS); 211 if ((val & PHYCTRL_CALDONE) == 0) { 212 device_printf(dev, "PHY calibration did not complete\n"); 213 return (ENXIO); 214 } 215 216 /* Set DLL frequency */ 217 mask = PHYCTRL_FRQSEL; 218 val = SHIFTIN(frqsel, PHYCTRL_FRQSEL); 219 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0, (mask << 16) | val); 220 221 /* Enable DLL */ 222 mask = PHYCTRL_ENDLL; 223 val = PHYCTRL_ENDLL; 224 SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val); 225 226 if (rate != 0) { 227 /* 228 * Rockchip RK3399 TRM V1.3 Part2.pdf says in page 698: 229 * After the DLL control loop reaches steady state a DLL 230 * ready signal is generated by the DLL circuits 231 * 'phyctrl_dllrdy'. 232 * The time from 'phyctrl_endll' to DLL ready signal 233 * 'phyctrl_dllrdy' varies with the clock frequency. 234 * At 200MHz clock frequency the DLL ready delay is 2.56us, 235 * at 100MHz clock frequency the DLL ready delay is 5.112us and 236 * at 50 MHz clock frequency the DLL ready delay is 10.231us. 237 * We could use safe values for wait, 12us, 8us, 6us and 4us 238 * respectively. 239 * However due to some unknown reason it is not working and 240 * DLL seems to take extra long time to lock. 241 * So we will use more safe value 50ms here. 242 */ 243 244 /* Wait for DLL ready */ 245 DELAY(50000); 246 val = SYSCON_READ_4(sc->syscon, GRF_EMMCPHY_STATUS); 247 if ((val & PHYCTRL_DLLRDY) == 0) { 248 device_printf(dev, "DLL loop failed to lock\n"); 249 return (ENXIO); 250 } 251 } 252 253 return (0); 254 } 255 256 static int 257 rk_emmcphy_probe(device_t dev) 258 { 259 260 if (!ofw_bus_status_okay(dev)) 261 return (ENXIO); 262 263 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 264 return (ENXIO); 265 266 device_set_desc(dev, "Rockchip RK3399 eMMC PHY"); 267 return (BUS_PROBE_DEFAULT); 268 } 269 270 static int 271 rk_emmcphy_attach(device_t dev) 272 { 273 struct phynode_init_def phy_init; 274 struct phynode *phynode; 275 struct rk_emmcphy_softc *sc; 276 phandle_t node; 277 phandle_t xnode; 278 pcell_t handle; 279 intptr_t phy; 280 281 sc = device_get_softc(dev); 282 node = ofw_bus_get_node(dev); 283 284 if (OF_getencprop(node, "clocks", (void *)&handle, 285 sizeof(handle)) <= 0) { 286 device_printf(dev, "cannot get clocks handle\n"); 287 return (ENXIO); 288 } 289 xnode = OF_node_from_xref(handle); 290 if (OF_hasprop(xnode, "arasan,soc-ctl-syscon") && 291 syscon_get_by_ofw_property(dev, xnode, 292 "arasan,soc-ctl-syscon", &sc->syscon) != 0) { 293 device_printf(dev, "cannot get grf driver handle\n"); 294 return (ENXIO); 295 } 296 297 if (sc->syscon == NULL) { 298 device_printf(dev, "failed to get syscon\n"); 299 return (ENXIO); 300 } 301 302 /* Create and register phy */ 303 bzero(&phy_init, sizeof(phy_init)); 304 phy_init.id = 0; 305 phy_init.ofw_node = ofw_bus_get_node(dev); 306 phynode = phynode_create(dev, &rk_emmcphy_phynode_class, &phy_init); 307 if (phynode == NULL) { 308 device_printf(dev, "failed to create eMMC PHY\n"); 309 return (ENXIO); 310 } 311 if (phynode_register(phynode) == NULL) { 312 device_printf(dev, "failed to register eMMC PHY\n"); 313 return (ENXIO); 314 } 315 if (bootverbose) { 316 phy = phynode_get_id(phynode); 317 device_printf(dev, "Attached phy id: %ld\n", phy); 318 } 319 return (0); 320 } 321 322 static device_method_t rk_emmcphy_methods[] = { 323 /* Device interface */ 324 DEVMETHOD(device_probe, rk_emmcphy_probe), 325 DEVMETHOD(device_attach, rk_emmcphy_attach), 326 327 DEVMETHOD_END 328 }; 329 330 static driver_t rk_emmcphy_driver = { 331 "rk_emmcphy", 332 rk_emmcphy_methods, 333 sizeof(struct rk_emmcphy_softc) 334 }; 335 336 EARLY_DRIVER_MODULE(rk_emmcphy, simplebus, rk_emmcphy_driver, 0, 0, 337 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 338 MODULE_VERSION(rk_emmcphy, 1); 339