1 /*- 2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kthread.h> 37 #include <sys/rman.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <machine/bus.h> 41 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #define GCC_QDSS_BCR 0x29000 46 #define GCC_QDSS_BCR_BLK_ARES (1 << 0) /* Async software reset. */ 47 #define GCC_QDSS_CFG_AHB_CBCR 0x29008 48 #define AHB_CBCR_CLK_ENABLE (1 << 0) /* AHB clk branch ctrl */ 49 #define GCC_QDSS_ETR_USB_CBCR 0x29028 50 #define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */ 51 #define GCC_QDSS_DAP_CBCR 0x29084 52 #define DAP_CBCR_CLK_ENABLE (1 << 0) /* DAP clk branch ctrl */ 53 54 static struct ofw_compat_data compat_data[] = { 55 { "qcom,gcc-msm8916", 1 }, 56 { NULL, 0 } 57 }; 58 59 struct qcom_gcc_softc { 60 struct resource *res; 61 }; 62 63 static struct resource_spec qcom_gcc_spec[] = { 64 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 65 { -1, 0 } 66 }; 67 68 /* 69 * Qualcomm Debug Subsystem (QDSS) 70 * block enabling routine. 71 */ 72 static void 73 qcom_qdss_enable(struct qcom_gcc_softc *sc) 74 { 75 76 /* Put QDSS block to reset */ 77 bus_write_4(sc->res, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES); 78 79 /* Enable AHB clock branch */ 80 bus_write_4(sc->res, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE); 81 82 /* Enable DAP clock branch */ 83 bus_write_4(sc->res, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE); 84 85 /* Enable ETR USB clock branch */ 86 bus_write_4(sc->res, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE); 87 88 /* Out of reset */ 89 bus_write_4(sc->res, GCC_QDSS_BCR, 0); 90 } 91 92 static int 93 qcom_gcc_probe(device_t dev) 94 { 95 if (!ofw_bus_status_okay(dev)) 96 return (ENXIO); 97 98 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 99 return (ENXIO); 100 101 device_set_desc(dev, "Qualcomm Global Clock Controller"); 102 103 return (BUS_PROBE_DEFAULT); 104 } 105 106 static int 107 qcom_gcc_attach(device_t dev) 108 { 109 struct qcom_gcc_softc *sc; 110 111 sc = device_get_softc(dev); 112 113 if (bus_alloc_resources(dev, qcom_gcc_spec, &sc->res) != 0) { 114 device_printf(dev, "cannot allocate resources for device\n"); 115 return (ENXIO); 116 } 117 118 /* 119 * Enable debug unit. 120 * This is required for Coresight operation. 121 * This also enables USB clock branch. 122 */ 123 qcom_qdss_enable(sc); 124 125 return (0); 126 } 127 128 static device_method_t qcom_gcc_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, qcom_gcc_probe), 131 DEVMETHOD(device_attach, qcom_gcc_attach), 132 133 DEVMETHOD_END 134 }; 135 136 static driver_t qcom_gcc_driver = { 137 "qcom_gcc", 138 qcom_gcc_methods, 139 sizeof(struct qcom_gcc_softc), 140 }; 141 142 EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 0, 0, 143 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 144 MODULE_VERSION(qcom_gcc, 1); 145