1 /*- 2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _TI_SPIVAR_H_ 30 #define _TI_SPIVAR_H_ 31 32 struct ti_spi_softc { 33 bus_space_tag_t sc_bst; 34 bus_space_handle_t sc_bsh; 35 device_t sc_dev; 36 int sc_numcs; 37 struct mtx sc_mtx; 38 struct resource *sc_mem_res; 39 struct resource *sc_irq_res; 40 struct { 41 int cs; 42 int fifolvl; 43 struct spi_command *cmd; 44 uint32_t len; 45 uint32_t read; 46 uint32_t written; 47 } xfer; 48 uint32_t sc_flags; 49 void *sc_intrhand; 50 #define sc_cs xfer.cs 51 #define sc_fifolvl xfer.fifolvl 52 #define sc_cmd xfer.cmd 53 #define sc_len xfer.len 54 #define sc_read xfer.read 55 #define sc_written xfer.written 56 }; 57 58 #define TI_SPI_BUSY 0x1 59 #define TI_SPI_DONE 0x2 60 61 #define TI_SPI_WRITE(_sc, _off, _val) \ 62 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val)) 63 #define TI_SPI_READ(_sc, _off) \ 64 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off)) 65 66 #define TI_SPI_LOCK(_sc) \ 67 mtx_lock(&(_sc)->sc_mtx) 68 #define TI_SPI_UNLOCK(_sc) \ 69 mtx_unlock(&(_sc)->sc_mtx) 70 71 #endif /* _TI_SPIVAR_H_ */ 72