1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2010 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ben Gray. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 38 /* 39 * Texas Instruments - OMAP3xxx series processors 40 * 41 * Reference: 42 * OMAP35x Applications Processor 43 * Technical Reference Manual 44 * (omap35xx_techref.pdf) 45 */ 46 #ifndef _TI_PRCM_H_ 47 #define _TI_PRCM_H_ 48 49 typedef enum { 50 51 INVALID_CLK_IDENT = 0, 52 53 /* System clocks, typically you can only call ti_prcm_clk_get_source_freq() 54 * on these clocks as they are enabled by default. 55 */ 56 SYS_CLK = 1, 57 58 /* The MPU (ARM) core clock */ 59 MPU_CLK = 20, 60 61 /* MMC modules */ 62 MMC1_CLK = 100, 63 MMC2_CLK, 64 MMC3_CLK, 65 MMC4_CLK, 66 MMC5_CLK, 67 MMC6_CLK, 68 69 /* I2C modules */ 70 I2C1_CLK = 200, 71 I2C2_CLK, 72 I2C3_CLK, 73 I2C4_CLK, 74 I2C5_CLK, 75 76 /* USB module(s) */ 77 USBTLL_CLK = 300, 78 USBHSHOST_CLK, 79 USBFSHOST_CLK, 80 USBP1_PHY_CLK, 81 USBP2_PHY_CLK, 82 USBP1_UTMI_CLK, 83 USBP2_UTMI_CLK, 84 USBP1_HSIC_CLK, 85 USBP2_HSIC_CLK, 86 87 /* UART modules */ 88 UART1_CLK = 400, 89 UART2_CLK, 90 UART3_CLK, 91 UART4_CLK, 92 UART5_CLK, 93 UART6_CLK, 94 UART7_CLK, 95 UART8_CLK, 96 UART9_CLK, 97 98 /* General purpose timer modules */ 99 TIMER1_CLK = 500, 100 TIMER2_CLK, 101 TIMER3_CLK, 102 TIMER4_CLK, 103 TIMER5_CLK, 104 TIMER6_CLK, 105 TIMER7_CLK, 106 TIMER8_CLK, 107 TIMER9_CLK, 108 TIMER10_CLK, 109 TIMER11_CLK, 110 TIMER12_CLK, 111 112 /* McBSP module(s) */ 113 MCBSP1_CLK = 600, 114 MCBSP2_CLK, 115 MCBSP3_CLK, 116 MCBSP4_CLK, 117 MCBSP5_CLK, 118 119 /* General purpose I/O modules */ 120 GPIO1_CLK = 700, 121 GPIO2_CLK, 122 GPIO3_CLK, 123 GPIO4_CLK, 124 GPIO5_CLK, 125 GPIO6_CLK, 126 GPIO7_CLK, 127 128 /* sDMA module */ 129 SDMA_CLK = 800, 130 131 /* CPSW modules */ 132 CPSW_CLK = 1000, 133 134 /* Mentor USB modules */ 135 MUSB0_CLK = 1100, 136 137 /* EDMA module */ 138 EDMA_TPCC_CLK = 1200, 139 EDMA_TPTC0_CLK, 140 EDMA_TPTC1_CLK, 141 EDMA_TPTC2_CLK, 142 143 /* LCD controller module */ 144 LCDC_CLK = 1300, 145 146 /* PWM modules */ 147 PWMSS0_CLK = 1400, 148 PWMSS1_CLK, 149 PWMSS2_CLK, 150 151 /* Mailbox modules */ 152 MAILBOX0_CLK = 1500, 153 154 /* Spinlock modules */ 155 SPINLOCK0_CLK = 1600, 156 157 PRUSS_CLK = 1700, 158 159 TSC_ADC_CLK = 1800, 160 161 /* RTC module */ 162 RTC_CLK = 1900, 163 164 /* McSPI */ 165 SPI0_CLK = 2000, 166 SPI1_CLK, 167 } clk_ident_t; 168 169 /* 170 * 171 */ 172 typedef enum { 173 SYSCLK_CLK, /* System clock */ 174 EXT_CLK, 175 176 F32KHZ_CLK, /* 32KHz clock */ 177 F48MHZ_CLK, /* 48MHz clock */ 178 F64MHZ_CLK, /* 64MHz clock */ 179 F96MHZ_CLK, /* 96MHz clock */ 180 181 } clk_src_t; 182 183 struct ti_clock_dev { 184 /* The profile of the timer */ 185 clk_ident_t id; 186 187 /* A bunch of callbacks associated with the clock device */ 188 int (*clk_activate)(struct ti_clock_dev *clkdev); 189 int (*clk_deactivate)(struct ti_clock_dev *clkdev); 190 int (*clk_set_source)(struct ti_clock_dev *clkdev, 191 clk_src_t clksrc); 192 int (*clk_accessible)(struct ti_clock_dev *clkdev); 193 int (*clk_set_source_freq)(struct ti_clock_dev *clkdev, 194 unsigned int freq); 195 int (*clk_get_source_freq)(struct ti_clock_dev *clkdev, 196 unsigned int *freq); 197 }; 198 199 int ti_prcm_clk_valid(clk_ident_t clk); 200 int ti_prcm_clk_enable(clk_ident_t clk); 201 int ti_prcm_clk_disable(clk_ident_t clk); 202 int ti_prcm_clk_accessible(clk_ident_t clk); 203 int ti_prcm_clk_disable_autoidle(clk_ident_t clk); 204 int ti_prcm_clk_set_source(clk_ident_t clk, clk_src_t clksrc); 205 int ti_prcm_clk_set_source_freq(clk_ident_t clk, unsigned int freq); 206 int ti_prcm_clk_get_source_freq(clk_ident_t clk, unsigned int *freq); 207 void ti_prcm_reset(void); 208 209 #endif /* _TI_PRCM_H_ */ 210