1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/interrupt.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <arm/ti/ti_cpuid.h> 56 #include <arm/ti/ti_gpio.h> 57 #include <arm/ti/ti_scm.h> 58 #include <arm/ti/ti_prcm.h> 59 #include <arm/ti/ti_hwmods.h> 60 61 #include <dev/fdt/fdt_common.h> 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include "gpio_if.h" 68 #include "ti_gpio_if.h" 69 #ifdef INTRNG 70 #include "pic_if.h" 71 #endif 72 73 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 74 #error "Unknown SoC" 75 #endif 76 77 /* Register definitions */ 78 #define TI_GPIO_REVISION 0x0000 79 #define TI_GPIO_SYSCONFIG 0x0010 80 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 81 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 82 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 87 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 88 #define TI_GPIO_IRQWAKEN_0 0x0044 89 #define TI_GPIO_IRQWAKEN_1 0x0048 90 #define TI_GPIO_SYSSTATUS 0x0114 91 #define TI_GPIO_IRQSTATUS1 0x0118 92 #define TI_GPIO_IRQENABLE1 0x011C 93 #define TI_GPIO_WAKEUPENABLE 0x0120 94 #define TI_GPIO_IRQSTATUS2 0x0128 95 #define TI_GPIO_IRQENABLE2 0x012C 96 #define TI_GPIO_CTRL 0x0130 97 #define TI_GPIO_OE 0x0134 98 #define TI_GPIO_DATAIN 0x0138 99 #define TI_GPIO_DATAOUT 0x013C 100 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 101 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 102 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 103 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 104 #define TI_GPIO_DEBOUNCENABLE 0x0150 105 #define TI_GPIO_DEBOUNCINGTIME 0x0154 106 #define TI_GPIO_CLEARWKUPENA 0x0180 107 #define TI_GPIO_SETWKUENA 0x0184 108 #define TI_GPIO_CLEARDATAOUT 0x0190 109 #define TI_GPIO_SETDATAOUT 0x0194 110 111 /* Other SoC Specific definitions */ 112 #define OMAP4_FIRST_GPIO_BANK 1 113 #define OMAP4_INTR_PER_BANK 1 114 #define OMAP4_GPIO_REV 0x50600801 115 #define AM335X_FIRST_GPIO_BANK 0 116 #define AM335X_INTR_PER_BANK 2 117 #define AM335X_GPIO_REV 0x50600801 118 #define PINS_PER_BANK 32 119 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 120 121 static int ti_gpio_intr(void *arg); 122 static int ti_gpio_detach(device_t); 123 124 #ifdef INTRNG 125 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 126 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 127 #endif 128 129 static u_int 130 ti_first_gpio_bank(void) 131 { 132 switch(ti_chip()) { 133 #ifdef SOC_OMAP4 134 case CHIP_OMAP_4: 135 return (OMAP4_FIRST_GPIO_BANK); 136 #endif 137 #ifdef SOC_TI_AM335X 138 case CHIP_AM335X: 139 return (AM335X_FIRST_GPIO_BANK); 140 #endif 141 } 142 return (0); 143 } 144 145 static uint32_t 146 ti_gpio_rev(void) 147 { 148 switch(ti_chip()) { 149 #ifdef SOC_OMAP4 150 case CHIP_OMAP_4: 151 return (OMAP4_GPIO_REV); 152 #endif 153 #ifdef SOC_TI_AM335X 154 case CHIP_AM335X: 155 return (AM335X_GPIO_REV); 156 #endif 157 } 158 return (0); 159 } 160 161 /** 162 * Macros for driver mutex locking 163 */ 164 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 165 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 166 #define TI_GPIO_LOCK_INIT(_sc) \ 167 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 168 "ti_gpio", MTX_SPIN) 169 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 170 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 171 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 172 173 /** 174 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 175 * @sc: GPIO device context 176 * @bank: The bank to read from 177 * @off: The offset of a register from the GPIO register address range 178 * 179 * 180 * RETURNS: 181 * 32-bit value read from the register. 182 */ 183 static inline uint32_t 184 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 185 { 186 return (bus_read_4(sc->sc_mem_res, off)); 187 } 188 189 /** 190 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 191 * @sc: GPIO device context 192 * @bank: The bank to write to 193 * @off: The offset of a register from the GPIO register address range 194 * @val: The value to write into the register 195 * 196 * RETURNS: 197 * nothing 198 */ 199 static inline void 200 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 201 uint32_t val) 202 { 203 bus_write_4(sc->sc_mem_res, off, val); 204 } 205 206 static inline void 207 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 208 { 209 210 /* We clear both set of registers. */ 211 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 212 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 213 } 214 215 static inline void 216 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 217 { 218 219 /* 220 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 221 * also activate only the first interrupt. 222 */ 223 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 224 } 225 226 static inline void 227 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 228 { 229 230 /* 231 * Acknowledge the interrupt on both registers even if we use only 232 * the first one. 233 */ 234 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 235 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 236 } 237 238 static inline uint32_t 239 ti_gpio_intr_status(struct ti_gpio_softc *sc) 240 { 241 uint32_t reg; 242 243 /* Get the status from both registers. */ 244 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 245 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 246 247 return (reg); 248 } 249 250 static device_t 251 ti_gpio_get_bus(device_t dev) 252 { 253 struct ti_gpio_softc *sc; 254 255 sc = device_get_softc(dev); 256 257 return (sc->sc_busdev); 258 } 259 260 /** 261 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 262 * @dev: gpio device handle 263 * @maxpin: pointer to a value that upon return will contain the maximum number 264 * of pins in the device. 265 * 266 * 267 * LOCKING: 268 * No locking required, returns static data. 269 * 270 * RETURNS: 271 * Returns 0 on success otherwise an error code 272 */ 273 static int 274 ti_gpio_pin_max(device_t dev, int *maxpin) 275 { 276 277 *maxpin = PINS_PER_BANK - 1; 278 279 return (0); 280 } 281 282 static int 283 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 284 { 285 286 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 287 return (EINVAL); 288 289 return (0); 290 } 291 292 /** 293 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 294 * @dev: gpio device handle 295 * @pin: the number of the pin 296 * @caps: pointer to a value that upon return will contain the capabilities 297 * 298 * Currently all pins have the same capability, notably: 299 * - GPIO_PIN_INPUT 300 * - GPIO_PIN_OUTPUT 301 * - GPIO_PIN_PULLUP 302 * - GPIO_PIN_PULLDOWN 303 * - GPIO_INTR_LEVEL_LOW 304 * - GPIO_INTR_LEVEL_HIGH 305 * - GPIO_INTR_EDGE_RISING 306 * - GPIO_INTR_EDGE_FALLING 307 * - GPIO_INTR_EDGE_BOTH 308 * 309 * LOCKING: 310 * No locking required, returns static data. 311 * 312 * RETURNS: 313 * Returns 0 on success otherwise an error code 314 */ 315 static int 316 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 317 { 318 struct ti_gpio_softc *sc; 319 320 sc = device_get_softc(dev); 321 if (ti_gpio_valid_pin(sc, pin) != 0) 322 return (EINVAL); 323 324 #ifdef INTRNG 325 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 326 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 327 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 328 GPIO_INTR_EDGE_BOTH); 329 #else 330 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 331 GPIO_PIN_PULLDOWN); 332 #endif 333 334 return (0); 335 } 336 337 /** 338 * ti_gpio_pin_getflags - Gets the current flags of a given pin 339 * @dev: gpio device handle 340 * @pin: the number of the pin 341 * @flags: upon return will contain the current flags of the pin 342 * 343 * Reads the current flags of a given pin, here we actually read the H/W 344 * registers to determine the flags, rather than storing the value in the 345 * setflags call. 346 * 347 * LOCKING: 348 * Internally locks the context 349 * 350 * RETURNS: 351 * Returns 0 on success otherwise an error code 352 */ 353 static int 354 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 355 { 356 struct ti_gpio_softc *sc; 357 358 sc = device_get_softc(dev); 359 if (ti_gpio_valid_pin(sc, pin) != 0) 360 return (EINVAL); 361 362 /* Get the current pin state */ 363 TI_GPIO_LOCK(sc); 364 TI_GPIO_GET_FLAGS(dev, pin, flags); 365 TI_GPIO_UNLOCK(sc); 366 367 return (0); 368 } 369 370 /** 371 * ti_gpio_pin_getname - Gets the name of a given pin 372 * @dev: gpio device handle 373 * @pin: the number of the pin 374 * @name: buffer to put the name in 375 * 376 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 377 * of the pin. 378 * 379 * LOCKING: 380 * No locking required, returns static data. 381 * 382 * RETURNS: 383 * Returns 0 on success otherwise an error code 384 */ 385 static int 386 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 387 { 388 struct ti_gpio_softc *sc; 389 390 sc = device_get_softc(dev); 391 if (ti_gpio_valid_pin(sc, pin) != 0) 392 return (EINVAL); 393 394 /* Set a very simple name */ 395 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 396 name[GPIOMAXNAME - 1] = '\0'; 397 398 return (0); 399 } 400 401 /** 402 * ti_gpio_pin_setflags - Sets the flags for a given pin 403 * @dev: gpio device handle 404 * @pin: the number of the pin 405 * @flags: the flags to set 406 * 407 * The flags of the pin correspond to things like input/output mode, pull-ups, 408 * pull-downs, etc. This driver doesn't support all flags, only the following: 409 * - GPIO_PIN_INPUT 410 * - GPIO_PIN_OUTPUT 411 * - GPIO_PIN_PULLUP 412 * - GPIO_PIN_PULLDOWN 413 * 414 * LOCKING: 415 * Internally locks the context 416 * 417 * RETURNS: 418 * Returns 0 on success otherwise an error code 419 */ 420 static int 421 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 422 { 423 struct ti_gpio_softc *sc; 424 uint32_t oe; 425 426 sc = device_get_softc(dev); 427 if (ti_gpio_valid_pin(sc, pin) != 0) 428 return (EINVAL); 429 430 /* Set the GPIO mode and state */ 431 TI_GPIO_LOCK(sc); 432 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 433 TI_GPIO_UNLOCK(sc); 434 return (EINVAL); 435 } 436 437 /* If configuring as an output set the "output enable" bit */ 438 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 439 if (flags & GPIO_PIN_INPUT) 440 oe |= TI_GPIO_MASK(pin); 441 else 442 oe &= ~TI_GPIO_MASK(pin); 443 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 444 TI_GPIO_UNLOCK(sc); 445 446 return (0); 447 } 448 449 /** 450 * ti_gpio_pin_set - Sets the current level on a GPIO pin 451 * @dev: gpio device handle 452 * @pin: the number of the pin 453 * @value: non-zero value will drive the pin high, otherwise the pin is 454 * driven low. 455 * 456 * 457 * LOCKING: 458 * Internally locks the context 459 * 460 * RETURNS: 461 * Returns 0 on success otherwise a error code 462 */ 463 static int 464 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 465 { 466 struct ti_gpio_softc *sc; 467 uint32_t reg; 468 469 sc = device_get_softc(dev); 470 if (ti_gpio_valid_pin(sc, pin) != 0) 471 return (EINVAL); 472 473 TI_GPIO_LOCK(sc); 474 if (value == GPIO_PIN_LOW) 475 reg = TI_GPIO_CLEARDATAOUT; 476 else 477 reg = TI_GPIO_SETDATAOUT; 478 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 479 TI_GPIO_UNLOCK(sc); 480 481 return (0); 482 } 483 484 /** 485 * ti_gpio_pin_get - Gets the current level on a GPIO pin 486 * @dev: gpio device handle 487 * @pin: the number of the pin 488 * @value: pointer to a value that upond return will contain the pin value 489 * 490 * The pin must be configured as an input pin beforehand, otherwise this 491 * function will fail. 492 * 493 * LOCKING: 494 * Internally locks the context 495 * 496 * RETURNS: 497 * Returns 0 on success otherwise a error code 498 */ 499 static int 500 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 501 { 502 struct ti_gpio_softc *sc; 503 uint32_t oe, reg, val; 504 505 sc = device_get_softc(dev); 506 if (ti_gpio_valid_pin(sc, pin) != 0) 507 return (EINVAL); 508 509 /* 510 * Return data from output latch when set as output and from the 511 * input register otherwise. 512 */ 513 TI_GPIO_LOCK(sc); 514 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 515 if (oe & TI_GPIO_MASK(pin)) 516 reg = TI_GPIO_DATAIN; 517 else 518 reg = TI_GPIO_DATAOUT; 519 val = ti_gpio_read_4(sc, reg); 520 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 521 TI_GPIO_UNLOCK(sc); 522 523 return (0); 524 } 525 526 /** 527 * ti_gpio_pin_toggle - Toggles a given GPIO pin 528 * @dev: gpio device handle 529 * @pin: the number of the pin 530 * 531 * 532 * LOCKING: 533 * Internally locks the context 534 * 535 * RETURNS: 536 * Returns 0 on success otherwise a error code 537 */ 538 static int 539 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 540 { 541 struct ti_gpio_softc *sc; 542 uint32_t reg, val; 543 544 sc = device_get_softc(dev); 545 if (ti_gpio_valid_pin(sc, pin) != 0) 546 return (EINVAL); 547 548 /* Toggle the pin */ 549 TI_GPIO_LOCK(sc); 550 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 551 if (val & TI_GPIO_MASK(pin)) 552 reg = TI_GPIO_CLEARDATAOUT; 553 else 554 reg = TI_GPIO_SETDATAOUT; 555 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 556 TI_GPIO_UNLOCK(sc); 557 558 return (0); 559 } 560 561 #ifndef INTRNG 562 /** 563 * ti_gpio_intr - ISR for all GPIO modules 564 * @arg: the soft context pointer 565 * 566 * LOCKING: 567 * Internally locks the context 568 * 569 */ 570 static int 571 ti_gpio_intr(void *arg) 572 { 573 int bank_last, irq; 574 struct intr_event *event; 575 struct ti_gpio_softc *sc; 576 uint32_t reg; 577 578 sc = (struct ti_gpio_softc *)arg; 579 bank_last = -1; 580 reg = 0; /* squelch bogus gcc warning */ 581 reg = ti_gpio_intr_status(sc); 582 for (irq = 0; irq < sc->sc_maxpin; irq++) { 583 if ((reg & TI_GPIO_MASK(irq)) == 0) 584 continue; 585 event = sc->sc_events[irq]; 586 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 587 intr_event_handle(event, NULL); 588 else 589 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 590 /* Ack the IRQ Status bit. */ 591 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq)); 592 } 593 594 return (FILTER_HANDLED); 595 } 596 #endif 597 598 static int 599 ti_gpio_bank_init(device_t dev) 600 { 601 int pin; 602 struct ti_gpio_softc *sc; 603 uint32_t flags, reg_oe, reg_set, rev; 604 clk_ident_t clk; 605 606 sc = device_get_softc(dev); 607 608 /* Enable the interface and functional clocks for the module. */ 609 clk = ti_hwmods_get_clock(dev); 610 if (clk == INVALID_CLK_IDENT) { 611 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 612 return (EINVAL); 613 } 614 615 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 616 ti_prcm_clk_enable(clk); 617 618 /* 619 * Read the revision number of the module. TI don't publish the 620 * actual revision numbers, so instead the values have been 621 * determined by experimentation. 622 */ 623 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 624 625 /* Check the revision. */ 626 if (rev != ti_gpio_rev()) { 627 device_printf(dev, "Warning: could not determine the revision " 628 "of GPIO module (revision:0x%08x)\n", rev); 629 return (EINVAL); 630 } 631 632 /* Disable interrupts for all pins. */ 633 ti_gpio_intr_clr(sc, 0xffffffff); 634 635 /* Init OE register based on pads configuration. */ 636 reg_oe = 0xffffffff; 637 reg_set = 0; 638 for (pin = 0; pin < PINS_PER_BANK; pin++) { 639 TI_GPIO_GET_FLAGS(dev, pin, &flags); 640 if (flags & GPIO_PIN_OUTPUT) { 641 reg_oe &= ~(1UL << pin); 642 if (flags & GPIO_PIN_PULLUP) 643 reg_set |= (1UL << pin); 644 } 645 } 646 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 647 if (reg_set) 648 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 649 650 return (0); 651 } 652 653 /** 654 * ti_gpio_attach - attach function for the driver 655 * @dev: gpio device handle 656 * 657 * Allocates and sets up the driver context for all GPIO banks. This function 658 * expects the memory ranges and IRQs to already be allocated to the driver. 659 * 660 * LOCKING: 661 * None 662 * 663 * RETURNS: 664 * Always returns 0 665 */ 666 static int 667 ti_gpio_attach(device_t dev) 668 { 669 struct ti_gpio_softc *sc; 670 #ifndef INTRNG 671 unsigned int i; 672 #endif 673 int err; 674 675 sc = device_get_softc(dev); 676 sc->sc_dev = dev; 677 TI_GPIO_LOCK_INIT(sc); 678 ti_gpio_pin_max(dev, &sc->sc_maxpin); 679 sc->sc_maxpin++; 680 681 sc->sc_mem_rid = 0; 682 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 683 &sc->sc_mem_rid, RF_ACTIVE); 684 if (!sc->sc_mem_res) { 685 device_printf(dev, "Error: could not allocate mem resources\n"); 686 ti_gpio_detach(dev); 687 return (ENXIO); 688 } 689 690 sc->sc_irq_rid = 0; 691 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 692 &sc->sc_irq_rid, RF_ACTIVE); 693 if (!sc->sc_irq_res) { 694 device_printf(dev, "Error: could not allocate irq resources\n"); 695 ti_gpio_detach(dev); 696 return (ENXIO); 697 } 698 699 /* 700 * Register our interrupt filter for each of the IRQ resources. 701 */ 702 if (bus_setup_intr(dev, sc->sc_irq_res, 703 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 704 &sc->sc_irq_hdl) != 0) { 705 device_printf(dev, 706 "WARNING: unable to register interrupt filter\n"); 707 ti_gpio_detach(dev); 708 return (ENXIO); 709 } 710 711 #ifdef INTRNG 712 if (ti_gpio_pic_attach(sc) != 0) { 713 device_printf(dev, "WARNING: unable to attach PIC\n"); 714 ti_gpio_detach(dev); 715 return (ENXIO); 716 } 717 #else 718 /* 719 * Initialize the interrupt settings. The default is active-low 720 * interrupts. 721 */ 722 sc->sc_irq_trigger = malloc( 723 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 724 M_DEVBUF, M_WAITOK | M_ZERO); 725 sc->sc_irq_polarity = malloc( 726 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 727 M_DEVBUF, M_WAITOK | M_ZERO); 728 for (i = 0; i < sc->sc_maxpin; i++) { 729 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 730 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 731 } 732 733 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 734 M_DEVBUF, M_WAITOK | M_ZERO); 735 736 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin, 737 M_DEVBUF, M_WAITOK | M_ZERO); 738 #endif 739 /* We need to go through each block and ensure the clocks are running and 740 * the module is enabled. It might be better to do this only when the 741 * pins are configured which would result in less power used if the GPIO 742 * pins weren't used ... 743 */ 744 if (sc->sc_mem_res != NULL) { 745 /* Initialize the GPIO module. */ 746 err = ti_gpio_bank_init(dev); 747 if (err != 0) { 748 ti_gpio_detach(dev); 749 return (err); 750 } 751 } 752 753 sc->sc_busdev = gpiobus_attach_bus(dev); 754 if (sc->sc_busdev == NULL) { 755 ti_gpio_detach(dev); 756 return (ENXIO); 757 } 758 759 return (0); 760 } 761 762 /** 763 * ti_gpio_detach - detach function for the driver 764 * @dev: scm device handle 765 * 766 * Allocates and sets up the driver context, this simply entails creating a 767 * bus mappings for the SCM register set. 768 * 769 * LOCKING: 770 * None 771 * 772 * RETURNS: 773 * Always returns 0 774 */ 775 static int 776 ti_gpio_detach(device_t dev) 777 { 778 struct ti_gpio_softc *sc = device_get_softc(dev); 779 780 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 781 782 /* Disable all interrupts */ 783 if (sc->sc_mem_res != NULL) 784 ti_gpio_intr_clr(sc, 0xffffffff); 785 gpiobus_detach_bus(dev); 786 #ifdef INTRNG 787 if (sc->sc_isrcs != NULL) 788 ti_gpio_pic_detach(sc); 789 #else 790 if (sc->sc_events) 791 free(sc->sc_events, M_DEVBUF); 792 if (sc->sc_mask_args) 793 free(sc->sc_mask_args, M_DEVBUF); 794 if (sc->sc_irq_polarity) 795 free(sc->sc_irq_polarity, M_DEVBUF); 796 if (sc->sc_irq_trigger) 797 free(sc->sc_irq_trigger, M_DEVBUF); 798 #endif 799 /* Release the memory and IRQ resources. */ 800 if (sc->sc_irq_hdl) { 801 bus_teardown_intr(dev, sc->sc_irq_res, 802 sc->sc_irq_hdl); 803 } 804 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 805 sc->sc_irq_res); 806 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 807 sc->sc_mem_res); 808 TI_GPIO_LOCK_DESTROY(sc); 809 810 return (0); 811 } 812 813 #ifdef INTRNG 814 static inline void 815 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 816 bool set_bits) 817 { 818 uint32_t value; 819 820 value = ti_gpio_read_4(sc, reg); 821 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 822 } 823 824 static inline void 825 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 826 { 827 828 /* Writing a 0 has no effect. */ 829 ti_gpio_intr_clr(sc, tgi->tgi_mask); 830 } 831 832 static inline void 833 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 834 { 835 836 /* Writing a 0 has no effect. */ 837 ti_gpio_intr_set(sc, tgi->tgi_mask); 838 } 839 840 static inline void 841 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 842 { 843 844 /* Writing a 0 has no effect. */ 845 ti_gpio_intr_ack(sc, tgi->tgi_mask); 846 } 847 848 static inline bool 849 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 850 { 851 852 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 853 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 854 } 855 856 static int 857 ti_gpio_intr(void *arg) 858 { 859 u_int irq; 860 uint32_t reg; 861 struct ti_gpio_softc *sc; 862 struct trapframe *tf; 863 struct ti_gpio_irqsrc *tgi; 864 865 sc = (struct ti_gpio_softc *)arg; 866 tf = curthread->td_intr_frame; 867 868 reg = ti_gpio_intr_status(sc); 869 for (irq = 0; irq < sc->sc_maxpin; irq++) { 870 tgi = &sc->sc_isrcs[irq]; 871 if ((reg & tgi->tgi_mask) == 0) 872 continue; 873 if (!ti_gpio_isrc_is_level(tgi)) 874 ti_gpio_isrc_eoi(sc, tgi); 875 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 876 ti_gpio_isrc_mask(sc, tgi); 877 if (ti_gpio_isrc_is_level(tgi)) 878 ti_gpio_isrc_eoi(sc, tgi); 879 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 880 irq); 881 } 882 } 883 return (FILTER_HANDLED); 884 } 885 886 static int 887 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 888 { 889 int error; 890 uint32_t irq; 891 const char *name; 892 893 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 894 M_WAITOK | M_ZERO); 895 896 name = device_get_nameunit(sc->sc_dev); 897 for (irq = 0; irq < sc->sc_maxpin; irq++) { 898 sc->sc_isrcs[irq].tgi_irq = irq; 899 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 900 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 901 902 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 903 sc->sc_dev, 0, "%s,%u", name, irq); 904 if (error != 0) 905 return (error); /* XXX deregister ISRCs */ 906 } 907 return (intr_pic_register(sc->sc_dev, 908 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)))); 909 } 910 911 static int 912 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 913 { 914 915 /* 916 * There has not been established any procedure yet 917 * how to detach PIC from living system correctly. 918 */ 919 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 920 return (EBUSY); 921 } 922 923 static void 924 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 925 uint32_t mode) 926 { 927 928 TI_GPIO_LOCK(sc); 929 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 930 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 931 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 932 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 933 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 934 mode == GPIO_INTR_LEVEL_HIGH); 935 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 936 mode == GPIO_INTR_LEVEL_LOW); 937 tgi->tgi_mode = mode; 938 TI_GPIO_UNLOCK(sc); 939 } 940 941 static void 942 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 943 { 944 struct ti_gpio_softc *sc = device_get_softc(dev); 945 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 946 947 ti_gpio_isrc_mask(sc, tgi); 948 } 949 950 static void 951 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 952 { 953 struct ti_gpio_softc *sc = device_get_softc(dev); 954 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 955 956 arm_irq_memory_barrier(tgi->tgi_irq); 957 ti_gpio_isrc_unmask(sc, tgi); 958 } 959 960 static int 961 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 962 u_int *irqp, uint32_t *modep) 963 { 964 uint32_t mode; 965 966 /* 967 * The first cell is the interrupt number. 968 * The second cell is used to specify flags: 969 * bits[3:0] trigger type and level flags: 970 * 1 = low-to-high edge triggered. 971 * 2 = high-to-low edge triggered. 972 * 4 = active high level-sensitive. 973 * 8 = active low level-sensitive. 974 */ 975 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 976 return (EINVAL); 977 978 /* Only reasonable modes are supported. */ 979 if (daf->cells[1] == 1) 980 mode = GPIO_INTR_EDGE_RISING; 981 else if (daf->cells[1] == 2) 982 mode = GPIO_INTR_EDGE_FALLING; 983 else if (daf->cells[1] == 3) 984 mode = GPIO_INTR_EDGE_BOTH; 985 else if (daf->cells[1] == 4) 986 mode = GPIO_INTR_LEVEL_HIGH; 987 else if (daf->cells[1] == 8) 988 mode = GPIO_INTR_LEVEL_LOW; 989 else 990 return (EINVAL); 991 992 *irqp = daf->cells[0]; 993 if (modep != NULL) 994 *modep = mode; 995 return (0); 996 } 997 998 static int 999 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 1000 u_int *irqp, uint32_t *modep) 1001 { 1002 uint32_t mode; 1003 1004 if (dag->gpio_pin_num >= sc->sc_maxpin) 1005 return (EINVAL); 1006 1007 mode = dag->gpio_intr_mode; 1008 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 1009 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 1010 mode != GPIO_INTR_EDGE_BOTH) 1011 return (EINVAL); 1012 1013 *irqp = dag->gpio_pin_num; 1014 if (modep != NULL) 1015 *modep = mode; 1016 return (0); 1017 } 1018 1019 static int 1020 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 1021 u_int *irqp, uint32_t *modep) 1022 { 1023 1024 switch (data->type) { 1025 case INTR_MAP_DATA_FDT: 1026 return (ti_gpio_pic_map_fdt(sc, 1027 (struct intr_map_data_fdt *)data, irqp, modep)); 1028 case INTR_MAP_DATA_GPIO: 1029 return (ti_gpio_pic_map_gpio(sc, 1030 (struct intr_map_data_gpio *)data, irqp, modep)); 1031 default: 1032 return (ENOTSUP); 1033 } 1034 } 1035 1036 static int 1037 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1038 struct intr_irqsrc **isrcp) 1039 { 1040 int error; 1041 u_int irq; 1042 struct ti_gpio_softc *sc = device_get_softc(dev); 1043 1044 error = ti_gpio_pic_map(sc, data, &irq, NULL); 1045 if (error == 0) 1046 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 1047 return (error); 1048 } 1049 1050 static void 1051 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1052 { 1053 struct ti_gpio_softc *sc = device_get_softc(dev); 1054 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1055 1056 if (ti_gpio_isrc_is_level(tgi)) 1057 ti_gpio_isrc_eoi(sc, tgi); 1058 } 1059 1060 static void 1061 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1062 { 1063 1064 ti_gpio_pic_enable_intr(dev, isrc); 1065 } 1066 1067 static void 1068 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1069 { 1070 struct ti_gpio_softc *sc = device_get_softc(dev); 1071 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1072 1073 ti_gpio_isrc_mask(sc, tgi); 1074 if (ti_gpio_isrc_is_level(tgi)) 1075 ti_gpio_isrc_eoi(sc, tgi); 1076 } 1077 1078 static int 1079 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1080 struct resource *res, struct intr_map_data *data) 1081 { 1082 u_int irq; 1083 uint32_t mode; 1084 struct ti_gpio_softc *sc; 1085 struct ti_gpio_irqsrc *tgi; 1086 1087 if (data == NULL) 1088 return (ENOTSUP); 1089 1090 sc = device_get_softc(dev); 1091 tgi = (struct ti_gpio_irqsrc *)isrc; 1092 1093 /* Get and check config for an interrupt. */ 1094 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1095 return (EINVAL); 1096 1097 /* 1098 * If this is a setup for another handler, 1099 * only check that its configuration match. 1100 */ 1101 if (isrc->isrc_handlers != 0) 1102 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1103 1104 ti_gpio_pic_config_intr(sc, tgi, mode); 1105 return (0); 1106 } 1107 1108 static int 1109 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1110 struct resource *res, struct intr_map_data *data) 1111 { 1112 struct ti_gpio_softc *sc = device_get_softc(dev); 1113 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1114 1115 if (isrc->isrc_handlers == 0) 1116 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1117 return (0); 1118 } 1119 1120 #else 1121 static uint32_t 1122 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 1123 { 1124 1125 if (ti_gpio_valid_pin(sc, irq) != 0) 1126 return (0); 1127 1128 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 1129 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1130 return (TI_GPIO_LEVELDETECT0); 1131 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1132 return (TI_GPIO_LEVELDETECT1); 1133 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 1134 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1135 return (TI_GPIO_FALLINGDETECT); 1136 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1137 return (TI_GPIO_RISINGDETECT); 1138 } 1139 1140 return (0); 1141 } 1142 1143 static void 1144 ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq) 1145 { 1146 uint32_t reg, val; 1147 1148 if (ti_gpio_valid_pin(sc, irq) != 0) 1149 return; 1150 1151 TI_GPIO_LOCK(sc); 1152 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq)); 1153 reg = ti_gpio_intr_reg(sc, irq); 1154 if (reg != 0) { 1155 val = ti_gpio_read_4(sc, reg); 1156 val &= ~TI_GPIO_MASK(irq); 1157 ti_gpio_write_4(sc, reg, val); 1158 } 1159 TI_GPIO_UNLOCK(sc); 1160 } 1161 1162 static void 1163 ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq) 1164 { 1165 uint32_t reg, val; 1166 1167 if (ti_gpio_valid_pin(sc, irq) != 0) 1168 return; 1169 1170 TI_GPIO_LOCK(sc); 1171 reg = ti_gpio_intr_reg(sc, irq); 1172 if (reg != 0) { 1173 val = ti_gpio_read_4(sc, reg); 1174 val |= TI_GPIO_MASK(irq); 1175 ti_gpio_write_4(sc, reg, val); 1176 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq)); 1177 } 1178 TI_GPIO_UNLOCK(sc); 1179 } 1180 1181 static void 1182 ti_gpio_mask_irq(void *source) 1183 { 1184 struct ti_gpio_mask_arg *arg = source; 1185 1186 ti_gpio_mask_irq_internal(arg->softc, arg->pin); 1187 } 1188 1189 static void 1190 ti_gpio_unmask_irq(void *source) 1191 { 1192 struct ti_gpio_mask_arg *arg = source; 1193 1194 ti_gpio_unmask_irq_internal(arg->softc, arg->pin); 1195 } 1196 1197 static int 1198 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 1199 struct resource *res) 1200 { 1201 struct ti_gpio_mask_arg mask_arg; 1202 1203 if (type != SYS_RES_IRQ) 1204 return (ENXIO); 1205 1206 /* Unmask the interrupt. */ 1207 mask_arg.pin = rman_get_start(res); 1208 mask_arg.softc = device_get_softc(dev); 1209 1210 ti_gpio_unmask_irq((void *)&mask_arg); 1211 1212 return (0); 1213 } 1214 1215 static int 1216 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 1217 struct resource *res) 1218 { 1219 int pin; 1220 1221 if (type != SYS_RES_IRQ) 1222 return (ENXIO); 1223 1224 /* Mask the interrupt. */ 1225 pin = rman_get_start(res); 1226 ti_gpio_mask_irq((void *)(uintptr_t)pin); 1227 1228 return (0); 1229 } 1230 1231 static int 1232 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 1233 enum intr_polarity pol) 1234 { 1235 struct ti_gpio_softc *sc; 1236 uint32_t oldreg, reg, val; 1237 1238 sc = device_get_softc(dev); 1239 if (ti_gpio_valid_pin(sc, irq) != 0) 1240 return (EINVAL); 1241 1242 /* There is no standard trigger or polarity. */ 1243 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 1244 return (EINVAL); 1245 1246 TI_GPIO_LOCK(sc); 1247 /* 1248 * TRM recommends add the new event before remove the old one to 1249 * avoid losing interrupts. 1250 */ 1251 oldreg = ti_gpio_intr_reg(sc, irq); 1252 sc->sc_irq_trigger[irq] = trig; 1253 sc->sc_irq_polarity[irq] = pol; 1254 reg = ti_gpio_intr_reg(sc, irq); 1255 if (reg != 0) { 1256 /* Apply the new settings. */ 1257 val = ti_gpio_read_4(sc, reg); 1258 val |= TI_GPIO_MASK(irq); 1259 ti_gpio_write_4(sc, reg, val); 1260 } 1261 if (reg != oldreg && oldreg != 0) { 1262 /* Remove the old settings. */ 1263 val = ti_gpio_read_4(sc, oldreg); 1264 val &= ~TI_GPIO_MASK(irq); 1265 ti_gpio_write_4(sc, oldreg, val); 1266 } 1267 TI_GPIO_UNLOCK(sc); 1268 1269 return (0); 1270 } 1271 1272 static int 1273 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 1274 int flags, driver_filter_t *filt, driver_intr_t *handler, 1275 void *arg, void **cookiep) 1276 { 1277 struct ti_gpio_softc *sc; 1278 struct intr_event *event; 1279 int pin, error; 1280 1281 sc = device_get_softc(dev); 1282 pin = rman_get_start(ires); 1283 if (ti_gpio_valid_pin(sc, pin) != 0) 1284 panic("%s: bad pin %d", __func__, pin); 1285 1286 event = sc->sc_events[pin]; 1287 if (event == NULL) { 1288 sc->sc_mask_args[pin].softc = sc; 1289 sc->sc_mask_args[pin].pin = pin; 1290 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0, 1291 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 1292 "gpio%d pin%d:", device_get_unit(dev), pin); 1293 if (error != 0) 1294 return (error); 1295 sc->sc_events[pin] = event; 1296 } 1297 intr_event_add_handler(event, device_get_nameunit(child), filt, 1298 handler, arg, intr_priority(flags), flags, cookiep); 1299 1300 return (0); 1301 } 1302 1303 static int 1304 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1305 void *cookie) 1306 { 1307 struct ti_gpio_softc *sc; 1308 int pin, err; 1309 1310 sc = device_get_softc(dev); 1311 pin = rman_get_start(ires); 1312 if (ti_gpio_valid_pin(sc, pin) != 0) 1313 panic("%s: bad pin %d", __func__, pin); 1314 if (sc->sc_events[pin] == NULL) 1315 panic("Trying to teardown unoccupied IRQ"); 1316 err = intr_event_remove_handler(cookie); 1317 if (!err) 1318 sc->sc_events[pin] = NULL; 1319 1320 return (err); 1321 } 1322 #endif 1323 1324 static phandle_t 1325 ti_gpio_get_node(device_t bus, device_t dev) 1326 { 1327 1328 /* We only have one child, the GPIO bus, which needs our own node. */ 1329 return (ofw_bus_get_node(bus)); 1330 } 1331 1332 static device_method_t ti_gpio_methods[] = { 1333 DEVMETHOD(device_attach, ti_gpio_attach), 1334 DEVMETHOD(device_detach, ti_gpio_detach), 1335 1336 /* GPIO protocol */ 1337 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1338 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1339 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1340 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1341 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1342 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1343 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1344 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1345 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1346 1347 #ifdef INTRNG 1348 /* Interrupt controller interface */ 1349 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1350 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1351 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1352 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1353 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1354 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1355 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1356 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1357 #else 1358 /* Bus interface */ 1359 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 1360 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1361 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1362 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1363 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1364 #endif 1365 1366 /* ofw_bus interface */ 1367 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1368 1369 {0, 0}, 1370 }; 1371 1372 driver_t ti_gpio_driver = { 1373 "gpio", 1374 ti_gpio_methods, 1375 sizeof(struct ti_gpio_softc), 1376 }; 1377