1 /*- 2 * Copyright (c) 2016 Svatopluk Kraus 3 * Copyright (c) 2016 Michal Meloun 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/conf.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/rman.h> 34 #include <sys/systm.h> 35 36 #include <machine/fdt.h> 37 #include <machine/intr.h> 38 #include <machine/resource.h> 39 40 #include <dev/ofw/ofw_bus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include "pic_if.h" 44 45 static struct ofw_compat_data compat_data[] = { 46 {"ti,omap4-wugen-mpu", 1}, 47 {NULL, 0} 48 }; 49 50 struct omap4_wugen_sc { 51 device_t sc_dev; 52 struct resource *sc_mem_res; 53 device_t sc_parent; 54 }; 55 56 static int 57 omap4_wugen_activate_intr(device_t dev, struct intr_irqsrc *isrc, 58 struct resource *res, struct intr_map_data *data) 59 { 60 struct omap4_wugen_sc *sc = device_get_softc(dev); 61 62 return (PIC_ACTIVATE_INTR(sc->sc_parent, isrc, res, data)); 63 } 64 65 static void 66 omap4_wugen_disable_intr(device_t dev, struct intr_irqsrc *isrc) 67 { 68 struct omap4_wugen_sc *sc = device_get_softc(dev); 69 70 PIC_DISABLE_INTR(sc->sc_parent, isrc); 71 } 72 73 static void 74 omap4_wugen_enable_intr(device_t dev, struct intr_irqsrc *isrc) 75 { 76 struct omap4_wugen_sc *sc = device_get_softc(dev); 77 78 PIC_ENABLE_INTR(sc->sc_parent, isrc); 79 } 80 81 static int 82 omap4_wugen_map_intr(device_t dev, struct intr_map_data *data, 83 struct intr_irqsrc **isrcp) 84 { 85 struct omap4_wugen_sc *sc = device_get_softc(dev); 86 87 return (PIC_MAP_INTR(sc->sc_parent, data, isrcp)); 88 } 89 90 static int 91 omap4_wugen_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, 92 struct resource *res, struct intr_map_data *data) 93 { 94 struct omap4_wugen_sc *sc = device_get_softc(dev); 95 96 return (PIC_DEACTIVATE_INTR(sc->sc_parent, isrc, res, data)); 97 } 98 99 static int 100 omap4_wugen_setup_intr(device_t dev, struct intr_irqsrc *isrc, 101 struct resource *res, struct intr_map_data *data) 102 { 103 struct omap4_wugen_sc *sc = device_get_softc(dev); 104 105 return (PIC_SETUP_INTR(sc->sc_parent, isrc, res, data)); 106 } 107 108 static int 109 omap4_wugen_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 110 struct resource *res, struct intr_map_data *data) 111 { 112 struct omap4_wugen_sc *sc = device_get_softc(dev); 113 114 return (PIC_TEARDOWN_INTR(sc->sc_parent, isrc, res, data)); 115 } 116 117 static void 118 omap4_wugen_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 119 { 120 struct omap4_wugen_sc *sc = device_get_softc(dev); 121 122 PIC_PRE_ITHREAD(sc->sc_parent, isrc); 123 } 124 125 static void 126 omap4_wugen_post_ithread(device_t dev, struct intr_irqsrc *isrc) 127 { 128 struct omap4_wugen_sc *sc = device_get_softc(dev); 129 130 PIC_POST_ITHREAD(sc->sc_parent, isrc); 131 } 132 133 static void 134 omap4_wugen_post_filter(device_t dev, struct intr_irqsrc *isrc) 135 { 136 struct omap4_wugen_sc *sc = device_get_softc(dev); 137 138 PIC_POST_FILTER(sc->sc_parent, isrc); 139 } 140 141 #ifdef SMP 142 static int 143 omap4_wugen_bind_intr(device_t dev, struct intr_irqsrc *isrc) 144 { 145 struct omap4_wugen_sc *sc = device_get_softc(dev); 146 147 return (PIC_BIND_INTR(sc->sc_parent, isrc)); 148 } 149 #endif 150 151 static int 152 omap4_wugen_probe(device_t dev) 153 { 154 155 if (!ofw_bus_status_okay(dev)) 156 return (ENXIO); 157 158 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 159 return (ENXIO); 160 161 return (BUS_PROBE_DEFAULT); 162 } 163 164 static int 165 omap4_wugen_detach(device_t dev) 166 { 167 struct omap4_wugen_sc *sc; 168 169 sc = device_get_softc(dev); 170 if (sc->sc_mem_res != NULL) { 171 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 172 sc->sc_mem_res = NULL; 173 } 174 return (0); 175 } 176 177 static int 178 omap4_wugen_attach(device_t dev) 179 { 180 struct omap4_wugen_sc *sc; 181 phandle_t node; 182 phandle_t parent_xref; 183 int rid, rv; 184 185 sc = device_get_softc(dev); 186 sc->sc_dev = dev; 187 node = ofw_bus_get_node(dev); 188 189 rv = OF_getencprop(node, "interrupt-parent", &parent_xref, 190 sizeof(parent_xref)); 191 if (rv <= 0) { 192 device_printf(dev, "can't read parent node property\n"); 193 goto fail; 194 } 195 sc->sc_parent = OF_device_from_xref(parent_xref); 196 if (sc->sc_parent == NULL) { 197 device_printf(dev, "can't find parent controller\n"); 198 goto fail; 199 } 200 201 rid = 0; 202 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 203 RF_ACTIVE); 204 if (sc->sc_mem_res == NULL) { 205 device_printf(dev, "can't allocate resources\n"); 206 return (ENXIO); 207 } 208 209 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 210 device_printf(dev, "can't register PIC\n"); 211 goto fail; 212 } 213 return (0); 214 215 fail: 216 omap4_wugen_detach(dev); 217 return (ENXIO); 218 } 219 220 static device_method_t omap4_wugen_methods[] = { 221 DEVMETHOD(device_probe, omap4_wugen_probe), 222 DEVMETHOD(device_attach, omap4_wugen_attach), 223 DEVMETHOD(device_detach, omap4_wugen_detach), 224 225 /* Interrupt controller interface */ 226 DEVMETHOD(pic_activate_intr, omap4_wugen_activate_intr), 227 DEVMETHOD(pic_disable_intr, omap4_wugen_disable_intr), 228 DEVMETHOD(pic_enable_intr, omap4_wugen_enable_intr), 229 DEVMETHOD(pic_map_intr, omap4_wugen_map_intr), 230 DEVMETHOD(pic_deactivate_intr, omap4_wugen_deactivate_intr), 231 DEVMETHOD(pic_setup_intr, omap4_wugen_setup_intr), 232 DEVMETHOD(pic_teardown_intr, omap4_wugen_teardown_intr), 233 DEVMETHOD(pic_pre_ithread, omap4_wugen_pre_ithread), 234 DEVMETHOD(pic_post_ithread, omap4_wugen_post_ithread), 235 DEVMETHOD(pic_post_filter, omap4_wugen_post_filter), 236 #ifdef SMP 237 DEVMETHOD(pic_bind_intr, omap4_wugen_bind_intr), 238 #endif 239 DEVMETHOD_END 240 }; 241 242 DEFINE_CLASS_0(omap4_wugen, omap4_wugen_driver, omap4_wugen_methods, 243 sizeof(struct omap4_wugen_sc)); 244 EARLY_DRIVER_MODULE(omap4_wugen, simplebus, omap4_wugen_driver, NULL, NULL, 245 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1); 246