1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Based on OMAP3 INTC code by Ben Gray 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_platform.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/ktr.h> 39 #include <sys/module.h> 40 #include <sys/proc.h> 41 #include <sys/rman.h> 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include "pic_if.h" 50 51 #define INTC_REVISION 0x00 52 #define INTC_SYSCONFIG 0x10 53 #define INTC_SYSSTATUS 0x14 54 #define INTC_SIR_IRQ 0x40 55 #define INTC_CONTROL 0x48 56 #define INTC_THRESHOLD 0x68 57 #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) 58 #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) 59 #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) 60 #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) 61 62 #define INTC_SIR_SPURIOUS_MASK 0xffffff80 63 #define INTC_SIR_ACTIVE_MASK 0x7f 64 65 #define INTC_NIRQS 128 66 67 struct ti_aintc_irqsrc { 68 struct intr_irqsrc tai_isrc; 69 u_int tai_irq; 70 }; 71 72 struct ti_aintc_softc { 73 device_t sc_dev; 74 struct resource * aintc_res[3]; 75 bus_space_tag_t aintc_bst; 76 bus_space_handle_t aintc_bsh; 77 uint8_t ver; 78 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS]; 79 }; 80 81 static struct resource_spec ti_aintc_spec[] = { 82 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 83 { -1, 0 } 84 }; 85 86 #define aintc_read_4(_sc, reg) \ 87 bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg)) 88 #define aintc_write_4(_sc, reg, val) \ 89 bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val)) 90 91 /* List of compatible strings for FDT tree */ 92 static struct ofw_compat_data compat_data[] = { 93 {"ti,am33xx-intc", 1}, 94 {"ti,omap2-intc", 1}, 95 {NULL, 0}, 96 }; 97 98 static inline void 99 ti_aintc_irq_eoi(struct ti_aintc_softc *sc) 100 { 101 102 aintc_write_4(sc, INTC_CONTROL, 1); 103 } 104 105 static inline void 106 ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq) 107 { 108 109 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); 110 } 111 112 static inline void 113 ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq) 114 { 115 116 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); 117 } 118 119 static int 120 ti_aintc_intr(void *arg) 121 { 122 uint32_t irq; 123 struct ti_aintc_softc *sc = arg; 124 125 /* Get active interrupt */ 126 irq = aintc_read_4(sc, INTC_SIR_IRQ); 127 if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) { 128 device_printf(sc->sc_dev, 129 "Spurious interrupt detected (0x%08x)\n", irq); 130 ti_aintc_irq_eoi(sc); 131 return (FILTER_HANDLED); 132 } 133 134 /* Only level-sensitive interrupts detection is supported. */ 135 irq &= INTC_SIR_ACTIVE_MASK; 136 if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc, 137 curthread->td_intr_frame) != 0) { 138 ti_aintc_irq_mask(sc, irq); 139 ti_aintc_irq_eoi(sc); 140 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); 141 } 142 143 arm_irq_memory_barrier(irq); /* XXX */ 144 return (FILTER_HANDLED); 145 } 146 147 static void 148 ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 149 { 150 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 151 struct ti_aintc_softc *sc = device_get_softc(dev); 152 153 arm_irq_memory_barrier(irq); 154 ti_aintc_irq_unmask(sc, irq); 155 } 156 157 static void 158 ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 159 { 160 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 161 struct ti_aintc_softc *sc = device_get_softc(dev); 162 163 ti_aintc_irq_mask(sc, irq); 164 } 165 166 static int 167 ti_aintc_map_intr(device_t dev, struct intr_map_data *data, 168 struct intr_irqsrc **isrcp) 169 { 170 struct intr_map_data_fdt *daf; 171 struct ti_aintc_softc *sc; 172 173 if (data->type != INTR_MAP_DATA_FDT) 174 return (ENOTSUP); 175 176 daf = (struct intr_map_data_fdt *)data; 177 if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS) 178 return (EINVAL); 179 180 sc = device_get_softc(dev); 181 *isrcp = &sc->aintc_isrcs[daf->cells[0]].tai_isrc; 182 return (0); 183 } 184 185 static void 186 ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 187 { 188 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 189 struct ti_aintc_softc *sc = device_get_softc(dev); 190 191 ti_aintc_irq_mask(sc, irq); 192 ti_aintc_irq_eoi(sc); 193 } 194 195 static void 196 ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 197 { 198 199 ti_aintc_enable_intr(dev, isrc); 200 } 201 202 static void 203 ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc) 204 { 205 206 ti_aintc_irq_eoi(device_get_softc(dev)); 207 } 208 209 static int 210 ti_aintc_pic_attach(struct ti_aintc_softc *sc) 211 { 212 struct intr_pic *pic; 213 int error; 214 uint32_t irq; 215 const char *name; 216 intptr_t xref; 217 218 name = device_get_nameunit(sc->sc_dev); 219 for (irq = 0; irq < INTC_NIRQS; irq++) { 220 sc->aintc_isrcs[irq].tai_irq = irq; 221 222 error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc, 223 sc->sc_dev, 0, "%s,%u", name, irq); 224 if (error != 0) 225 return (error); 226 } 227 228 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 229 pic = intr_pic_register(sc->sc_dev, xref); 230 if (pic == NULL) 231 return (ENXIO); 232 233 return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc)); 234 } 235 236 static int 237 ti_aintc_probe(device_t dev) 238 { 239 if (!ofw_bus_status_okay(dev)) 240 return (ENXIO); 241 242 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 243 return (ENXIO); 244 245 device_set_desc(dev, "TI AINTC Interrupt Controller"); 246 return (BUS_PROBE_DEFAULT); 247 } 248 249 static int 250 ti_aintc_attach(device_t dev) 251 { 252 struct ti_aintc_softc *sc = device_get_softc(dev); 253 uint32_t x; 254 255 sc->sc_dev = dev; 256 257 if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { 258 device_printf(dev, "could not allocate resources\n"); 259 return (ENXIO); 260 } 261 262 sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); 263 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); 264 265 x = aintc_read_4(sc, INTC_REVISION); 266 device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); 267 268 /* SoftReset */ 269 aintc_write_4(sc, INTC_SYSCONFIG, 2); 270 271 /* Wait for reset to complete */ 272 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1)); 273 274 /*Set Priority Threshold */ 275 aintc_write_4(sc, INTC_THRESHOLD, 0xFF); 276 277 if (ti_aintc_pic_attach(sc) != 0) { 278 device_printf(dev, "could not attach PIC\n"); 279 return (ENXIO); 280 } 281 return (0); 282 } 283 284 static device_method_t ti_aintc_methods[] = { 285 DEVMETHOD(device_probe, ti_aintc_probe), 286 DEVMETHOD(device_attach, ti_aintc_attach), 287 288 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr), 289 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr), 290 DEVMETHOD(pic_map_intr, ti_aintc_map_intr), 291 DEVMETHOD(pic_post_filter, ti_aintc_post_filter), 292 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread), 293 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread), 294 { 0, 0 } 295 }; 296 297 static driver_t ti_aintc_driver = { 298 "ti_aintc", 299 ti_aintc_methods, 300 sizeof(struct ti_aintc_softc), 301 }; 302 303 EARLY_DRIVER_MODULE(ti_aintc, simplebus, ti_aintc_driver, 0, 0, 304 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 305 SIMPLEBUS_PNP_INFO(compat_data); 306