1ef2ee5d0SMichal Meloun /*- 2ef2ee5d0SMichal Meloun * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3ef2ee5d0SMichal Meloun * All rights reserved. 4ef2ee5d0SMichal Meloun * 5ef2ee5d0SMichal Meloun * Redistribution and use in source and binary forms, with or without 6ef2ee5d0SMichal Meloun * modification, are permitted provided that the following conditions 7ef2ee5d0SMichal Meloun * are met: 8ef2ee5d0SMichal Meloun * 1. Redistributions of source code must retain the above copyright 9ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer. 10ef2ee5d0SMichal Meloun * 2. Redistributions in binary form must reproduce the above copyright 11ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer in the 12ef2ee5d0SMichal Meloun * documentation and/or other materials provided with the distribution. 13ef2ee5d0SMichal Meloun * 14ef2ee5d0SMichal Meloun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15ef2ee5d0SMichal Meloun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16ef2ee5d0SMichal Meloun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17ef2ee5d0SMichal Meloun * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18ef2ee5d0SMichal Meloun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19ef2ee5d0SMichal Meloun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20ef2ee5d0SMichal Meloun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21ef2ee5d0SMichal Meloun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22ef2ee5d0SMichal Meloun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23ef2ee5d0SMichal Meloun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24ef2ee5d0SMichal Meloun * SUCH DAMAGE. 25ef2ee5d0SMichal Meloun */ 26ef2ee5d0SMichal Meloun 27ef2ee5d0SMichal Meloun #include <sys/cdefs.h> 28ef2ee5d0SMichal Meloun __FBSDID("$FreeBSD$"); 29ef2ee5d0SMichal Meloun 30ef2ee5d0SMichal Meloun /* 31ef2ee5d0SMichal Meloun * Thermometer and thermal zones driver for Tegra SoCs. 32ef2ee5d0SMichal Meloun * Calibration data and algo are taken from Linux, because this part of SoC 33ef2ee5d0SMichal Meloun * is undocumented in TRM. 34ef2ee5d0SMichal Meloun */ 35ef2ee5d0SMichal Meloun 36ef2ee5d0SMichal Meloun #include <sys/param.h> 37ef2ee5d0SMichal Meloun #include <sys/systm.h> 38ef2ee5d0SMichal Meloun #include <sys/bus.h> 39ef2ee5d0SMichal Meloun #include <sys/gpio.h> 40ef2ee5d0SMichal Meloun #include <sys/kernel.h> 41ef2ee5d0SMichal Meloun #include <sys/module.h> 42ef2ee5d0SMichal Meloun #include <sys/malloc.h> 43ef2ee5d0SMichal Meloun #include <sys/rman.h> 44ef2ee5d0SMichal Meloun #include <sys/sysctl.h> 45ef2ee5d0SMichal Meloun 46ef2ee5d0SMichal Meloun #include <machine/bus.h> 47ef2ee5d0SMichal Meloun 48ef2ee5d0SMichal Meloun #include <dev/extres/clk/clk.h> 49ef2ee5d0SMichal Meloun #include <dev/extres/hwreset/hwreset.h> 50ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus.h> 51ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus_subr.h> 52ef2ee5d0SMichal Meloun 53ef2ee5d0SMichal Meloun #include <arm/nvidia/tegra_efuse.h> 54ef2ee5d0SMichal Meloun #include <gnu/dts/include/dt-bindings/thermal/tegra124-soctherm.h> 55ef2ee5d0SMichal Meloun #include "tegra_soctherm_if.h" 56ef2ee5d0SMichal Meloun 57ef2ee5d0SMichal Meloun /* Per sensors registers - base is 0x0c0*/ 58ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0 0x000 59ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_TALL(x) (((x) & 0xFFFFF) << 8) 60ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_STATUS_CLR (1 << 5) 61ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_TCALC_OVERFLOW (1 << 4) 62ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_OVERFLOW (1 << 3) 63ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_CPTR_OVERFLOW (1 << 2) 64ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_RO_SEL (1 << 1) 65ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG0_STOP (1 << 0) 66ef2ee5d0SMichal Meloun 67ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG1 0x004 68ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG1_TEMP_ENABLE (1U << 31) 69ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG1_TEN_COUNT(x) (((x) & 0x3F) << 24) 70ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG1_TIDDQ_EN(x) (((x) & 0x3F) << 15) 71ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG1_TSAMPLE(x) (((x) & 0x3FF) << 0) 72ef2ee5d0SMichal Meloun 73ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG2 0x008 74ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG2_THERMA(x) (((x) & 0xFFFF) << 16) 75ef2ee5d0SMichal Meloun #define TSENSOR_CONFIG2_THERMB(x) (((x) & 0xFFFF) << 0) 76ef2ee5d0SMichal Meloun 77ef2ee5d0SMichal Meloun #define TSENSOR_STATUS0 0x00c 78ef2ee5d0SMichal Meloun #define TSENSOR_STATUS0_CAPTURE_VALID (1U << 31) 79ef2ee5d0SMichal Meloun #define TSENSOR_STATUS0_CAPTURE(x) (((x) >> 0) & 0xffff) 80ef2ee5d0SMichal Meloun 81ef2ee5d0SMichal Meloun #define TSENSOR_STATUS1 0x010 82ef2ee5d0SMichal Meloun #define TSENSOR_STATUS1_TEMP_VALID (1U << 31) 83ef2ee5d0SMichal Meloun #define TSENSOR_STATUS1_TEMP(x) (((x) >> 0) & 0xffff) 84ef2ee5d0SMichal Meloun 85ef2ee5d0SMichal Meloun #define TSENSOR_STATUS2 0x014 86ef2ee5d0SMichal Meloun #define TSENSOR_STATUS2_TEMP_MAX(x) (((x) >> 16) & 0xffff) 87ef2ee5d0SMichal Meloun #define TSENSOR_STATUS2_TEMP_MIN(x) (((x) >> 0) & 0xffff) 88ef2ee5d0SMichal Meloun 89ef2ee5d0SMichal Meloun /* Global registers */ 90ef2ee5d0SMichal Meloun #define TSENSOR_PDIV 0x1c0 91ef2ee5d0SMichal Meloun #define TSENSOR_PDIV_T124 0x8888 92ef2ee5d0SMichal Meloun #define TSENSOR_HOTSPOT_OFF 0x1c4 93ef2ee5d0SMichal Meloun #define TSENSOR_HOTSPOT_OFF_T124 0x00060600 94ef2ee5d0SMichal Meloun #define TSENSOR_TEMP1 0x1c8 95ef2ee5d0SMichal Meloun #define TSENSOR_TEMP2 0x1cc 96ef2ee5d0SMichal Meloun 97ef2ee5d0SMichal Meloun /* Readbacks */ 98ef2ee5d0SMichal Meloun #define READBACK_VALUE_MASK 0xff00 99ef2ee5d0SMichal Meloun #define READBACK_VALUE_SHIFT 8 100ef2ee5d0SMichal Meloun #define READBACK_ADD_HALF (1 << 7) 101ef2ee5d0SMichal Meloun #define READBACK_NEGATE (1 << 0) 102ef2ee5d0SMichal Meloun 103ef2ee5d0SMichal Meloun 104ef2ee5d0SMichal Meloun /* Fuses */ 105ef2ee5d0SMichal Meloun #define FUSE_TSENSOR_CALIB_CP_TS_BASE_SHIFT 0 106ef2ee5d0SMichal Meloun #define FUSE_TSENSOR_CALIB_CP_TS_BASE_BITS 13 107ef2ee5d0SMichal Meloun #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13 108ef2ee5d0SMichal Meloun #define FUSE_TSENSOR_CALIB_FT_TS_BASE_BITS 13 109ef2ee5d0SMichal Meloun 110ef2ee5d0SMichal Meloun #define FUSE_TSENSOR8_CALIB 0x180 111ef2ee5d0SMichal Meloun #define FUSE_TSENSOR8_CALIB_CP_TS_BASE(x) (((x) >> 0) & 0x3ff) 112ef2ee5d0SMichal Meloun #define FUSE_TSENSOR8_CALIB_FT_TS_BASE(x) (((x) >> 10) & 0x7ff) 113ef2ee5d0SMichal Meloun 114ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG 0x1fc 115ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_SHIFT 0 116ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_BITS 6 117ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21 118ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_BITS 5 119ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP(x) (((x) >> 0) & 0x3f) 120ef2ee5d0SMichal Meloun #define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT(x) (((x) >> 21) & 0x1f) 121ef2ee5d0SMichal Meloun 122ef2ee5d0SMichal Meloun 123ef2ee5d0SMichal Meloun #define NOMINAL_CALIB_FT_T124 105 124ef2ee5d0SMichal Meloun #define NOMINAL_CALIB_CP_T124 25 125ef2ee5d0SMichal Meloun 126ef2ee5d0SMichal Meloun #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 127ef2ee5d0SMichal Meloun #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 128ef2ee5d0SMichal Meloun 129ef2ee5d0SMichal Meloun static struct sysctl_ctx_list soctherm_sysctl_ctx; 130ef2ee5d0SMichal Meloun 131ef2ee5d0SMichal Meloun struct soctherm_shared_cal { 132ef2ee5d0SMichal Meloun uint32_t base_cp; 133ef2ee5d0SMichal Meloun uint32_t base_ft; 134ef2ee5d0SMichal Meloun int32_t actual_temp_cp; 135ef2ee5d0SMichal Meloun int32_t actual_temp_ft; 136ef2ee5d0SMichal Meloun }; 137ef2ee5d0SMichal Meloun struct tsensor_cfg { 138ef2ee5d0SMichal Meloun uint32_t tall; 139ef2ee5d0SMichal Meloun uint32_t tsample; 140ef2ee5d0SMichal Meloun uint32_t tiddq_en; 141ef2ee5d0SMichal Meloun uint32_t ten_count; 142ef2ee5d0SMichal Meloun uint32_t pdiv; 143ef2ee5d0SMichal Meloun uint32_t tsample_ate; 144ef2ee5d0SMichal Meloun uint32_t pdiv_ate; 145ef2ee5d0SMichal Meloun }; 146ef2ee5d0SMichal Meloun 147ef2ee5d0SMichal Meloun struct tsensor { 148ef2ee5d0SMichal Meloun char *name; 149ef2ee5d0SMichal Meloun int id; 150ef2ee5d0SMichal Meloun struct tsensor_cfg *cfg; 151ef2ee5d0SMichal Meloun bus_addr_t sensor_base; 152ef2ee5d0SMichal Meloun bus_addr_t calib_fuse; 153ef2ee5d0SMichal Meloun int fuse_corr_alpha; 154ef2ee5d0SMichal Meloun int fuse_corr_beta; 155ef2ee5d0SMichal Meloun 156ef2ee5d0SMichal Meloun int16_t therm_a; 157ef2ee5d0SMichal Meloun int16_t therm_b; 158ef2ee5d0SMichal Meloun }; 159ef2ee5d0SMichal Meloun 160ef2ee5d0SMichal Meloun struct soctherm_softc { 161ef2ee5d0SMichal Meloun device_t dev; 162ef2ee5d0SMichal Meloun struct resource *mem_res; 163ef2ee5d0SMichal Meloun struct resource *irq_res; 164ef2ee5d0SMichal Meloun void *irq_ih; 165ef2ee5d0SMichal Meloun 166ef2ee5d0SMichal Meloun clk_t tsensor_clk; 167ef2ee5d0SMichal Meloun clk_t soctherm_clk; 168ef2ee5d0SMichal Meloun hwreset_t reset; 169ef2ee5d0SMichal Meloun 170ef2ee5d0SMichal Meloun int ntsensors; 171ef2ee5d0SMichal Meloun struct tsensor *tsensors; 172ef2ee5d0SMichal Meloun }; 173ef2ee5d0SMichal Meloun 174ef2ee5d0SMichal Meloun static struct ofw_compat_data compat_data[] = { 175ef2ee5d0SMichal Meloun {"nvidia,tegra124-soctherm", 1}, 176ef2ee5d0SMichal Meloun {NULL, 0}, 177ef2ee5d0SMichal Meloun }; 178ef2ee5d0SMichal Meloun 179ef2ee5d0SMichal Meloun static struct tsensor_cfg t124_tsensor_config = { 180ef2ee5d0SMichal Meloun .tall = 16300, 181ef2ee5d0SMichal Meloun .tsample = 120, 182ef2ee5d0SMichal Meloun .tiddq_en = 1, 183ef2ee5d0SMichal Meloun .ten_count = 1, 184ef2ee5d0SMichal Meloun .pdiv = 8, 185ef2ee5d0SMichal Meloun .tsample_ate = 480, 186ef2ee5d0SMichal Meloun .pdiv_ate = 8 187ef2ee5d0SMichal Meloun }; 188ef2ee5d0SMichal Meloun 189ef2ee5d0SMichal Meloun 190ef2ee5d0SMichal Meloun static struct tsensor t124_tsensors[] = { 191ef2ee5d0SMichal Meloun { 192ef2ee5d0SMichal Meloun .name = "cpu0", 193ef2ee5d0SMichal Meloun .id = TEGRA124_SOCTHERM_SENSOR_CPU, 194ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 195ef2ee5d0SMichal Meloun .sensor_base = 0x0c0, 196ef2ee5d0SMichal Meloun .calib_fuse = 0x098, 197ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1135400, 198ef2ee5d0SMichal Meloun .fuse_corr_beta = -6266900, 199ef2ee5d0SMichal Meloun }, 200ef2ee5d0SMichal Meloun { 201ef2ee5d0SMichal Meloun .name = "cpu1", 202ef2ee5d0SMichal Meloun .id = -1, 203ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 204ef2ee5d0SMichal Meloun .sensor_base = 0x0e0, 205ef2ee5d0SMichal Meloun .calib_fuse = 0x084, 206ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1122220, 207ef2ee5d0SMichal Meloun .fuse_corr_beta = -5700700, 208ef2ee5d0SMichal Meloun }, 209ef2ee5d0SMichal Meloun { 210ef2ee5d0SMichal Meloun .name = "cpu2", 211ef2ee5d0SMichal Meloun .id = -1, 212ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 213ef2ee5d0SMichal Meloun .sensor_base = 0x100, 214ef2ee5d0SMichal Meloun .calib_fuse = 0x088, 215ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1127000, 216ef2ee5d0SMichal Meloun .fuse_corr_beta = -6768200, 217ef2ee5d0SMichal Meloun }, 218ef2ee5d0SMichal Meloun { 219ef2ee5d0SMichal Meloun .name = "cpu3", 220ef2ee5d0SMichal Meloun .id = -1, 221ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 222ef2ee5d0SMichal Meloun .sensor_base = 0x120, 223ef2ee5d0SMichal Meloun .calib_fuse = 0x12c, 224ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1110900, 225ef2ee5d0SMichal Meloun .fuse_corr_beta = -6232000, 226ef2ee5d0SMichal Meloun }, 227ef2ee5d0SMichal Meloun { 228ef2ee5d0SMichal Meloun .name = "mem0", 229ef2ee5d0SMichal Meloun .id = TEGRA124_SOCTHERM_SENSOR_MEM, 230ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 231ef2ee5d0SMichal Meloun .sensor_base = 0x140, 232ef2ee5d0SMichal Meloun .calib_fuse = 0x158, 233ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1122300, 234ef2ee5d0SMichal Meloun .fuse_corr_beta = -5936400, 235ef2ee5d0SMichal Meloun }, 236ef2ee5d0SMichal Meloun { 237ef2ee5d0SMichal Meloun .name = "mem1", 238ef2ee5d0SMichal Meloun .id = -1, 239ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 240ef2ee5d0SMichal Meloun .sensor_base = 0x160, 241ef2ee5d0SMichal Meloun .calib_fuse = 0x15c, 242ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1145700, 243ef2ee5d0SMichal Meloun .fuse_corr_beta = -7124600, 244ef2ee5d0SMichal Meloun }, 245ef2ee5d0SMichal Meloun { 246ef2ee5d0SMichal Meloun .name = "gpu", 247ef2ee5d0SMichal Meloun .id = TEGRA124_SOCTHERM_SENSOR_GPU, 248ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 249ef2ee5d0SMichal Meloun .sensor_base = 0x180, 250ef2ee5d0SMichal Meloun .calib_fuse = 0x154, 251ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1120100, 252ef2ee5d0SMichal Meloun .fuse_corr_beta = -6000500, 253ef2ee5d0SMichal Meloun }, 254ef2ee5d0SMichal Meloun { 255ef2ee5d0SMichal Meloun .name = "pllX", 256ef2ee5d0SMichal Meloun .id = TEGRA124_SOCTHERM_SENSOR_PLLX, 257ef2ee5d0SMichal Meloun .cfg = &t124_tsensor_config, 258ef2ee5d0SMichal Meloun .sensor_base = 0x1a0, 259ef2ee5d0SMichal Meloun .calib_fuse = 0x160, 260ef2ee5d0SMichal Meloun .fuse_corr_alpha = 1106500, 261ef2ee5d0SMichal Meloun .fuse_corr_beta = -6729300, 262ef2ee5d0SMichal Meloun }, 263ef2ee5d0SMichal Meloun }; 264ef2ee5d0SMichal Meloun 265ef2ee5d0SMichal Meloun /* Extract signed integer bitfield from register */ 266ef2ee5d0SMichal Meloun static int 267ef2ee5d0SMichal Meloun extract_signed(uint32_t reg, int shift, int bits) 268ef2ee5d0SMichal Meloun { 269ef2ee5d0SMichal Meloun int32_t val; 270ef2ee5d0SMichal Meloun uint32_t mask; 271ef2ee5d0SMichal Meloun 272ef2ee5d0SMichal Meloun mask = (1 << bits) - 1; 273ef2ee5d0SMichal Meloun val = ((reg >> shift) & mask) << (32 - bits); 274ef2ee5d0SMichal Meloun val >>= 32 - bits; 275ef2ee5d0SMichal Meloun return ((int32_t)val); 276ef2ee5d0SMichal Meloun } 277ef2ee5d0SMichal Meloun 278ef2ee5d0SMichal Meloun static inline int64_t div64_s64_precise(int64_t a, int64_t b) 279ef2ee5d0SMichal Meloun { 280ef2ee5d0SMichal Meloun int64_t r, al; 281ef2ee5d0SMichal Meloun 282ef2ee5d0SMichal Meloun al = a << 16; 283ef2ee5d0SMichal Meloun r = (al * 2 + 1) / (2 * b); 284ef2ee5d0SMichal Meloun return r >> 16; 285ef2ee5d0SMichal Meloun } 286ef2ee5d0SMichal Meloun 287ef2ee5d0SMichal Meloun static void 288ef2ee5d0SMichal Meloun get_shared_cal(struct soctherm_softc *sc, struct soctherm_shared_cal *cal) 289ef2ee5d0SMichal Meloun { 290ef2ee5d0SMichal Meloun uint32_t val; 291ef2ee5d0SMichal Meloun int calib_cp, calib_ft; 292ef2ee5d0SMichal Meloun 293ef2ee5d0SMichal Meloun val = tegra_fuse_read_4(FUSE_TSENSOR8_CALIB); 294ef2ee5d0SMichal Meloun cal->base_cp = FUSE_TSENSOR8_CALIB_CP_TS_BASE(val); 295ef2ee5d0SMichal Meloun cal->base_ft = FUSE_TSENSOR8_CALIB_FT_TS_BASE(val); 296ef2ee5d0SMichal Meloun 297ef2ee5d0SMichal Meloun val = tegra_fuse_read_4(FUSE_SPARE_REALIGNMENT_REG); 298ef2ee5d0SMichal Meloun calib_ft = extract_signed(val, 299ef2ee5d0SMichal Meloun FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT, 300ef2ee5d0SMichal Meloun FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_BITS); 301ef2ee5d0SMichal Meloun calib_cp = extract_signed(val, 302ef2ee5d0SMichal Meloun FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_SHIFT, 303ef2ee5d0SMichal Meloun FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_BITS); 304ef2ee5d0SMichal Meloun 305ef2ee5d0SMichal Meloun cal->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + calib_cp; 306ef2ee5d0SMichal Meloun cal->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + calib_ft; 307ef2ee5d0SMichal Meloun #ifdef DEBUG 308ef2ee5d0SMichal Meloun printf("%s: base_cp: %u, base_ft: %d," 309ef2ee5d0SMichal Meloun " actual_temp_cp: %d, actual_temp_ft: %d\n", 310ef2ee5d0SMichal Meloun __func__, cal->base_cp, cal->base_ft, 311ef2ee5d0SMichal Meloun cal->actual_temp_cp, cal->actual_temp_ft); 312ef2ee5d0SMichal Meloun #endif 313ef2ee5d0SMichal Meloun } 314ef2ee5d0SMichal Meloun 315ef2ee5d0SMichal Meloun 316ef2ee5d0SMichal Meloun static void 317ef2ee5d0SMichal Meloun tsensor_calibration(struct tsensor *sensor, struct soctherm_shared_cal *shared) 318ef2ee5d0SMichal Meloun { 319ef2ee5d0SMichal Meloun uint32_t val; 320ef2ee5d0SMichal Meloun int mult, div, calib_cp, calib_ft; 321ef2ee5d0SMichal Meloun int actual_tsensor_ft, actual_tsensor_cp, delta_sens, delta_temp; 322ef2ee5d0SMichal Meloun int temp_a, temp_b; 323ef2ee5d0SMichal Meloun int64_t tmp; 324ef2ee5d0SMichal Meloun 325ef2ee5d0SMichal Meloun val = tegra_fuse_read_4(sensor->calib_fuse); 326ef2ee5d0SMichal Meloun calib_cp = extract_signed(val, 327ef2ee5d0SMichal Meloun FUSE_TSENSOR_CALIB_CP_TS_BASE_SHIFT, 328ef2ee5d0SMichal Meloun FUSE_TSENSOR_CALIB_CP_TS_BASE_BITS); 329ef2ee5d0SMichal Meloun actual_tsensor_cp = shared->base_cp * 64 + calib_cp; 330ef2ee5d0SMichal Meloun 331ef2ee5d0SMichal Meloun calib_ft = extract_signed(val, 332ef2ee5d0SMichal Meloun FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT, 333ef2ee5d0SMichal Meloun FUSE_TSENSOR_CALIB_FT_TS_BASE_BITS); 334ef2ee5d0SMichal Meloun actual_tsensor_ft = shared->base_ft * 32 + calib_ft; 335ef2ee5d0SMichal Meloun 336ef2ee5d0SMichal Meloun delta_sens = actual_tsensor_ft - actual_tsensor_cp; 337ef2ee5d0SMichal Meloun delta_temp = shared->actual_temp_ft - shared->actual_temp_cp; 338ef2ee5d0SMichal Meloun mult = sensor->cfg->pdiv * sensor->cfg->tsample_ate; 339ef2ee5d0SMichal Meloun div = sensor->cfg->tsample * sensor->cfg->pdiv_ate; 340ef2ee5d0SMichal Meloun 341ef2ee5d0SMichal Meloun 342ef2ee5d0SMichal Meloun temp_a = div64_s64_precise((int64_t) delta_temp * (1LL << 13) * mult, 343ef2ee5d0SMichal Meloun (int64_t) delta_sens * div); 344ef2ee5d0SMichal Meloun 345ef2ee5d0SMichal Meloun tmp = (int64_t)actual_tsensor_ft * shared->actual_temp_cp - 346ef2ee5d0SMichal Meloun (int64_t)actual_tsensor_cp * shared->actual_temp_ft; 347ef2ee5d0SMichal Meloun temp_b = div64_s64_precise(tmp, (int64_t)delta_sens); 348ef2ee5d0SMichal Meloun 349ef2ee5d0SMichal Meloun temp_a = div64_s64_precise((int64_t)temp_a * sensor->fuse_corr_alpha, 350ef2ee5d0SMichal Meloun 1000000); 351ef2ee5d0SMichal Meloun temp_b = div64_s64_precise((int64_t)temp_b * sensor->fuse_corr_alpha + 352ef2ee5d0SMichal Meloun sensor->fuse_corr_beta, 1000000); 353ef2ee5d0SMichal Meloun sensor->therm_a = (int16_t)temp_a; 354ef2ee5d0SMichal Meloun sensor->therm_b = (int16_t)temp_b; 355ef2ee5d0SMichal Meloun #ifdef DEBUG 356ef2ee5d0SMichal Meloun printf("%s: sensor %s fuse: 0x%08X (0x%04X, 0x%04X)" 357ef2ee5d0SMichal Meloun " calib_cp: %d(0x%04X), calib_ft: %d(0x%04X)\n", 358ef2ee5d0SMichal Meloun __func__, sensor->name, val, val & 0x1FFF, (val >> 13) & 0x1FFF, 359ef2ee5d0SMichal Meloun calib_cp, calib_cp, calib_ft, calib_ft); 360ef2ee5d0SMichal Meloun printf("therma: 0x%04X(%d), thermb: 0x%04X(%d)\n", 361ef2ee5d0SMichal Meloun (uint16_t)sensor->therm_a, temp_a, 362ef2ee5d0SMichal Meloun (uint16_t)sensor->therm_b, sensor->therm_b); 363ef2ee5d0SMichal Meloun #endif 364ef2ee5d0SMichal Meloun } 365ef2ee5d0SMichal Meloun 366ef2ee5d0SMichal Meloun static void 367ef2ee5d0SMichal Meloun soctherm_init_tsensor(struct soctherm_softc *sc, struct tsensor *sensor, 368ef2ee5d0SMichal Meloun struct soctherm_shared_cal *shared_cal) 369ef2ee5d0SMichal Meloun { 370ef2ee5d0SMichal Meloun uint32_t val; 371ef2ee5d0SMichal Meloun 372ef2ee5d0SMichal Meloun tsensor_calibration(sensor, shared_cal); 373ef2ee5d0SMichal Meloun 374ef2ee5d0SMichal Meloun val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); 375ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG0_STOP; 376ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG0_STATUS_CLR; 377ef2ee5d0SMichal Meloun WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val); 378ef2ee5d0SMichal Meloun 379ef2ee5d0SMichal Meloun val = TSENSOR_CONFIG0_TALL(sensor->cfg->tall); 380ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG0_STOP; 381ef2ee5d0SMichal Meloun WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val); 382ef2ee5d0SMichal Meloun 383ef2ee5d0SMichal Meloun val = TSENSOR_CONFIG1_TSAMPLE(sensor->cfg->tsample - 1); 384ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG1_TIDDQ_EN(sensor->cfg->tiddq_en); 385ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG1_TEN_COUNT(sensor->cfg->ten_count); 386ef2ee5d0SMichal Meloun val |= TSENSOR_CONFIG1_TEMP_ENABLE; 387ef2ee5d0SMichal Meloun WR4(sc, sensor->sensor_base + TSENSOR_CONFIG1, val); 388ef2ee5d0SMichal Meloun 389ef2ee5d0SMichal Meloun val = TSENSOR_CONFIG2_THERMA((uint16_t)sensor->therm_a) | 390ef2ee5d0SMichal Meloun TSENSOR_CONFIG2_THERMB((uint16_t)sensor->therm_b); 391ef2ee5d0SMichal Meloun WR4(sc, sensor->sensor_base + TSENSOR_CONFIG2, val); 392ef2ee5d0SMichal Meloun 393ef2ee5d0SMichal Meloun val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); 394ef2ee5d0SMichal Meloun val &= ~TSENSOR_CONFIG0_STOP; 395ef2ee5d0SMichal Meloun WR4(sc, sensor->sensor_base + TSENSOR_CONFIG0, val); 396ef2ee5d0SMichal Meloun #ifdef DEBUG 397ef2ee5d0SMichal Meloun printf(" Sensor: %s cfg:0x%08X, 0x%08X, 0x%08X," 398ef2ee5d0SMichal Meloun " sts:0x%08X, 0x%08X, 0x%08X\n", sensor->name, 399ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), 400ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), 401ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), 402ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), 403ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), 404ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) 405ef2ee5d0SMichal Meloun ); 406ef2ee5d0SMichal Meloun #endif 407ef2ee5d0SMichal Meloun } 408ef2ee5d0SMichal Meloun 409ef2ee5d0SMichal Meloun static int 410ef2ee5d0SMichal Meloun soctherm_convert_raw(uint32_t val) 411ef2ee5d0SMichal Meloun { 412ef2ee5d0SMichal Meloun int32_t t; 413ef2ee5d0SMichal Meloun 414ef2ee5d0SMichal Meloun t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000; 415ef2ee5d0SMichal Meloun if (val & READBACK_ADD_HALF) 416ef2ee5d0SMichal Meloun t += 500; 417ef2ee5d0SMichal Meloun if (val & READBACK_NEGATE) 418ef2ee5d0SMichal Meloun t *= -1; 419ef2ee5d0SMichal Meloun 420ef2ee5d0SMichal Meloun return t; 421ef2ee5d0SMichal Meloun } 422ef2ee5d0SMichal Meloun 423ef2ee5d0SMichal Meloun static int 424ef2ee5d0SMichal Meloun soctherm_read_temp(struct soctherm_softc *sc, struct tsensor *sensor, int *temp) 425ef2ee5d0SMichal Meloun { 426ef2ee5d0SMichal Meloun int timeout; 427ef2ee5d0SMichal Meloun uint32_t val; 428ef2ee5d0SMichal Meloun 429ef2ee5d0SMichal Meloun 430ef2ee5d0SMichal Meloun /* wait for valid sample */ 431ef2ee5d0SMichal Meloun for (timeout = 1000; timeout > 0; timeout--) { 432ef2ee5d0SMichal Meloun val = RD4(sc, sensor->sensor_base + TSENSOR_STATUS1); 433ef2ee5d0SMichal Meloun if ((val & TSENSOR_STATUS1_TEMP_VALID) != 0) 434ef2ee5d0SMichal Meloun break; 435ef2ee5d0SMichal Meloun DELAY(100); 436ef2ee5d0SMichal Meloun } 437ef2ee5d0SMichal Meloun if (timeout <= 0) 438ef2ee5d0SMichal Meloun device_printf(sc->dev, "Sensor %s timeouted\n", sensor->name); 439ef2ee5d0SMichal Meloun *temp = soctherm_convert_raw(val); 440ef2ee5d0SMichal Meloun #ifdef DEBUG 441ef2ee5d0SMichal Meloun printf("%s: Raw: 0x%08X, temp: %d\n", __func__, val, *temp); 442ef2ee5d0SMichal Meloun printf(" Sensor: %s cfg:0x%08X, 0x%08X, 0x%08X," 443ef2ee5d0SMichal Meloun " sts:0x%08X, 0x%08X, 0x%08X\n", sensor->name, 444ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), 445ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), 446ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), 447ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), 448ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), 449ef2ee5d0SMichal Meloun RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) 450ef2ee5d0SMichal Meloun ); 451ef2ee5d0SMichal Meloun #endif 452ef2ee5d0SMichal Meloun return 0; 453ef2ee5d0SMichal Meloun } 454ef2ee5d0SMichal Meloun 455ef2ee5d0SMichal Meloun static int 456ef2ee5d0SMichal Meloun soctherm_get_temp(device_t dev, device_t cdev, uintptr_t id, int *val) 457ef2ee5d0SMichal Meloun { 458ef2ee5d0SMichal Meloun struct soctherm_softc *sc; 459ef2ee5d0SMichal Meloun int i; 460ef2ee5d0SMichal Meloun 461ef2ee5d0SMichal Meloun sc = device_get_softc(dev); 462ef2ee5d0SMichal Meloun /* The direct sensor map starts at 0x100 */ 463ef2ee5d0SMichal Meloun if (id >= 0x100) { 464ef2ee5d0SMichal Meloun id -= 0x100; 465ef2ee5d0SMichal Meloun if (id >= sc->ntsensors) 466ef2ee5d0SMichal Meloun return (ERANGE); 467ef2ee5d0SMichal Meloun return(soctherm_read_temp(sc, sc->tsensors + id, val)); 468ef2ee5d0SMichal Meloun } 469ef2ee5d0SMichal Meloun /* Linux (DT) compatible thermal zones */ 470ef2ee5d0SMichal Meloun for (i = 0; i < sc->ntsensors; i++) { 471ef2ee5d0SMichal Meloun if (sc->tsensors->id == id) 472ef2ee5d0SMichal Meloun return(soctherm_read_temp(sc, sc->tsensors + id, val)); 473ef2ee5d0SMichal Meloun } 474ef2ee5d0SMichal Meloun return (ERANGE); 475ef2ee5d0SMichal Meloun } 476ef2ee5d0SMichal Meloun 477ef2ee5d0SMichal Meloun static int 478ef2ee5d0SMichal Meloun soctherm_sysctl_temperature(SYSCTL_HANDLER_ARGS) 479ef2ee5d0SMichal Meloun { 480ef2ee5d0SMichal Meloun struct soctherm_softc *sc; 481ef2ee5d0SMichal Meloun int val; 482ef2ee5d0SMichal Meloun int rv; 483ef2ee5d0SMichal Meloun int id; 484ef2ee5d0SMichal Meloun 485ef2ee5d0SMichal Meloun /* Write request */ 486ef2ee5d0SMichal Meloun if (req->newptr != NULL) 487ef2ee5d0SMichal Meloun return (EINVAL); 488ef2ee5d0SMichal Meloun 489ef2ee5d0SMichal Meloun sc = arg1; 490ef2ee5d0SMichal Meloun id = arg2; 491ef2ee5d0SMichal Meloun 492ef2ee5d0SMichal Meloun if (id >= sc->ntsensors) 493ef2ee5d0SMichal Meloun return (ERANGE); 494ef2ee5d0SMichal Meloun rv = soctherm_read_temp(sc, sc->tsensors + id, &val); 495ef2ee5d0SMichal Meloun if (rv != 0) 496ef2ee5d0SMichal Meloun return (rv); 497ef2ee5d0SMichal Meloun 498ef2ee5d0SMichal Meloun val = val / 100; 499ef2ee5d0SMichal Meloun val += 2731; 500ef2ee5d0SMichal Meloun rv = sysctl_handle_int(oidp, &val, 0, req); 501ef2ee5d0SMichal Meloun return (rv); 502ef2ee5d0SMichal Meloun } 503ef2ee5d0SMichal Meloun 504ef2ee5d0SMichal Meloun static int 505ef2ee5d0SMichal Meloun soctherm_init_sysctl(struct soctherm_softc *sc) 506ef2ee5d0SMichal Meloun { 507ef2ee5d0SMichal Meloun int i; 508ef2ee5d0SMichal Meloun struct sysctl_oid *oid, *tmp; 509ef2ee5d0SMichal Meloun 510ef2ee5d0SMichal Meloun sysctl_ctx_init(&soctherm_sysctl_ctx); 511ef2ee5d0SMichal Meloun /* create node for hw.temp */ 512ef2ee5d0SMichal Meloun oid = SYSCTL_ADD_NODE(&soctherm_sysctl_ctx, 513ef2ee5d0SMichal Meloun SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, "temperature", 514ef2ee5d0SMichal Meloun CTLFLAG_RD, NULL, ""); 515ef2ee5d0SMichal Meloun if (oid == NULL) 516ef2ee5d0SMichal Meloun return (ENXIO); 517ef2ee5d0SMichal Meloun 518ef2ee5d0SMichal Meloun /* Add sensors */ 519ef2ee5d0SMichal Meloun for (i = sc->ntsensors - 1; i >= 0; i--) { 520ef2ee5d0SMichal Meloun tmp = SYSCTL_ADD_PROC(&soctherm_sysctl_ctx, 521ef2ee5d0SMichal Meloun SYSCTL_CHILDREN(oid), OID_AUTO, sc->tsensors[i].name, 522ef2ee5d0SMichal Meloun CTLTYPE_INT | CTLFLAG_RD, sc, i, 523ef2ee5d0SMichal Meloun soctherm_sysctl_temperature, "IK", "SoC Temperature"); 524ef2ee5d0SMichal Meloun if (tmp == NULL) 525ef2ee5d0SMichal Meloun return (ENXIO); 526ef2ee5d0SMichal Meloun } 527ef2ee5d0SMichal Meloun 528ef2ee5d0SMichal Meloun return (0); 529ef2ee5d0SMichal Meloun } 530ef2ee5d0SMichal Meloun 531ef2ee5d0SMichal Meloun static int 532ef2ee5d0SMichal Meloun soctherm_probe(device_t dev) 533ef2ee5d0SMichal Meloun { 534ef2ee5d0SMichal Meloun 535ef2ee5d0SMichal Meloun if (!ofw_bus_status_okay(dev)) 536ef2ee5d0SMichal Meloun return (ENXIO); 537ef2ee5d0SMichal Meloun 538ef2ee5d0SMichal Meloun if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 539ef2ee5d0SMichal Meloun return (ENXIO); 540ef2ee5d0SMichal Meloun 541ef2ee5d0SMichal Meloun device_set_desc(dev, "Tegra temperature sensors"); 542ef2ee5d0SMichal Meloun return (BUS_PROBE_DEFAULT); 543ef2ee5d0SMichal Meloun } 544ef2ee5d0SMichal Meloun 545ef2ee5d0SMichal Meloun static int 546ef2ee5d0SMichal Meloun soctherm_attach(device_t dev) 547ef2ee5d0SMichal Meloun { 548ef2ee5d0SMichal Meloun struct soctherm_softc *sc; 549ef2ee5d0SMichal Meloun phandle_t node; 550ef2ee5d0SMichal Meloun int i, rid, rv; 551ef2ee5d0SMichal Meloun struct soctherm_shared_cal shared_calib; 552ef2ee5d0SMichal Meloun 553ef2ee5d0SMichal Meloun sc = device_get_softc(dev); 554ef2ee5d0SMichal Meloun sc->dev = dev; 555ef2ee5d0SMichal Meloun node = ofw_bus_get_node(sc->dev); 556ef2ee5d0SMichal Meloun 557ef2ee5d0SMichal Meloun rid = 0; 558ef2ee5d0SMichal Meloun sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 559ef2ee5d0SMichal Meloun RF_ACTIVE); 560ef2ee5d0SMichal Meloun if (sc->mem_res == NULL) { 561ef2ee5d0SMichal Meloun device_printf(dev, "Cannot allocate memory resources\n"); 562ef2ee5d0SMichal Meloun goto fail; 563ef2ee5d0SMichal Meloun } 564ef2ee5d0SMichal Meloun 565ef2ee5d0SMichal Meloun rid = 0; 566ef2ee5d0SMichal Meloun sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 567ef2ee5d0SMichal Meloun if (sc->irq_res == NULL) { 568ef2ee5d0SMichal Meloun device_printf(dev, "Cannot allocate IRQ resources\n"); 569ef2ee5d0SMichal Meloun goto fail; 570ef2ee5d0SMichal Meloun } 571ef2ee5d0SMichal Meloun 572ef2ee5d0SMichal Meloun /* 573ef2ee5d0SMichal Meloun if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 574ef2ee5d0SMichal Meloun soctherm_intr, NULL, sc, &sc->irq_ih))) { 575ef2ee5d0SMichal Meloun device_printf(dev, 576ef2ee5d0SMichal Meloun "WARNING: unable to register interrupt handler\n"); 577ef2ee5d0SMichal Meloun goto fail; 578ef2ee5d0SMichal Meloun } 579ef2ee5d0SMichal Meloun */ 580ef2ee5d0SMichal Meloun 581ef2ee5d0SMichal Meloun /* OWF resources */ 582*dac93553SMichal Meloun rv = hwreset_get_by_ofw_name(dev, 0, "soctherm", &sc->reset); 583ef2ee5d0SMichal Meloun if (rv != 0) { 584ef2ee5d0SMichal Meloun device_printf(dev, "Cannot get fuse reset\n"); 585ef2ee5d0SMichal Meloun goto fail; 586ef2ee5d0SMichal Meloun } 587*dac93553SMichal Meloun rv = clk_get_by_ofw_name(dev, 0, "tsensor", &sc->tsensor_clk); 588ef2ee5d0SMichal Meloun if (rv != 0) { 589ef2ee5d0SMichal Meloun device_printf(dev, "Cannot get 'tsensor' clock: %d\n", rv); 590ef2ee5d0SMichal Meloun goto fail; 591ef2ee5d0SMichal Meloun } 592*dac93553SMichal Meloun rv = clk_get_by_ofw_name(dev, 0, "soctherm", &sc->soctherm_clk); 593ef2ee5d0SMichal Meloun if (rv != 0) { 594ef2ee5d0SMichal Meloun device_printf(dev, "Cannot get 'soctherm' clock: %d\n", rv); 595ef2ee5d0SMichal Meloun goto fail; 596ef2ee5d0SMichal Meloun } 597ef2ee5d0SMichal Meloun 598ef2ee5d0SMichal Meloun rv = hwreset_assert(sc->reset); 599ef2ee5d0SMichal Meloun if (rv != 0) { 600ef2ee5d0SMichal Meloun device_printf(dev, "Cannot assert reset\n"); 601ef2ee5d0SMichal Meloun goto fail; 602ef2ee5d0SMichal Meloun } 603ef2ee5d0SMichal Meloun rv = clk_enable(sc->tsensor_clk); 604ef2ee5d0SMichal Meloun if (rv != 0) { 605ef2ee5d0SMichal Meloun device_printf(dev, "Cannot enable 'tsensor' clock: %d\n", rv); 606ef2ee5d0SMichal Meloun goto fail; 607ef2ee5d0SMichal Meloun } 608ef2ee5d0SMichal Meloun rv = clk_enable(sc->soctherm_clk); 609ef2ee5d0SMichal Meloun if (rv != 0) { 610ef2ee5d0SMichal Meloun device_printf(dev, "Cannot enable 'soctherm' clock: %d\n", rv); 611ef2ee5d0SMichal Meloun goto fail; 612ef2ee5d0SMichal Meloun } 613ef2ee5d0SMichal Meloun rv = hwreset_deassert(sc->reset); 614ef2ee5d0SMichal Meloun if (rv != 0) { 615ef2ee5d0SMichal Meloun device_printf(dev, "Cannot clear reset\n"); 616ef2ee5d0SMichal Meloun goto fail; 617ef2ee5d0SMichal Meloun } 618ef2ee5d0SMichal Meloun 619ef2ee5d0SMichal Meloun /* Tegra 124 */ 620ef2ee5d0SMichal Meloun sc->tsensors = t124_tsensors; 621ef2ee5d0SMichal Meloun sc->ntsensors = nitems(t124_tsensors); 622ef2ee5d0SMichal Meloun get_shared_cal(sc, &shared_calib); 623ef2ee5d0SMichal Meloun 624ef2ee5d0SMichal Meloun WR4(sc, TSENSOR_PDIV, TSENSOR_PDIV_T124); 625ef2ee5d0SMichal Meloun WR4(sc, TSENSOR_HOTSPOT_OFF, TSENSOR_HOTSPOT_OFF_T124); 626ef2ee5d0SMichal Meloun 627ef2ee5d0SMichal Meloun for (i = 0; i < sc->ntsensors; i++) 628ef2ee5d0SMichal Meloun soctherm_init_tsensor(sc, sc->tsensors + i, &shared_calib); 629ef2ee5d0SMichal Meloun 630ef2ee5d0SMichal Meloun rv = soctherm_init_sysctl(sc); 631ef2ee5d0SMichal Meloun if (rv != 0) { 632ef2ee5d0SMichal Meloun device_printf(sc->dev, "Cannot initialize sysctls\n"); 633ef2ee5d0SMichal Meloun goto fail; 634ef2ee5d0SMichal Meloun } 635ef2ee5d0SMichal Meloun 636ef2ee5d0SMichal Meloun OF_device_register_xref(OF_xref_from_node(node), dev); 637ef2ee5d0SMichal Meloun return (bus_generic_attach(dev)); 638ef2ee5d0SMichal Meloun 639ef2ee5d0SMichal Meloun fail: 640ef2ee5d0SMichal Meloun if (sc->irq_ih != NULL) 641ef2ee5d0SMichal Meloun bus_teardown_intr(dev, sc->irq_res, sc->irq_ih); 642ef2ee5d0SMichal Meloun sysctl_ctx_free(&soctherm_sysctl_ctx); 643ef2ee5d0SMichal Meloun if (sc->tsensor_clk != NULL) 644ef2ee5d0SMichal Meloun clk_release(sc->tsensor_clk); 645ef2ee5d0SMichal Meloun if (sc->soctherm_clk != NULL) 646ef2ee5d0SMichal Meloun clk_release(sc->soctherm_clk); 647ef2ee5d0SMichal Meloun if (sc->reset != NULL) 648ef2ee5d0SMichal Meloun hwreset_release(sc->reset); 649ef2ee5d0SMichal Meloun if (sc->irq_res != NULL) 650ef2ee5d0SMichal Meloun bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 651ef2ee5d0SMichal Meloun if (sc->mem_res != NULL) 652ef2ee5d0SMichal Meloun bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 653ef2ee5d0SMichal Meloun 654ef2ee5d0SMichal Meloun return (ENXIO); 655ef2ee5d0SMichal Meloun } 656ef2ee5d0SMichal Meloun 657ef2ee5d0SMichal Meloun static int 658ef2ee5d0SMichal Meloun soctherm_detach(device_t dev) 659ef2ee5d0SMichal Meloun { 660ef2ee5d0SMichal Meloun struct soctherm_softc *sc; 661ef2ee5d0SMichal Meloun sc = device_get_softc(dev); 662ef2ee5d0SMichal Meloun 663ef2ee5d0SMichal Meloun if (sc->irq_ih != NULL) 664ef2ee5d0SMichal Meloun bus_teardown_intr(dev, sc->irq_res, sc->irq_ih); 665ef2ee5d0SMichal Meloun sysctl_ctx_free(&soctherm_sysctl_ctx); 666ef2ee5d0SMichal Meloun if (sc->tsensor_clk != NULL) 667ef2ee5d0SMichal Meloun clk_release(sc->tsensor_clk); 668ef2ee5d0SMichal Meloun if (sc->soctherm_clk != NULL) 669ef2ee5d0SMichal Meloun clk_release(sc->soctherm_clk); 670ef2ee5d0SMichal Meloun if (sc->reset != NULL) 671ef2ee5d0SMichal Meloun hwreset_release(sc->reset); 672ef2ee5d0SMichal Meloun if (sc->irq_res != NULL) 673ef2ee5d0SMichal Meloun bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 674ef2ee5d0SMichal Meloun if (sc->mem_res != NULL) 675ef2ee5d0SMichal Meloun bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 676ef2ee5d0SMichal Meloun 677ef2ee5d0SMichal Meloun return (ENXIO); 678ef2ee5d0SMichal Meloun } 679ef2ee5d0SMichal Meloun 680ef2ee5d0SMichal Meloun static device_method_t tegra_soctherm_methods[] = { 681ef2ee5d0SMichal Meloun /* Device interface */ 682ef2ee5d0SMichal Meloun DEVMETHOD(device_probe, soctherm_probe), 683ef2ee5d0SMichal Meloun DEVMETHOD(device_attach, soctherm_attach), 684ef2ee5d0SMichal Meloun DEVMETHOD(device_detach, soctherm_detach), 685ef2ee5d0SMichal Meloun 686ef2ee5d0SMichal Meloun /* SOCTHERM interface */ 687ef2ee5d0SMichal Meloun DEVMETHOD(tegra_soctherm_get_temperature, soctherm_get_temp), 688ef2ee5d0SMichal Meloun 689ef2ee5d0SMichal Meloun DEVMETHOD_END 690ef2ee5d0SMichal Meloun }; 691ef2ee5d0SMichal Meloun 692ef2ee5d0SMichal Meloun static devclass_t tegra_soctherm_devclass; 693ef2ee5d0SMichal Meloun DEFINE_CLASS_0(tegra_soctherm, tegra_soctherm_driver, tegra_soctherm_methods, 694ef2ee5d0SMichal Meloun sizeof(struct soctherm_softc)); 695ef2ee5d0SMichal Meloun EARLY_DRIVER_MODULE(tegra_soctherm, simplebus, tegra_soctherm_driver, 696ef2ee5d0SMichal Meloun tegra_soctherm_devclass, 0, 0, 79); 697