1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * I2C driver for Tegra SoCs. 30 */ 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/limits.h> 36 #include <sys/module.h> 37 #include <sys/resource.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <sys/rman.h> 42 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 46 #include <dev/clk/clk.h> 47 #include <dev/hwreset/hwreset.h> 48 #include <dev/iicbus/iiconf.h> 49 #include <dev/iicbus/iicbus.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include "iicbus_if.h" 54 55 #define I2C_CNFG 0x000 56 #define I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT (1 << 15) 57 #define I2C_CNFG_DEBOUNCE_CNT(x) (((x) & 0x07) << 12) 58 #define I2C_CNFG_NEW_MASTER_FSM (1 << 11) 59 #define I2C_CNFG_PACKET_MODE_EN (1 << 10) 60 #define I2C_CNFG_SEND (1 << 9) 61 #define I2C_CNFG_NOACK (1 << 8) 62 #define I2C_CNFG_CMD2 (1 << 7) 63 #define I2C_CNFG_CMD1 (1 << 6) 64 #define I2C_CNFG_START (1 << 5) 65 #define I2C_CNFG_SLV2 (1 << 4) 66 #define I2C_CNFG_LENGTH_SHIFT 1 67 #define I2C_CNFG_LENGTH_MASK 0x7 68 #define I2C_CNFG_A_MOD (1 << 0) 69 70 #define I2C_CMD_ADDR0 0x004 71 #define I2C_CMD_ADDR1 0x008 72 #define I2C_CMD_DATA1 0x00c 73 #define I2C_CMD_DATA2 0x010 74 #define I2C_STATUS 0x01c 75 #define I2C_SL_CNFG 0x020 76 #define I2C_SL_RCVD 0x024 77 #define I2C_SL_STATUS 0x028 78 #define I2C_SL_ADDR1 0x02c 79 #define I2C_SL_ADDR2 0x030 80 #define I2C_TLOW_SEXT 0x034 81 #define I2C_SL_DELAY_COUNT 0x03c 82 #define I2C_SL_INT_MASK 0x040 83 #define I2C_SL_INT_SOURCE 0x044 84 #define I2C_SL_INT_SET 0x048 85 #define I2C_TX_PACKET_FIFO 0x050 86 #define I2C_RX_FIFO 0x054 87 #define I2C_PACKET_TRANSFER_STATUS 0x058 88 #define I2C_FIFO_CONTROL 0x05c 89 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_TRIG(x) (((x) & 0x07) << 13) 90 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_TRIG(x) (((x) & 0x07) << 10) 91 #define I2C_FIFO_CONTROL_SLV_TX_FIFO_FLUSH (1 << 9) 92 #define I2C_FIFO_CONTROL_SLV_RX_FIFO_FLUSH (1 << 8) 93 #define I2C_FIFO_CONTROL_TX_FIFO_TRIG(x) (((x) & 0x07) << 5) 94 #define I2C_FIFO_CONTROL_RX_FIFO_TRIG(x) (((x) & 0x07) << 2) 95 #define I2C_FIFO_CONTROL_TX_FIFO_FLUSH (1 << 1) 96 #define I2C_FIFO_CONTROL_RX_FIFO_FLUSH (1 << 0) 97 98 #define I2C_FIFO_STATUS 0x060 99 #define I2C_FIFO_STATUS_SLV_XFER_ERR_REASON (1 << 25) 100 #define I2C_FIFO_STATUS_TX_FIFO_SLV_EMPTY_CNT(x) (((x) >> 20) & 0xF) 101 #define I2C_FIFO_STATUS_RX_FIFO_SLV_FULL_CNT(x) (((x) >> 16) & 0xF) 102 #define I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(x) (((x) >> 4) & 0xF) 103 #define I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(x) (((x) >> 0) & 0xF) 104 105 #define I2C_INTERRUPT_MASK_REGISTER 0x064 106 #define I2C_INTERRUPT_STATUS_REGISTER 0x068 107 #define I2C_INT_SLV_ACK_WITHHELD (1 << 28) 108 #define I2C_INT_SLV_RD2WR (1 << 27) 109 #define I2C_INT_SLV_WR2RD (1 << 26) 110 #define I2C_INT_SLV_PKT_XFER_ERR (1 << 25) 111 #define I2C_INT_SLV_TX_BUFFER_REQ (1 << 24) 112 #define I2C_INT_SLV_RX_BUFFER_FILLED (1 << 23) 113 #define I2C_INT_SLV_PACKET_XFER_COMPLETE (1 << 22) 114 #define I2C_INT_SLV_TFIFO_OVF (1 << 21) 115 #define I2C_INT_SLV_RFIFO_UNF (1 << 20) 116 #define I2C_INT_SLV_TFIFO_DATA_REQ (1 << 17) 117 #define I2C_INT_SLV_RFIFO_DATA_REQ (1 << 16) 118 #define I2C_INT_BUS_CLEAR_DONE (1 << 11) 119 #define I2C_INT_TLOW_MEXT_TIMEOUT (1 << 10) 120 #define I2C_INT_TLOW_SEXT_TIMEOUT (1 << 9) 121 #define I2C_INT_TIMEOUT (1 << 8) 122 #define I2C_INT_PACKET_XFER_COMPLETE (1 << 7) 123 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1 << 6) 124 #define I2C_INT_TFIFO_OVR (1 << 5) 125 #define I2C_INT_RFIFO_UNF (1 << 4) 126 #define I2C_INT_NOACK (1 << 3) 127 #define I2C_INT_ARB_LOST (1 << 2) 128 #define I2C_INT_TFIFO_DATA_REQ (1 << 1) 129 #define I2C_INT_RFIFO_DATA_REQ (1 << 0) 130 #define I2C_ERROR_MASK (I2C_INT_ARB_LOST | I2C_INT_NOACK | \ 131 I2C_INT_RFIFO_UNF | I2C_INT_TFIFO_OVR) 132 133 #define I2C_CLK_DIVISOR 0x06c 134 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 135 #define I2C_CLK_DIVISOR_STD_FAST_MODE_MASK 0xffff 136 #define I2C_CLK_DIVISOR_HSMODE_SHIFT 0 137 #define I2C_CLK_DIVISOR_HSMODE_MASK 0xffff 138 #define I2C_INTERRUPT_SOURCE_REGISTER 0x070 139 #define I2C_INTERRUPT_SET_REGISTER 0x074 140 #define I2C_SLV_TX_PACKET_FIFO 0x07c 141 #define I2C_SLV_PACKET_STATUS 0x080 142 #define I2C_BUS_CLEAR_CONFIG 0x084 143 #define I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(x) (((x) & 0xFF) << 16) 144 #define I2C_BUS_CLEAR_CONFIG_BC_STOP_COND (1 << 2) 145 #define I2C_BUS_CLEAR_CONFIG_BC_TERMINATE (1 << 1) 146 #define I2C_BUS_CLEAR_CONFIG_BC_ENABLE (1 << 0) 147 148 #define I2C_BUS_CLEAR_STATUS 0x088 149 #define I2C_BUS_CLEAR_STATUS_BC_STATUS (1 << 0) 150 151 #define I2C_CONFIG_LOAD 0x08c 152 #define I2C_CONFIG_LOAD_TIMEOUT_CONFIG_LOAD (1 << 2) 153 #define I2C_CONFIG_LOAD_SLV_CONFIG_LOAD (1 << 1) 154 #define I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD (1 << 0) 155 156 #define I2C_INTERFACE_TIMING_0 0x094 157 #define I2C_INTERFACE_TIMING_1 0x098 158 #define I2C_HS_INTERFACE_TIMING_0 0x09c 159 #define I2C_HS_INTERFACE_TIMING_1 0x0a0 160 161 /* Protocol header 0 */ 162 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 163 #define PACKET_HEADER0_HEADER_SIZE_MASK 0x3 164 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 165 #define PACKET_HEADER0_PACKET_ID_MASK 0xff 166 #define PACKET_HEADER0_CONT_ID_SHIFT 12 167 #define PACKET_HEADER0_CONT_ID_MASK 0xf 168 #define PACKET_HEADER0_PROTOCOL_I2C (1 << 4) 169 #define PACKET_HEADER0_TYPE_SHIFT 0 170 #define PACKET_HEADER0_TYPE_MASK 0x7 171 172 /* I2C header */ 173 #define I2C_HEADER_HIGHSPEED_MODE (1 << 22) 174 #define I2C_HEADER_CONT_ON_NAK (1 << 21) 175 #define I2C_HEADER_SEND_START_BYTE (1 << 20) 176 #define I2C_HEADER_READ (1 << 19) 177 #define I2C_HEADER_10BIT_ADDR (1 << 18) 178 #define I2C_HEADER_IE_ENABLE (1 << 17) 179 #define I2C_HEADER_REPEAT_START (1 << 16) 180 #define I2C_HEADER_CONTINUE_XFER (1 << 15) 181 #define I2C_HEADER_MASTER_ADDR_SHIFT 12 182 #define I2C_HEADER_MASTER_ADDR_MASK 0x7 183 #define I2C_HEADER_SLAVE_ADDR_SHIFT 0 184 #define I2C_HEADER_SLAVE_ADDR_MASK 0x3ff 185 186 #define I2C_CLK_DIVISOR_STD_FAST_MODE 0x19 187 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8 188 189 #define I2C_REQUEST_TIMEOUT (5 * hz) 190 191 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 192 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 193 194 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) 195 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 196 #define SLEEP(_sc, timeout) \ 197 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", timeout); 198 #define LOCK_INIT(_sc) \ 199 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_i2c", MTX_DEF) 200 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 201 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 202 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 203 204 static struct ofw_compat_data compat_data[] = { 205 {"nvidia,tegra124-i2c", 1}, 206 {"nvidia,tegra210-i2c", 1}, 207 {NULL, 0} 208 }; 209 enum tegra_i2c_xfer_type { 210 XFER_STOP, /* Send stop condition after xfer */ 211 XFER_REPEAT_START, /* Send repeated start after xfer */ 212 XFER_CONTINUE /* Don't send nothing */ 213 } ; 214 215 struct tegra_i2c_softc { 216 device_t dev; 217 struct mtx mtx; 218 219 struct resource *mem_res; 220 struct resource *irq_res; 221 void *irq_h; 222 223 device_t iicbus; 224 clk_t clk; 225 hwreset_t reset; 226 uint32_t core_freq; 227 uint32_t bus_freq; 228 int bus_inuse; 229 230 struct iic_msg *msg; 231 int msg_idx; 232 uint32_t bus_err; 233 int done; 234 }; 235 236 static int 237 tegra_i2c_flush_fifo(struct tegra_i2c_softc *sc) 238 { 239 int timeout; 240 uint32_t reg; 241 242 reg = RD4(sc, I2C_FIFO_CONTROL); 243 reg |= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 244 WR4(sc, I2C_FIFO_CONTROL, reg); 245 246 timeout = 10; 247 while (timeout > 0) { 248 reg = RD4(sc, I2C_FIFO_CONTROL); 249 reg &= I2C_FIFO_CONTROL_TX_FIFO_FLUSH | 250 I2C_FIFO_CONTROL_RX_FIFO_FLUSH; 251 if (reg == 0) 252 break; 253 DELAY(10); 254 } 255 if (timeout <= 0) { 256 device_printf(sc->dev, "FIFO flush timedout\n"); 257 return (ETIMEDOUT); 258 } 259 return (0); 260 } 261 262 static void 263 tegra_i2c_setup_clk(struct tegra_i2c_softc *sc, int clk_freq) 264 { 265 int div; 266 267 div = ((sc->core_freq / clk_freq) / 10) - 1; 268 if ((sc->core_freq / (10 * (div + 1))) > clk_freq) 269 div++; 270 if (div > 65535) 271 div = 65535; 272 WR4(sc, I2C_CLK_DIVISOR, 273 (1 << I2C_CLK_DIVISOR_HSMODE_SHIFT) | 274 (div << I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT)); 275 } 276 277 static void 278 tegra_i2c_bus_clear(struct tegra_i2c_softc *sc) 279 { 280 int timeout; 281 uint32_t reg, status; 282 283 WR4(sc, I2C_BUS_CLEAR_CONFIG, 284 I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD(18) | 285 I2C_BUS_CLEAR_CONFIG_BC_STOP_COND | 286 I2C_BUS_CLEAR_CONFIG_BC_TERMINATE); 287 288 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD); 289 for (timeout = 1000; timeout > 0; timeout--) { 290 if (RD4(sc, I2C_CONFIG_LOAD) == 0) 291 break; 292 DELAY(10); 293 } 294 if (timeout <= 0) 295 device_printf(sc->dev, "config load timeouted\n"); 296 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); 297 reg |= I2C_BUS_CLEAR_CONFIG_BC_ENABLE; 298 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg); 299 300 for (timeout = 1000; timeout > 0; timeout--) { 301 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & 302 I2C_BUS_CLEAR_CONFIG_BC_ENABLE) == 0) 303 break; 304 DELAY(10); 305 } 306 if (timeout <= 0) 307 device_printf(sc->dev, "bus clear timeouted\n"); 308 309 status = RD4(sc, I2C_BUS_CLEAR_STATUS); 310 if ((status & I2C_BUS_CLEAR_STATUS_BC_STATUS) == 0) 311 device_printf(sc->dev, "bus clear failed\n"); 312 } 313 314 static int 315 tegra_i2c_hw_init(struct tegra_i2c_softc *sc) 316 { 317 int rv, timeout; 318 319 /* Reset the core. */ 320 rv = hwreset_assert(sc->reset); 321 if (rv != 0) { 322 device_printf(sc->dev, "Cannot assert reset\n"); 323 return (rv); 324 } 325 DELAY(10); 326 rv = hwreset_deassert(sc->reset); 327 if (rv != 0) { 328 device_printf(sc->dev, "Cannot clear reset\n"); 329 return (rv); 330 } 331 332 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 333 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF); 334 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 335 I2C_CNFG_DEBOUNCE_CNT(2)); 336 337 tegra_i2c_setup_clk(sc, sc->bus_freq); 338 339 WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) | 340 I2C_FIFO_CONTROL_RX_FIFO_TRIG(0)); 341 342 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD); 343 for (timeout = 1000; timeout > 0; timeout--) { 344 if (RD4(sc, I2C_CONFIG_LOAD) == 0) 345 break; 346 DELAY(10); 347 } 348 if (timeout <= 0) 349 device_printf(sc->dev, "config load timeouted\n"); 350 351 tegra_i2c_bus_clear(sc); 352 return (0); 353 } 354 355 static int 356 tegra_i2c_tx(struct tegra_i2c_softc *sc) 357 { 358 uint32_t reg; 359 int cnt, i; 360 361 if (sc->msg_idx >= sc->msg->len) 362 panic("Invalid call to tegra_i2c_tx\n"); 363 364 while(sc->msg_idx < sc->msg->len) { 365 reg = RD4(sc, I2C_FIFO_STATUS); 366 if (I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT(reg) == 0) 367 break; 368 cnt = min(4, sc->msg->len - sc->msg_idx); 369 reg = 0; 370 for (i = 0; i < cnt; i++) { 371 reg |= sc->msg->buf[sc->msg_idx] << (i * 8); 372 sc->msg_idx++; 373 } 374 WR4(sc, I2C_TX_PACKET_FIFO, reg); 375 } 376 if (sc->msg_idx >= sc->msg->len) 377 return (0); 378 return (sc->msg->len - sc->msg_idx - 1); 379 } 380 381 static int 382 tegra_i2c_rx(struct tegra_i2c_softc *sc) 383 { 384 uint32_t reg; 385 int cnt, i; 386 387 if (sc->msg_idx >= sc->msg->len) 388 panic("Invalid call to tegra_i2c_rx\n"); 389 390 while(sc->msg_idx < sc->msg->len) { 391 reg = RD4(sc, I2C_FIFO_STATUS); 392 if (I2C_FIFO_STATUS_RX_FIFO_FULL_CNT(reg) == 0) 393 break; 394 cnt = min(4, sc->msg->len - sc->msg_idx); 395 reg = RD4(sc, I2C_RX_FIFO); 396 for (i = 0; i < cnt; i++) { 397 sc->msg->buf[sc->msg_idx] = (reg >> (i * 8)) & 0xFF; 398 sc->msg_idx++; 399 } 400 } 401 402 if (sc->msg_idx >= sc->msg->len) 403 return (0); 404 return (sc->msg->len - sc->msg_idx - 1); 405 } 406 407 static void 408 tegra_i2c_intr(void *arg) 409 { 410 struct tegra_i2c_softc *sc; 411 uint32_t status, reg; 412 int rv; 413 414 sc = (struct tegra_i2c_softc *)arg; 415 416 LOCK(sc); 417 status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER); 418 if (sc->msg == NULL) { 419 /* Unexpected interrupt - disable FIFOs, clear reset. */ 420 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 421 reg &= ~I2C_INT_TFIFO_DATA_REQ; 422 reg &= ~I2C_INT_RFIFO_DATA_REQ; 423 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 424 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status); 425 UNLOCK(sc); 426 return; 427 } 428 429 if ((status & I2C_ERROR_MASK) != 0) { 430 if (status & I2C_INT_NOACK) 431 sc->bus_err = IIC_ENOACK; 432 if (status & I2C_INT_ARB_LOST) 433 sc->bus_err = IIC_EBUSERR; 434 if ((status & I2C_INT_TFIFO_OVR) || 435 (status & I2C_INT_RFIFO_UNF)) 436 sc->bus_err = IIC_EBUSERR; 437 sc->done = 1; 438 } else if ((status & I2C_INT_RFIFO_DATA_REQ) && 439 (sc->msg != NULL) && (sc->msg->flags & IIC_M_RD)) { 440 rv = tegra_i2c_rx(sc); 441 if (rv == 0) { 442 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 443 reg &= ~I2C_INT_RFIFO_DATA_REQ; 444 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 445 } 446 } else if ((status & I2C_INT_TFIFO_DATA_REQ) && 447 (sc->msg != NULL) && !(sc->msg->flags & IIC_M_RD)) { 448 rv = tegra_i2c_tx(sc); 449 if (rv == 0) { 450 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 451 reg &= ~I2C_INT_TFIFO_DATA_REQ; 452 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 453 } 454 } else if ((status & I2C_INT_RFIFO_DATA_REQ) || 455 (status & I2C_INT_TFIFO_DATA_REQ)) { 456 device_printf(sc->dev, "Unexpected data interrupt: 0x%08X\n", 457 status); 458 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); 459 reg &= ~I2C_INT_TFIFO_DATA_REQ; 460 reg &= ~I2C_INT_RFIFO_DATA_REQ; 461 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, reg); 462 } 463 if (status & I2C_INT_PACKET_XFER_COMPLETE) 464 sc->done = 1; 465 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, status); 466 if (sc->done) { 467 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 468 wakeup(&(sc->done)); 469 } 470 UNLOCK(sc); 471 } 472 473 static void 474 tegra_i2c_start_msg(struct tegra_i2c_softc *sc, struct iic_msg *msg, 475 enum tegra_i2c_xfer_type xtype) 476 { 477 uint32_t tmp, mask; 478 479 /* Packet header. */ 480 tmp = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 481 PACKET_HEADER0_PROTOCOL_I2C | 482 (1 << PACKET_HEADER0_CONT_ID_SHIFT) | 483 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 484 WR4(sc, I2C_TX_PACKET_FIFO, tmp); 485 486 /* Packet size. */ 487 WR4(sc, I2C_TX_PACKET_FIFO, msg->len - 1); 488 489 /* I2C header. */ 490 tmp = I2C_HEADER_IE_ENABLE; 491 if (xtype == XFER_CONTINUE) 492 tmp |= I2C_HEADER_CONTINUE_XFER; 493 else if (xtype == XFER_REPEAT_START) 494 tmp |= I2C_HEADER_REPEAT_START; 495 tmp |= msg->slave << I2C_HEADER_SLAVE_ADDR_SHIFT; 496 if (msg->flags & IIC_M_RD) { 497 tmp |= I2C_HEADER_READ; 498 tmp |= 1 << I2C_HEADER_SLAVE_ADDR_SHIFT; 499 } else 500 tmp &= ~(1 << I2C_HEADER_SLAVE_ADDR_SHIFT); 501 502 WR4(sc, I2C_TX_PACKET_FIFO, tmp); 503 504 /* Interrupt mask. */ 505 mask = I2C_INT_NOACK | I2C_INT_ARB_LOST | I2C_INT_PACKET_XFER_COMPLETE; 506 if (msg->flags & IIC_M_RD) 507 mask |= I2C_INT_RFIFO_DATA_REQ; 508 else 509 mask |= I2C_INT_TFIFO_DATA_REQ; 510 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, mask); 511 } 512 513 static int 514 tegra_i2c_poll(struct tegra_i2c_softc *sc) 515 { 516 int timeout; 517 518 for(timeout = 10000; timeout > 0; timeout--) { 519 UNLOCK(sc); 520 tegra_i2c_intr(sc); 521 LOCK(sc); 522 if (sc->done != 0) 523 break; 524 DELAY(1); 525 } 526 if (timeout <= 0) 527 return (ETIMEDOUT); 528 return (0); 529 } 530 531 static int 532 tegra_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 533 { 534 int rv, i; 535 struct tegra_i2c_softc *sc; 536 enum tegra_i2c_xfer_type xtype; 537 538 sc = device_get_softc(dev); 539 LOCK(sc); 540 541 /* Get the bus. */ 542 while (sc->bus_inuse == 1) 543 SLEEP(sc, 0); 544 sc->bus_inuse = 1; 545 546 rv = 0; 547 for (i = 0; i < nmsgs; i++) { 548 sc->msg = &msgs[i]; 549 sc->msg_idx = 0; 550 sc->bus_err = 0; 551 sc->done = 0; 552 /* Check for valid parameters. */ 553 if (sc->msg == NULL || sc->msg->buf == NULL || 554 sc->msg->len == 0) { 555 rv = EINVAL; 556 break; 557 } 558 559 /* Get flags for next transfer. */ 560 if (i == (nmsgs - 1)) { 561 if (msgs[i].flags & IIC_M_NOSTOP) 562 xtype = XFER_CONTINUE; 563 else 564 xtype = XFER_STOP; 565 } else { 566 if (msgs[i + 1].flags & IIC_M_NOSTART) 567 xtype = XFER_CONTINUE; 568 else 569 xtype = XFER_REPEAT_START; 570 } 571 tegra_i2c_start_msg(sc, sc->msg, xtype); 572 if (cold) 573 rv = tegra_i2c_poll(sc); 574 else 575 rv = msleep(&sc->done, &sc->mtx, PZERO, "iic", 576 I2C_REQUEST_TIMEOUT); 577 578 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); 579 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF); 580 if (rv == 0) 581 rv = sc->bus_err; 582 if (rv != 0) 583 break; 584 } 585 586 if (rv != 0) { 587 tegra_i2c_hw_init(sc); 588 tegra_i2c_flush_fifo(sc); 589 } 590 591 sc->msg = NULL; 592 sc->msg_idx = 0; 593 sc->bus_err = 0; 594 sc->done = 0; 595 596 /* Wake up the processes that are waiting for the bus. */ 597 sc->bus_inuse = 0; 598 wakeup(sc); 599 UNLOCK(sc); 600 601 return (rv); 602 } 603 604 static int 605 tegra_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 606 { 607 struct tegra_i2c_softc *sc; 608 int busfreq; 609 610 sc = device_get_softc(dev); 611 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 612 sc = device_get_softc(dev); 613 LOCK(sc); 614 tegra_i2c_setup_clk(sc, busfreq); 615 UNLOCK(sc); 616 return (0); 617 } 618 619 static int 620 tegra_i2c_probe(device_t dev) 621 { 622 if (!ofw_bus_status_okay(dev)) 623 return (ENXIO); 624 625 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 626 return (ENXIO); 627 628 return (BUS_PROBE_DEFAULT); 629 } 630 631 static int 632 tegra_i2c_attach(device_t dev) 633 { 634 int rv, rid; 635 phandle_t node; 636 struct tegra_i2c_softc *sc; 637 uint64_t freq; 638 639 sc = device_get_softc(dev); 640 sc->dev = dev; 641 node = ofw_bus_get_node(dev); 642 643 LOCK_INIT(sc); 644 645 /* Get the memory resource for the register mapping. */ 646 rid = 0; 647 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 648 RF_ACTIVE); 649 if (sc->mem_res == NULL) { 650 device_printf(dev, "Cannot map registers.\n"); 651 rv = ENXIO; 652 goto fail; 653 } 654 655 /* Allocate our IRQ resource. */ 656 rid = 0; 657 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 658 RF_ACTIVE); 659 if (sc->irq_res == NULL) { 660 device_printf(dev, "Cannot allocate interrupt.\n"); 661 rv = ENXIO; 662 goto fail; 663 } 664 665 /* FDT resources. */ 666 rv = clk_get_by_ofw_name(dev, 0, "div-clk", &sc->clk); 667 if (rv != 0) { 668 device_printf(dev, "Cannot get i2c clock: %d\n", rv); 669 goto fail; 670 } 671 rv = hwreset_get_by_ofw_name(sc->dev, 0, "i2c", &sc->reset); 672 if (rv != 0) { 673 device_printf(sc->dev, "Cannot get i2c reset\n"); 674 return (ENXIO); 675 } 676 rv = OF_getencprop(node, "clock-frequency", &sc->bus_freq, 677 sizeof(sc->bus_freq)); 678 if (rv != sizeof(sc->bus_freq)) { 679 sc->bus_freq = 100000; 680 } 681 682 /* Request maximum frequency for I2C block 136MHz (408MHz / 3). */ 683 rv = clk_set_freq(sc->clk, 136000000, CLK_SET_ROUND_DOWN); 684 if (rv != 0) { 685 device_printf(dev, "Cannot set clock frequency\n"); 686 goto fail; 687 } 688 rv = clk_get_freq(sc->clk, &freq); 689 if (rv != 0) { 690 device_printf(dev, "Cannot get clock frequency\n"); 691 goto fail; 692 } 693 sc->core_freq = (uint32_t)freq; 694 695 rv = clk_enable(sc->clk); 696 if (rv != 0) { 697 device_printf(dev, "Cannot enable clock: %d\n", rv); 698 goto fail; 699 } 700 701 /* Init hardware. */ 702 rv = tegra_i2c_hw_init(sc); 703 if (rv) { 704 device_printf(dev, "tegra_i2c_activate failed\n"); 705 goto fail; 706 } 707 708 /* Setup interrupt. */ 709 rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 710 NULL, tegra_i2c_intr, sc, &sc->irq_h); 711 if (rv) { 712 device_printf(dev, "Cannot setup interrupt.\n"); 713 goto fail; 714 } 715 716 /* Attach the iicbus. */ 717 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY); 718 if (sc->iicbus == NULL) { 719 device_printf(dev, "Could not allocate iicbus instance.\n"); 720 rv = ENXIO; 721 goto fail; 722 } 723 724 /* Probe and attach the iicbus. */ 725 return (bus_generic_attach(dev)); 726 727 fail: 728 if (sc->irq_h != NULL) 729 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 730 if (sc->irq_res != NULL) 731 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 732 if (sc->mem_res != NULL) 733 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 734 LOCK_DESTROY(sc); 735 736 return (rv); 737 } 738 739 static int 740 tegra_i2c_detach(device_t dev) 741 { 742 struct tegra_i2c_softc *sc; 743 744 sc = device_get_softc(dev); 745 tegra_i2c_hw_init(sc); 746 if (sc->irq_h != NULL) 747 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 748 if (sc->irq_res != NULL) 749 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 750 if (sc->mem_res != NULL) 751 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 752 753 LOCK_DESTROY(sc); 754 if (sc->iicbus) 755 device_delete_child(dev, sc->iicbus); 756 return (bus_generic_detach(dev)); 757 } 758 759 static phandle_t 760 tegra_i2c_get_node(device_t bus, device_t dev) 761 { 762 763 /* Share controller node with iibus device. */ 764 return (ofw_bus_get_node(bus)); 765 } 766 767 static device_method_t tegra_i2c_methods[] = { 768 /* Device interface */ 769 DEVMETHOD(device_probe, tegra_i2c_probe), 770 DEVMETHOD(device_attach, tegra_i2c_attach), 771 DEVMETHOD(device_detach, tegra_i2c_detach), 772 773 /* Bus interface */ 774 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 775 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 776 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 777 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 778 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 779 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 780 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 781 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 782 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 783 784 /* OFW methods */ 785 DEVMETHOD(ofw_bus_get_node, tegra_i2c_get_node), 786 787 /* iicbus interface */ 788 DEVMETHOD(iicbus_callback, iicbus_null_callback), 789 DEVMETHOD(iicbus_reset, tegra_i2c_iicbus_reset), 790 DEVMETHOD(iicbus_transfer, tegra_i2c_transfer), 791 792 DEVMETHOD_END 793 }; 794 795 static DEFINE_CLASS_0(iichb, tegra_i2c_driver, tegra_i2c_methods, 796 sizeof(struct tegra_i2c_softc)); 797 EARLY_DRIVER_MODULE(tegra_iic, simplebus, tegra_i2c_driver, NULL, NULL, 73); 798