xref: /freebsd/sys/arm/nvidia/tegra_ahci.c (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c)
1 /*-
2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 /*
31  * AHCI driver for Tegra SoCs.
32  */
33 #include <sys/param.h>
34 #include <sys/module.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
43 #include <sys/rman.h>
44 
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 
48 #include <dev/ahci/ahci.h>
49 #include <dev/extres/clk/clk.h>
50 #include <dev/extres/hwreset/hwreset.h>
51 #include <dev/extres/phy/phy.h>
52 #include <dev/extres/regulator/regulator.h>
53 #include <dev/fdt/fdt_pinctrl.h>
54 #include <dev/ofw/ofw_bus.h>
55 #include <dev/ofw/ofw_bus_subr.h>
56 
57 #include <arm/nvidia/tegra_efuse.h>
58 #include <arm/nvidia/tegra_pmc.h>
59 
60 
61 #define	SATA_CONFIGURATION			0x180
62 #define  SATA_CONFIGURATION_CLK_OVERRIDE		(1U << 31)
63 #define	 SATA_CONFIGURATION_EN_FPCI			(1  <<  0)
64 
65 #define	SATA_FPCI_BAR5				0x94
66 #define	 SATA_FPCI_BAR_START(x)				(((x) & 0xFFFFFFF) << 4)
67 #define	 SATA_FPCI_BAR_ACCESS_TYPE			(1 << 0)
68 
69 #define	SATA_INTR_MASK				0x188
70 #define	SATA_INTR_MASK_IP_INT_MASK			(1 << 16)
71 
72 #define	SCFG_OFFSET				0x1000
73 
74 #define	T_SATA0_CFG_1				0x04
75 #define	 T_SATA0_CFG_1_IO_SPACE				(1 << 0)
76 #define	 T_SATA0_CFG_1_MEMORY_SPACE			(1 << 1)
77 #define	 T_SATA0_CFG_1_BUS_MASTER			(1 << 2)
78 #define	 T_SATA0_CFG_1_SERR				(1 << 8)
79 
80 #define	T_SATA0_CFG_9				0x24
81 #define	 T_SATA0_CFG_9_BASE_ADDRESS_SHIFT		13
82 
83 #define	T_SATA0_CFG_35				0x94
84 #define	 T_SATA0_CFG_35_IDP_INDEX_MASK			(0x7ff << 2)
85 #define	 T_SATA0_CFG_35_IDP_INDEX			(0x2a << 2)
86 
87 #define	T_SATA0_AHCI_IDP1			0x98
88 #define	 T_SATA0_AHCI_IDP1_DATA				0x400040
89 
90 #define	T_SATA0_CFG_PHY_1			0x12c
91 #define	 T_SATA0_CFG_PHY_1_PADS_IDDQ_EN			(1 << 23)
92 #define	 T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN		(1 << 22)
93 
94 #define	T_SATA0_NVOOB				0x114
95 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK	(0x3 << 26)
96 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH		(0x3 << 26)
97 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK		(0x3 << 24)
98 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_MODE		(0x1 << 24)
99 #define	 T_SATA0_NVOOB_COMMA_CNT_MASK			(0xff << 16)
100 #define	 T_SATA0_NVOOB_COMMA_CNT			(0x07 << 16)
101 
102 #define	T_SATA0_CFG_PHY				0x120
103 #define	 T_SATA0_CFG_PHY_MASK_SQUELCH			(1 << 24)
104 #define	 T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD	(1 << 11)
105 
106 #define	T_SATA0_CFG2NVOOB_2			0x134
107 #define	 T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK	(0x1ff << 18)
108 #define	 T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW	(0xc << 18)
109 
110 #define	T_SATA0_AHCI_HBA_CAP_BKDR		0x300
111 #define	 T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ			(1 << 30)
112 #define	 T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM		(1 << 17)
113 #define	 T_SATA0_AHCI_HBA_CAP_BKDR_SALP			(1 << 26)
114 #define	 T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP	(1 << 14)
115 #define	 T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP	(1 << 13)
116 
117 #define	T_SATA0_BKDOOR_CC			0x4a4
118 #define	 T_SATA0_BKDOOR_CC_CLASS_CODE_MASK		(0xffff << 16)
119 #define	 T_SATA0_BKDOOR_CC_CLASS_CODE			(0x0106 << 16)
120 #define	 T_SATA0_BKDOOR_CC_PROG_IF_MASK			(0xff << 8)
121 #define	 T_SATA0_BKDOOR_CC_PROG_IF			(0x01 << 8)
122 
123 #define	T_SATA0_CFG_SATA			0x54c
124 #define	 T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN		(1 << 12)
125 
126 #define	T_SATA0_CFG_MISC			0x550
127 #define	T_SATA0_INDEX				0x680
128 
129 #define	T_SATA0_CHX_PHY_CTRL1_GEN1		0x690
130 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK	0xff
131 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT	8
132 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK		0xff
133 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT	0
134 
135 #define	T_SATA0_CHX_PHY_CTRL1_GEN2		0x694
136 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK	0xff
137 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT	12
138 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK		0xff
139 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT	0
140 
141 #define	T_SATA0_CHX_PHY_CTRL2			0x69c
142 #define	 T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1		0x23
143 
144 #define	T_SATA0_CHX_PHY_CTRL11			0x6d0
145 #define	 T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ		(0x2800 << 16)
146 
147 #define T_SATA0_CHX_PHY_CTRL17			0x6e8
148 #define T_SATA0_CHX_PHY_CTRL18			0x6ec
149 #define T_SATA0_CHX_PHY_CTRL20			0x6f4
150 #define T_SATA0_CHX_PHY_CTRL21			0x6f8
151 
152 #define	FUSE_SATA_CALIB				0x124
153 #define	FUSE_SATA_CALIB_MASK			0x3
154 
155 #define	SATA_AUX_MISC_CNTL			0x1108
156 #define	SATA_AUX_PAD_PLL_CTRL_0			0x1120
157 #define	SATA_AUX_PAD_PLL_CTRL_1			0x1124
158 #define	SATA_AUX_PAD_PLL_CTRL_2			0x1128
159 #define	SATA_AUX_PAD_PLL_CTRL_3			0x112c
160 
161 #define	T_AHCI_HBA_CCC_PORTS			0x0018
162 #define	T_AHCI_HBA_CAP_BKDR			0x00A0
163 #define	 T_AHCI_HBA_CAP_BKDR_S64A			(1 << 31)
164 #define	 T_AHCI_HBA_CAP_BKDR_SNCQ			(1 << 30)
165 #define	 T_AHCI_HBA_CAP_BKDR_SSNTF			(1 << 29)
166 #define	 T_AHCI_HBA_CAP_BKDR_SMPS			(1 << 28)
167 #define	 T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP		(1 << 27)
168 #define	 T_AHCI_HBA_CAP_BKDR_SALP			(1 << 26)
169 #define	 T_AHCI_HBA_CAP_BKDR_SAL			(1 << 25)
170 #define	 T_AHCI_HBA_CAP_BKDR_SUPP_CLO			(1 << 24)
171 #define	 T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x)		(((x) & 0xF) << 20)
172 #define	 T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET	(1 << 19)
173 #define	 T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY		(1 << 18)
174 #define	 T_AHCI_HBA_CAP_BKDR_SUPP_PM			(1 << 17)
175 #define	 T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING		(1 << 16)
176 #define	 T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK		(1 << 15)
177 #define	 T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP		(1 << 14)
178 #define	 T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP		(1 << 13)
179 #define	 T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x)		(((x) & 0x1F) <<  8)
180 #define	 T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING		(1 <<  7)
181 #define	 T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP		(1 <<  6)
182 #define	 T_AHCI_HBA_CAP_BKDR_EXT_SATA			(1 <<  5)
183 #define	 T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x)		(((x) & 0xF) <<  0)
184 
185 #define	T_AHCI_PORT_BKDR			0x0170
186 
187 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x)	(((x) & 0xFF) << 24)
188 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x)	(((x) & 0x1F) << 16)
189 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE	(1 << 15)
190 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE	(1 << 14)
191 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_DM(x)		(((x) & 0xF) << 10)
192 #define	 T_AHCI_PORT_BKDR_PORT_UNCONNECTED		(1 <<  9)
193 #define	 T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH	(1 <<  8)
194 #define	 T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 <<  7)
195 #define	 T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP	(1 <<  6)
196 #define	 T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP	(1 <<  5)
197 #define	 T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP	(1 <<  4)
198 #define	 T_AHCI_PORT_BKDR_HOTPLUG_CAP			(1 <<  3)
199 #define	 T_AHCI_PORT_BKDR_MECH_SWITCH			(1 <<  2)
200 #define	 T_AHCI_PORT_BKDR_COLD_PRSN_DET			(1 <<  1)
201 #define	 T_AHCI_PORT_BKDR_EXT_SATA_SUPP			(1 <<  0)
202 
203 /* AUX registers */
204 #define	SATA_AUX_MISC_CNTL_1			0x008
205 #define	 SATA_AUX_MISC_CNTL_1_DEVSLP_OVERRIDE		(1 << 17)
206 #define	 SATA_AUX_MISC_CNTL_1_SDS_SUPPORT		(1 << 13)
207 #define	 SATA_AUX_MISC_CNTL_1_DESO_SUPPORT		(1 << 15)
208 
209 #define	AHCI_WR4(_sc, _r, _v)	bus_write_4((_sc)->ctlr.r_mem, (_r), (_v))
210 #define	AHCI_RD4(_sc, _r)	bus_read_4((_sc)->ctlr.r_mem, (_r))
211 #define	SATA_WR4(_sc, _r, _v)	bus_write_4((_sc)->sata_mem, (_r), (_v))
212 #define	SATA_RD4(_sc, _r)	bus_read_4((_sc)->sata_mem, (_r))
213 
214 struct sata_pad_calibration {
215 	uint32_t gen1_tx_amp;
216 	uint32_t gen1_tx_peak;
217 	uint32_t gen2_tx_amp;
218 	uint32_t gen2_tx_peak;
219 };
220 
221 static const struct sata_pad_calibration tegra124_pad_calibration[] = {
222 	{0x18, 0x04, 0x18, 0x0a},
223 	{0x0e, 0x04, 0x14, 0x0a},
224 	{0x0e, 0x07, 0x1a, 0x0e},
225 	{0x14, 0x0e, 0x1a, 0x0e},
226 };
227 
228 struct ahci_soc;
229 struct tegra_ahci_sc {
230 	struct ahci_controller	ctlr;	/* Must be first */
231 	device_t		dev;
232 	struct ahci_soc		*soc;
233 	struct resource		*sata_mem;
234 	struct resource		*aux_mem;
235 	clk_t			clk_sata;
236 	clk_t			clk_sata_oob;
237 	clk_t			clk_pll_e;
238 	clk_t			clk_cml;
239 	hwreset_t		hwreset_sata;
240 	hwreset_t		hwreset_sata_oob;
241 	hwreset_t		hwreset_sata_cold;
242 	regulator_t		regulators[16];		/* Safe maximum */
243 	phy_t			phy;
244 };
245 
246 struct ahci_soc {
247 	char 	**regulator_names;
248 	int	(*init)(struct tegra_ahci_sc *sc);
249 };
250 
251 /* Tegra 124 config. */
252 static char *tegra124_reg_names[] = {
253 	"hvdd-supply",
254 	"vddio-supply",
255 	"avdd-supply",
256 	"target-5v-supply",
257 	"target-12v-supply",
258 	NULL
259 };
260 
261 static int tegra124_ahci_init(struct tegra_ahci_sc *sc);
262 static struct ahci_soc tegra124_soc = {
263 	.regulator_names = tegra124_reg_names,
264 	.init = tegra124_ahci_init,
265 };
266 
267 /* Tegra 210 config. */
268 static char *tegra210_reg_names[] = {
269 	NULL
270 };
271 
272 static struct ahci_soc tegra210_soc = {
273 	.regulator_names = tegra210_reg_names,
274 };
275 
276 
277 static struct ofw_compat_data compat_data[] = {
278 	{"nvidia,tegra124-ahci", (uintptr_t)&tegra124_soc},
279 	{"nvidia,tegra210-ahci", (uintptr_t)&tegra210_soc},
280 	{NULL,			0}
281 };
282 
283 static int
284 get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node)
285 {
286 	int i, rv;
287 
288 	/* Regulators. */
289 	for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {
290 		if (i >= nitems(sc->regulators)) {
291 			device_printf(sc->dev,
292 			    "Too many regulators present in DT.\n");
293 			return (EOVERFLOW);
294 		}
295 		rv = regulator_get_by_ofw_property(sc->dev, 0,
296 		    sc->soc->regulator_names[i], sc->regulators + i);
297 		if (rv != 0) {
298 			device_printf(sc->dev,
299 			    "Cannot get '%s' regulator\n",
300 			    sc->soc->regulator_names[i]);
301 			return (ENXIO);
302 		}
303 	}
304 
305 	/* Resets. */
306 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );
307 	if (rv != 0) {
308 		device_printf(sc->dev, "Cannot get 'sata' reset\n");
309 		return (ENXIO);
310 	}
311 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",
312 	    &sc->hwreset_sata_oob);
313 	if (rv != 0) {
314 		device_printf(sc->dev, "Cannot get 'sata oob' reset\n");
315 		return (ENXIO);
316 	}
317 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",
318 	    &sc->hwreset_sata_cold);
319 	if (rv != 0) {
320 		device_printf(sc->dev, "Cannot get 'sata cold' reset\n");
321 		return (ENXIO);
322 	}
323 
324 	/* Phy */
325 	rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);
326 	if (rv != 0) {
327 		rv = phy_get_by_ofw_idx(sc->dev, 0, 0, &sc->phy);
328 		if (rv != 0) {
329 			device_printf(sc->dev, "Cannot get 'sata' phy\n");
330 			return (ENXIO);
331 		}
332 	}
333 
334 	/* Clocks. */
335 	rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);
336 	if (rv != 0) {
337 		device_printf(sc->dev, "Cannot get 'sata' clock\n");
338 		return (ENXIO);
339 	}
340 	rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);
341 	if (rv != 0) {
342 		device_printf(sc->dev, "Cannot get 'sata oob' clock\n");
343 		return (ENXIO);
344 	}
345 	/* These are optional */
346 	rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);
347 	if (rv != 0)
348 		sc->clk_cml = NULL;
349 
350 	rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
351 	if (rv != 0)
352 		sc->clk_pll_e = NULL;
353 	return (0);
354 }
355 
356 static int
357 enable_fdt_resources(struct tegra_ahci_sc *sc)
358 {
359 	int i, rv;
360 
361 	/* Enable regulators. */
362 	for (i = 0; i < nitems(sc->regulators); i++) {
363 		if (sc->regulators[i] == NULL)
364 			continue;
365 		rv = regulator_enable(sc->regulators[i]);
366 		if (rv != 0) {
367 			device_printf(sc->dev,
368 			    "Cannot enable '%s' regulator\n",
369 			    sc->soc->regulator_names[i]);
370 			return (rv);
371 		}
372 	}
373 
374 	/* Stop clocks */
375 	clk_stop(sc->clk_sata);
376 	clk_stop(sc->clk_sata_oob);
377 	tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
378 
379 	rv = hwreset_assert(sc->hwreset_sata);
380 	if (rv != 0) {
381 		device_printf(sc->dev, "Cannot assert 'sata' reset\n");
382 		return (rv);
383 	}
384 	rv = hwreset_assert(sc->hwreset_sata_oob);
385 	if (rv != 0) {
386 		device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
387 		return (rv);
388 	}
389 
390 	rv = hwreset_assert(sc->hwreset_sata_cold);
391 	if (rv != 0) {
392 		device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
393 		return (rv);
394 	}
395 	rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
396 	    sc->clk_sata, sc->hwreset_sata);
397 	if (rv != 0) {
398 		device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
399 		return (rv);
400 	}
401 
402 	rv = clk_enable(sc->clk_sata_oob);
403 	if (rv != 0) {
404 		device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
405 		return (rv);
406 	}
407 	if (sc->clk_cml != NULL) {
408 		rv = clk_enable(sc->clk_cml);
409 		if (rv != 0) {
410 			device_printf(sc->dev, "Cannot enable 'cml' clock\n");
411 			return (rv);
412 		}
413 	}
414 	if (sc->clk_pll_e != NULL) {
415 		rv = clk_enable(sc->clk_pll_e);
416 		if (rv != 0) {
417 			device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
418 			return (rv);
419 		}
420 	}
421 
422 	rv = hwreset_deassert(sc->hwreset_sata_cold);
423 	if (rv != 0) {
424 		device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
425 		return (rv);
426 	}
427 	rv = hwreset_deassert(sc->hwreset_sata_oob);
428 	if (rv != 0) {
429 		device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
430 		return (rv);
431 	}
432 
433 	rv = phy_enable(sc->phy);
434 	if (rv != 0) {
435 		device_printf(sc->dev, "Cannot enable SATA phy\n");
436 		return (rv);
437 	}
438 
439 	return (0);
440 }
441 
442 static int
443 tegra124_ahci_init(struct tegra_ahci_sc *sc)
444 {
445 	uint32_t val;
446 	const struct sata_pad_calibration *calib;
447 
448 	/* Pad calibration. */
449 	val = tegra_fuse_read_4(FUSE_SATA_CALIB);
450 	calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK);
451 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1);
452 
453 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
454 	val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK <<
455 	    T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
456 	val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK <<
457 	    T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
458 	val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
459 	val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
460 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val);
461 
462 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
463 	val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK <<
464 	    T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
465 	val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK <<
466 	    T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
467 	val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT;
468 	val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT;
469 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val);
470 
471 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11,
472 	    T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ);
473 
474 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2,
475 	    T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1);
476 
477 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0);
478 
479 	return (0);
480 }
481 
482 static int
483 tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc)
484 {
485 	uint32_t val;
486 	int rv;
487 
488 	/* Enable SATA MMIO. */
489 	val = SATA_RD4(sc, SATA_FPCI_BAR5);
490 	val &= ~SATA_FPCI_BAR_START(~0);
491 	val |= SATA_FPCI_BAR_START(0x10000);
492 	val |= SATA_FPCI_BAR_ACCESS_TYPE;
493 	SATA_WR4(sc, SATA_FPCI_BAR5, val);
494 
495 	/* Enable FPCI access */
496 	val = SATA_RD4(sc, SATA_CONFIGURATION);
497 	val |= SATA_CONFIGURATION_EN_FPCI;
498 	SATA_WR4(sc, SATA_CONFIGURATION, val);
499 
500 	/* Recommended electrical settings for phy */
501 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17, 0x55010000);
502 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18, 0x55010000);
503 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20, 0x1);
504 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21, 0x1);
505 
506 	/* SQUELCH and Gen3 */
507 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY);
508 	val |= T_SATA0_CFG_PHY_MASK_SQUELCH;
509 	val &= ~T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD;
510 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY, val);
511 
512 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_NVOOB);
513 	val &= ~T_SATA0_NVOOB_COMMA_CNT_MASK;
514 	val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK;
515 	val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK;
516 	val |= T_SATA0_NVOOB_COMMA_CNT;
517 	val |= T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH;
518 	val |= T_SATA0_NVOOB_SQUELCH_FILTER_MODE;
519 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_NVOOB, val);
520 
521 	 /* Setup COMWAKE_IDLE_CNT */
522 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
523 	val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
524 	val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
525 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2, val);
526 
527 	if (sc->soc->init != NULL) {
528 		rv = sc->soc->init(sc);
529 		if (rv != 0) {
530 			device_printf(sc->dev,
531 			    "SOC specific intialization failed: %d\n", rv);
532 			return (rv);
533 		}
534 	}
535 
536 	/* Enable backdoor programming. */
537 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
538 	val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
539 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
540 
541 	/* Set device class and interface */
542 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC);
543 	val &= ~T_SATA0_BKDOOR_CC_CLASS_CODE_MASK;
544 	val &= ~T_SATA0_BKDOOR_CC_PROG_IF_MASK;
545 	val |= T_SATA0_BKDOOR_CC_CLASS_CODE;
546 	val |= T_SATA0_BKDOOR_CC_PROG_IF;
547 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, val);
548 
549 	/* Enable LPM capabilities  */
550 	val = SATA_RD4(sc, SCFG_OFFSET +  T_SATA0_AHCI_HBA_CAP_BKDR);
551 	val |= T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP;
552 	val |= T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP;
553 	val |= T_SATA0_AHCI_HBA_CAP_BKDR_SALP;
554 	val |= T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM;
555 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR, val);
556 
557 	/* Disable backdoor programming. */
558 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
559 	val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
560 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
561 
562 	/* SATA Second Level Clock Gating */
563 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_35);
564 	val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
565 	val |= T_SATA0_CFG_35_IDP_INDEX;
566 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_35, val);
567 
568 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_IDP1, 0x400040);
569 
570 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1);
571 	val |= T_SATA0_CFG_PHY_1_PADS_IDDQ_EN;
572 	val |= T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN;
573 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1, val);
574 
575 	/*
576 	 * Indicate Sata only has the capability to enter DevSleep
577 	 * from slumber link.
578 	 */
579 	if (sc->aux_mem != NULL) {
580 		val = bus_read_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1);
581 		val |= SATA_AUX_MISC_CNTL_1_DESO_SUPPORT;
582 		bus_write_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1, val);
583 	}
584 
585 	/* Enable IPFS Clock Gating */
586 	val = SATA_RD4(sc, SCFG_OFFSET + SATA_CONFIGURATION);
587 	val &= ~SATA_CONFIGURATION_CLK_OVERRIDE;
588 	SATA_WR4(sc, SCFG_OFFSET + SATA_CONFIGURATION, val);
589 
590 
591 	/* Enable IO & memory access, bus master mode */
592 	val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1);
593 	val |= T_SATA0_CFG_1_IO_SPACE;
594 	val |= T_SATA0_CFG_1_MEMORY_SPACE;
595 	val |= T_SATA0_CFG_1_BUS_MASTER;
596 	val |= T_SATA0_CFG_1_SERR;
597 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val);
598 
599 	/* AHCI bar */
600 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_9,
601 	    0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT);
602 
603 	/* Unmask  interrupts. */
604 	val = SATA_RD4(sc, SATA_INTR_MASK);
605 	val |= SATA_INTR_MASK_IP_INT_MASK;
606 	SATA_WR4(sc, SATA_INTR_MASK, val);
607 
608 	return (0);
609 }
610 
611 static int
612 tegra_ahci_ctlr_reset(device_t dev)
613 {
614 	struct tegra_ahci_sc *sc;
615 	int rv;
616 	uint32_t reg;
617 
618 	sc = device_get_softc(dev);
619 	rv = ahci_ctlr_reset(dev);
620 	if (rv != 0)
621 		return (0);
622 	AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1);
623 
624 	/* Overwrite AHCI capabilites. */
625 	reg  = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR);
626 	reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0);
627 	reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0);
628 	reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA;
629 	reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING;
630 	reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING;
631 	reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM;
632 	reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO;
633 	reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP;
634 	AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg);
635 
636 	/* Overwrite AHCI portcapabilites. */
637 	reg  = AHCI_RD4(sc, T_AHCI_PORT_BKDR);
638 	reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET;
639 	reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP;
640 	reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP;
641 	AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg);
642 
643 	return (0);
644 }
645 
646 static int
647 tegra_ahci_probe(device_t dev)
648 {
649 
650 	if (!ofw_bus_status_okay(dev))
651 		return (ENXIO);
652 
653 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
654 		return (ENXIO);
655 
656 	device_set_desc_copy(dev, "AHCI SATA controller");
657 	return (BUS_PROBE_DEFAULT);
658 }
659 
660 static int
661 tegra_ahci_attach(device_t dev)
662 {
663 	struct tegra_ahci_sc *sc;
664 	struct ahci_controller *ctlr;
665 	phandle_t node;
666 	int rv, rid;
667 
668 	sc = device_get_softc(dev);
669 	sc->dev = dev;
670 	ctlr = &sc->ctlr;
671 	node = ofw_bus_get_node(dev);
672 	sc->soc = (struct ahci_soc *)ofw_bus_search_compatible(dev,
673 	    compat_data)->ocd_data;
674 
675 	ctlr->r_rid = 0;
676 	ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
677 	    &ctlr->r_rid, RF_ACTIVE);
678 	if (ctlr->r_mem == NULL)
679 		return (ENXIO);
680 
681 	rid = 1;
682 	sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
683 	    &rid, RF_ACTIVE);
684 	if (sc->sata_mem == NULL) {
685 		rv = ENXIO;
686 		goto fail;
687 	}
688 
689 	/* Aux is optionall */
690 	rid = 2;
691 	sc->aux_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
692 	    &rid, RF_ACTIVE);
693 
694 	rv = get_fdt_resources(sc, node);
695 	if (rv != 0) {
696 		device_printf(sc->dev, "Failed to allocate FDT resource(s)\n");
697 		goto fail;
698 	}
699 
700 	rv = enable_fdt_resources(sc);
701 	if (rv != 0) {
702 		device_printf(sc->dev, "Failed to enable FDT resource(s)\n");
703 		goto fail;
704 	}
705 	rv = tegra_ahci_ctrl_init(sc);
706 	if (rv != 0) {
707 		device_printf(sc->dev, "Failed to initialize controller)\n");
708 		goto fail;
709 	}
710 
711 	/* Setup controller defaults. */
712 	ctlr->msi = 0;
713 	ctlr->numirqs = 1;
714 	ctlr->ccc = 0;
715 
716 	/* Reset controller. */
717 	rv = tegra_ahci_ctlr_reset(dev);
718 	if (rv != 0)
719 		goto fail;
720 	rv = ahci_attach(dev);
721 	return (rv);
722 
723 fail:
724 	/* XXX FDT  stuff */
725 	if (sc->sata_mem != NULL)
726 		bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem);
727 	if (ctlr->r_mem != NULL)
728 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
729 		    ctlr->r_mem);
730 	return (rv);
731 }
732 
733 static int
734 tegra_ahci_detach(device_t dev)
735 {
736 
737 	ahci_detach(dev);
738 	return (0);
739 }
740 
741 static int
742 tegra_ahci_suspend(device_t dev)
743 {
744 	struct tegra_ahci_sc *sc = device_get_softc(dev);
745 
746 	bus_generic_suspend(dev);
747 	/* Disable interupts, so the state change(s) doesn't trigger. */
748 	ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC,
749 	     ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
750 	return (0);
751 }
752 
753 static int
754 tegra_ahci_resume(device_t dev)
755 {
756 	int res;
757 
758 	if ((res = tegra_ahci_ctlr_reset(dev)) != 0)
759 		return (res);
760 	ahci_ctlr_setup(dev);
761 	return (bus_generic_resume(dev));
762 }
763 
764 static device_method_t tegra_ahci_methods[] = {
765 	DEVMETHOD(device_probe,		tegra_ahci_probe),
766 	DEVMETHOD(device_attach,	tegra_ahci_attach),
767 	DEVMETHOD(device_detach,	tegra_ahci_detach),
768 	DEVMETHOD(device_suspend,	tegra_ahci_suspend),
769 	DEVMETHOD(device_resume,	tegra_ahci_resume),
770 	DEVMETHOD(bus_print_child,	ahci_print_child),
771 	DEVMETHOD(bus_alloc_resource,	ahci_alloc_resource),
772 	DEVMETHOD(bus_release_resource,	ahci_release_resource),
773 	DEVMETHOD(bus_setup_intr,	ahci_setup_intr),
774 	DEVMETHOD(bus_teardown_intr,	ahci_teardown_intr),
775 	DEVMETHOD(bus_child_location,	ahci_child_location),
776 	DEVMETHOD(bus_get_dma_tag,	ahci_get_dma_tag),
777 
778 	DEVMETHOD_END
779 };
780 
781 static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods,
782     sizeof(struct tegra_ahci_sc));
783 DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, NULL, NULL);
784