1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 #include <machine/frame.h> 47 #include <machine/intr.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 58 struct mv_timer_softc { 59 struct resource * timer_res[2]; 60 bus_space_tag_t timer_bst; 61 bus_space_handle_t timer_bsh; 62 struct mtx timer_mtx; 63 struct eventtimer et; 64 }; 65 66 static struct resource_spec mv_timer_spec[] = { 67 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 68 { SYS_RES_IRQ, 0, RF_ACTIVE }, 69 { -1, 0 } 70 }; 71 72 static struct mv_timer_softc *timer_softc = NULL; 73 static int timers_initialized = 0; 74 75 static int mv_timer_probe(device_t); 76 static int mv_timer_attach(device_t); 77 78 static int mv_hardclock(void *); 79 static unsigned mv_timer_get_timecount(struct timecounter *); 80 81 static uint32_t mv_get_timer_control(void); 82 static void mv_set_timer_control(uint32_t); 83 static uint32_t mv_get_timer(uint32_t); 84 static void mv_set_timer(uint32_t, uint32_t); 85 static void mv_set_timer_rel(uint32_t, uint32_t); 86 static void mv_watchdog_enable(void); 87 static void mv_watchdog_disable(void); 88 static void mv_watchdog_event(void *, unsigned int, int *); 89 static int mv_timer_start(struct eventtimer *et, 90 struct bintime *first, struct bintime *period); 91 static int mv_timer_stop(struct eventtimer *et); 92 static void mv_setup_timers(void); 93 94 static struct timecounter mv_timer_timecounter = { 95 .tc_get_timecount = mv_timer_get_timecount, 96 .tc_name = "CPUTimer1", 97 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 98 .tc_counter_mask = ~0u, 99 .tc_quality = 1000, 100 }; 101 102 static int 103 mv_timer_probe(device_t dev) 104 { 105 106 if (!ofw_bus_is_compatible(dev, "mrvl,timer")) 107 return (ENXIO); 108 109 device_set_desc(dev, "Marvell CPU Timer"); 110 return (0); 111 } 112 113 static int 114 mv_timer_attach(device_t dev) 115 { 116 int error; 117 void *ihl; 118 struct mv_timer_softc *sc; 119 uint32_t irq_cause, irq_mask; 120 121 if (timer_softc != NULL) 122 return (ENXIO); 123 124 sc = (struct mv_timer_softc *)device_get_softc(dev); 125 timer_softc = sc; 126 127 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 128 if (error) { 129 device_printf(dev, "could not allocate resources\n"); 130 return (ENXIO); 131 } 132 133 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 134 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 135 136 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 137 mv_watchdog_disable(); 138 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 139 140 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 141 mv_hardclock, NULL, sc, &ihl) != 0) { 142 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 143 device_printf(dev, "Could not setup interrupt.\n"); 144 return (ENXIO); 145 } 146 147 mv_setup_timers(); 148 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 149 irq_cause &= ~(IRQ_TIMER0); 150 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 151 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 152 irq_mask |= IRQ_TIMER0_MASK; 153 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 154 155 sc->et.et_name = "CPUTimer0"; 156 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 157 sc->et.et_quality = 1000; 158 sc->et.et_frequency = get_tclk(); 159 sc->et.et_min_period.sec = 0; 160 sc->et.et_min_period.frac = 161 ((0x00000002LLU << 32) / sc->et.et_frequency) << 32; 162 sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency; 163 sc->et.et_max_period.frac = 164 ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32; 165 sc->et.et_start = mv_timer_start; 166 sc->et.et_stop = mv_timer_stop; 167 sc->et.et_priv = sc; 168 et_register(&sc->et); 169 mv_timer_timecounter.tc_frequency = get_tclk(); 170 tc_init(&mv_timer_timecounter); 171 172 return (0); 173 } 174 175 static int 176 mv_hardclock(void *arg) 177 { 178 struct mv_timer_softc *sc; 179 uint32_t irq_cause; 180 181 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 182 irq_cause &= ~(IRQ_TIMER0); 183 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 184 185 sc = (struct mv_timer_softc *)arg; 186 if (sc->et.et_active) 187 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 188 189 return (FILTER_HANDLED); 190 } 191 192 static device_method_t mv_timer_methods[] = { 193 DEVMETHOD(device_probe, mv_timer_probe), 194 DEVMETHOD(device_attach, mv_timer_attach), 195 196 { 0, 0 } 197 }; 198 199 static driver_t mv_timer_driver = { 200 "timer", 201 mv_timer_methods, 202 sizeof(struct mv_timer_softc), 203 }; 204 205 static devclass_t mv_timer_devclass; 206 207 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0); 208 209 static unsigned 210 mv_timer_get_timecount(struct timecounter *tc) 211 { 212 213 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 214 } 215 216 void 217 cpu_initclocks(void) 218 { 219 220 cpu_initclocks_bsp(); 221 } 222 223 void 224 DELAY(int usec) 225 { 226 uint32_t val, val_temp; 227 int32_t nticks; 228 229 if (!timers_initialized) { 230 for (; usec > 0; usec--) 231 for (val = 100; val > 0; val--) 232 ; 233 return; 234 } 235 236 val = mv_get_timer(1); 237 nticks = ((get_tclk() / 1000000 + 1) * usec); 238 239 while (nticks > 0) { 240 val_temp = mv_get_timer(1); 241 if (val > val_temp) 242 nticks -= (val - val_temp); 243 else 244 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 245 246 val = val_temp; 247 } 248 } 249 250 static uint32_t 251 mv_get_timer_control(void) 252 { 253 254 return (bus_space_read_4(timer_softc->timer_bst, 255 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 256 } 257 258 static void 259 mv_set_timer_control(uint32_t val) 260 { 261 262 bus_space_write_4(timer_softc->timer_bst, 263 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 264 } 265 266 static uint32_t 267 mv_get_timer(uint32_t timer) 268 { 269 270 return (bus_space_read_4(timer_softc->timer_bst, 271 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 272 } 273 274 static void 275 mv_set_timer(uint32_t timer, uint32_t val) 276 { 277 278 bus_space_write_4(timer_softc->timer_bst, 279 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 280 } 281 282 static void 283 mv_set_timer_rel(uint32_t timer, uint32_t val) 284 { 285 286 bus_space_write_4(timer_softc->timer_bst, 287 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 288 } 289 290 static void 291 mv_watchdog_enable(void) 292 { 293 uint32_t val; 294 uint32_t irq_cause, irq_mask; 295 296 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 297 irq_cause &= ~(IRQ_TIMER_WD); 298 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 299 300 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 301 irq_mask |= IRQ_TIMER_WD_MASK; 302 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 303 304 val = read_cpu_ctrl(RSTOUTn_MASK); 305 val |= WD_RST_OUT_EN; 306 write_cpu_ctrl(RSTOUTn_MASK, val); 307 308 val = mv_get_timer_control(); 309 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; 310 mv_set_timer_control(val); 311 } 312 313 static void 314 mv_watchdog_disable(void) 315 { 316 uint32_t val; 317 uint32_t irq_cause, irq_mask; 318 319 val = mv_get_timer_control(); 320 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 321 mv_set_timer_control(val); 322 323 val = read_cpu_ctrl(RSTOUTn_MASK); 324 val &= ~WD_RST_OUT_EN; 325 write_cpu_ctrl(RSTOUTn_MASK, val); 326 327 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 328 irq_mask &= ~(IRQ_TIMER_WD_MASK); 329 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 330 331 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 332 irq_cause &= ~(IRQ_TIMER_WD); 333 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 334 } 335 336 337 /* 338 * Watchdog event handler. 339 */ 340 static void 341 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 342 { 343 uint64_t ns; 344 uint64_t ticks; 345 346 mtx_lock(&timer_softc->timer_mtx); 347 if (cmd == 0) 348 mv_watchdog_disable(); 349 else { 350 /* 351 * Watchdog timeout is in nanosecs, calculation according to 352 * watchdog(9) 353 */ 354 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 355 ticks = (uint64_t)(ns * get_tclk()) / 1000000000; 356 if (ticks > MAX_WATCHDOG_TICKS) 357 mv_watchdog_disable(); 358 else { 359 /* Timer 2 is the watchdog */ 360 mv_set_timer(2, ticks); 361 mv_watchdog_enable(); 362 *error = 0; 363 } 364 } 365 mtx_unlock(&timer_softc->timer_mtx); 366 } 367 368 static int 369 mv_timer_start(struct eventtimer *et, 370 struct bintime *first, struct bintime *period) 371 { 372 struct mv_timer_softc *sc; 373 uint32_t val, val1; 374 375 /* Calculate dividers. */ 376 sc = (struct mv_timer_softc *)et->et_priv; 377 if (period != NULL) { 378 val = (sc->et.et_frequency * (period->frac >> 32)) >> 32; 379 if (period->sec != 0) 380 val += sc->et.et_frequency * period->sec; 381 } else 382 val = 0; 383 if (first != NULL) { 384 val1 = (sc->et.et_frequency * (first->frac >> 32)) >> 32; 385 if (first->sec != 0) 386 val1 += sc->et.et_frequency * first->sec; 387 } else 388 val1 = val; 389 390 /* Apply configuration. */ 391 mv_set_timer_rel(0, val); 392 mv_set_timer(0, val1); 393 val = mv_get_timer_control(); 394 val |= CPU_TIMER0_EN; 395 if (period != NULL) 396 val |= CPU_TIMER0_AUTO; 397 else 398 val &= ~CPU_TIMER0_AUTO; 399 mv_set_timer_control(val); 400 return (0); 401 } 402 403 static int 404 mv_timer_stop(struct eventtimer *et) 405 { 406 uint32_t val; 407 408 val = mv_get_timer_control(); 409 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 410 mv_set_timer_control(val); 411 return (0); 412 } 413 414 static void 415 mv_setup_timers(void) 416 { 417 uint32_t val; 418 419 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 420 mv_set_timer(1, INITIAL_TIMECOUNTER); 421 val = mv_get_timer_control(); 422 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 423 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 424 mv_set_timer_control(val); 425 timers_initialized = 1; 426 } 427