1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Semihalf. 5 * Copyright (c) 1994-1998 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 39 */ 40 41 #include "opt_ddb.h" 42 #include "opt_platform.h" 43 44 #include <sys/cdefs.h> 45 #define _ARM32_BUS_DMA_PRIVATE 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/devmap.h> 50 #include <sys/kernel.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 #include <arm/arm/mpcore_timervar.h> 56 #include <arm/arm/nexusvar.h> 57 58 #include <machine/bus.h> 59 #include <machine/fdt.h> 60 #include <machine/machdep.h> 61 #include <machine/platform.h> 62 #include <machine/platformvar.h> 63 #include <machine/pte.h> 64 65 #include <arm/mv/mvreg.h> 66 #include <arm/mv/mvvar.h> 67 #include <arm/mv/mvwin.h> 68 69 #include <dev/fdt/fdt_common.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include "opt_platform.h" 73 #include "platform_if.h" 74 75 #if defined(SOC_MV_ARMADA38X) 76 #include "platform_pl310_if.h" 77 #include "armada38x/armada38x_pl310.h" 78 #endif 79 80 static int platform_mpp_init(void); 81 int armada38x_win_set_iosync_barrier(void); 82 int armada38x_scu_enable(void); 83 int armada38x_open_bootrom_win(void); 84 int armada38x_mbus_optimization(void); 85 86 static vm_offset_t mv_platform_lastaddr(platform_t plate); 87 static int mv_platform_probe_and_attach(platform_t plate); 88 static void mv_platform_gpio_init(platform_t plate); 89 static void mv_cpu_reset(platform_t plat); 90 91 static void mv_a38x_platform_late_init(platform_t plate); 92 static int mv_a38x_platform_devmap_init(platform_t plate); 93 static void mv_axp_platform_late_init(platform_t plate); 94 static int mv_axp_platform_devmap_init(platform_t plate); 95 96 void armadaxp_init_coher_fabric(void); 97 void armadaxp_l2_init(void); 98 99 #ifdef SMP 100 void mv_a38x_platform_mp_setmaxid(platform_t plate); 101 void mv_a38x_platform_mp_start_ap(platform_t plate); 102 void mv_axp_platform_mp_setmaxid(platform_t plate); 103 void mv_axp_platform_mp_start_ap(platform_t plate); 104 #endif 105 106 #define MPP_PIN_MAX 68 107 #define MPP_PIN_CELLS 2 108 #define MPP_PINS_PER_REG 8 109 #define MPP_SEL(pin,func) (((func) & 0xf) << \ 110 (((pin) % MPP_PINS_PER_REG) * 4)) 111 112 static void 113 mv_busdma_tag_init(void *arg __unused) 114 { 115 phandle_t node; 116 bus_dma_tag_t dmat; 117 118 /* 119 * If this platform has coherent DMA, create the parent DMA tag to pass 120 * down the coherent flag to all busses and devices on the platform, 121 * otherwise return without doing anything. By default create tag 122 * for all A38x-based platforms only. 123 */ 124 if ((node = OF_finddevice("/")) == -1){ 125 printf("no tree\n"); 126 return; 127 } 128 129 if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) 130 return; 131 132 bus_dma_tag_create(NULL, /* No parent tag */ 133 1, 0, /* alignment, bounds */ 134 BUS_SPACE_MAXADDR, /* lowaddr */ 135 BUS_SPACE_MAXADDR, /* highaddr */ 136 NULL, NULL, /* filter, filterarg */ 137 BUS_SPACE_MAXSIZE, /* maxsize */ 138 BUS_SPACE_UNRESTRICTED, /* nsegments */ 139 BUS_SPACE_MAXSIZE, /* maxsegsize */ 140 BUS_DMA_COHERENT, /* flags */ 141 NULL, NULL, /* lockfunc, lockarg */ 142 &dmat); 143 144 nexus_set_dma_tag(dmat); 145 146 } 147 SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); 148 149 static int 150 platform_mpp_init(void) 151 { 152 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 153 int mpp[MPP_PIN_MAX]; 154 uint32_t ctrl_val, ctrl_offset; 155 pcell_t reg[4]; 156 u_long start, size; 157 phandle_t node; 158 pcell_t pin_cells, *pinmap_ptr, pin_count; 159 ssize_t len; 160 int par_addr_cells, par_size_cells; 161 int tuple_size, rv, pins, i, j; 162 int mpp_pin, mpp_function; 163 164 /* 165 * Try to access the MPP node directly i.e. through /aliases/mpp. 166 */ 167 if ((node = OF_finddevice("mpp")) != -1) 168 if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) 169 goto moveon; 170 /* 171 * Find the node the long way. 172 */ 173 if ((node = OF_finddevice("/")) == -1) 174 return (ENXIO); 175 176 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 177 return (ENXIO); 178 179 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 180 /* 181 * No MPP node. Fall back to how MPP got set by the 182 * first-stage loader and try to continue booting. 183 */ 184 return (0); 185 moveon: 186 /* 187 * Process 'reg' prop. 188 */ 189 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 190 &par_size_cells)) != 0) 191 return(ENXIO); 192 193 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 194 len = OF_getprop(node, "reg", reg, sizeof(reg)); 195 if (tuple_size <= 0) 196 return (EINVAL); 197 198 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 199 &start, &size); 200 if (rv != 0) 201 return (rv); 202 start += fdt_immr_va; 203 204 /* 205 * Process 'pin-count' and 'pin-map' props. 206 */ 207 if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 208 return (ENXIO); 209 if (pin_count > MPP_PIN_MAX) 210 return (ERANGE); 211 212 if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 213 pin_cells = MPP_PIN_CELLS; 214 if (pin_cells > MPP_PIN_CELLS) 215 return (ERANGE); 216 tuple_size = sizeof(pcell_t) * pin_cells; 217 218 bzero(pinmap, sizeof(pinmap)); 219 len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); 220 if (len <= 0) 221 return (ERANGE); 222 if (len % tuple_size) 223 return (ERANGE); 224 pins = len / tuple_size; 225 if (pins > pin_count) 226 return (ERANGE); 227 /* 228 * Fill out a "mpp[pin] => function" table. All pins unspecified in 229 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 230 */ 231 bzero(mpp, sizeof(mpp)); 232 pinmap_ptr = pinmap; 233 for (i = 0; i < pins; i++) { 234 mpp_pin = *pinmap_ptr; 235 mpp_function = *(pinmap_ptr + 1); 236 mpp[mpp_pin] = mpp_function; 237 pinmap_ptr += pin_cells; 238 } 239 240 /* 241 * Prepare and program MPP control register values. 242 */ 243 ctrl_offset = 0; 244 for (i = 0; i < pin_count;) { 245 ctrl_val = 0; 246 247 for (j = 0; j < MPP_PINS_PER_REG; j++) { 248 if (i + j == pin_count - 1) 249 break; 250 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 251 } 252 i += MPP_PINS_PER_REG; 253 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 254 ctrl_val); 255 256 ctrl_offset += 4; 257 } 258 259 return (0); 260 } 261 262 static vm_offset_t 263 mv_platform_lastaddr(platform_t plat) 264 { 265 266 return (fdt_immr_va); 267 } 268 269 static int 270 mv_platform_probe_and_attach(platform_t plate) 271 { 272 273 if (fdt_immr_addr(MV_BASE) != 0) 274 while (1); 275 return (0); 276 } 277 278 static void 279 mv_platform_gpio_init(platform_t plate) 280 { 281 282 /* 283 * Re-initialise MPP. It is important to call this prior to using 284 * console as the physical connection can be routed via MPP. 285 */ 286 if (platform_mpp_init() != 0) 287 while (1); 288 } 289 290 static void 291 mv_a38x_platform_late_init(platform_t plate) 292 { 293 294 /* 295 * Re-initialise decode windows 296 */ 297 if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) 298 panic("Unsupported SoC family\n"); 299 300 if (soc_decode_win() != 0) 301 printf("WARNING: could not re-initialise decode windows! " 302 "Running with existing settings...\n"); 303 304 /* Configure timers' base frequency */ 305 arm_tmr_change_frequency(get_cpu_freq() / 2); 306 307 /* 308 * Workaround for Marvell Armada38X family HW issue 309 * between Cortex-A9 CPUs and on-chip devices that may 310 * cause hang on heavy load. 311 * To avoid that, map all registers including PCIe IO 312 * as strongly ordered instead of device memory. 313 */ 314 pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO); 315 316 /* Set IO Sync Barrier bit for all Mbus devices */ 317 if (armada38x_win_set_iosync_barrier() != 0) 318 printf("WARNING: could not map CPU Subsystem registers\n"); 319 if (armada38x_mbus_optimization() != 0) 320 printf("WARNING: could not enable mbus optimization\n"); 321 if (armada38x_scu_enable() != 0) 322 printf("WARNING: could not enable SCU\n"); 323 #ifdef SMP 324 /* Open window to bootROM memory - needed for SMP */ 325 if (armada38x_open_bootrom_win() != 0) 326 printf("WARNING: could not open window to bootROM\n"); 327 #endif 328 } 329 330 static void 331 mv_axp_platform_late_init(platform_t plate) 332 { 333 phandle_t node; 334 /* 335 * Re-initialise decode windows 336 */ 337 if (soc_decode_win() != 0) 338 printf("WARNING: could not re-initialise decode windows! " 339 "Running with existing settings...\n"); 340 if ((node = OF_finddevice("/")) == -1) 341 return; 342 343 #if !defined(SMP) 344 /* For SMP case it should be initialized after APs are booted */ 345 armadaxp_init_coher_fabric(); 346 #endif 347 armadaxp_l2_init(); 348 } 349 350 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2) 351 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 352 { 0, 0, 0, } 353 }; 354 355 static int 356 platform_sram_devmap(struct devmap_entry *map) 357 { 358 359 return (ENOENT); 360 } 361 362 /* 363 * Construct devmap table with DT-derived config data. 364 */ 365 static int 366 mv_a38x_platform_devmap_init(platform_t plat) 367 { 368 phandle_t root, child; 369 int i; 370 371 i = 0; 372 devmap_register_table(&fdt_devmap[0]); 373 374 if ((root = OF_finddevice("/")) == -1) 375 return (ENXIO); 376 377 /* 378 * IMMR range. 379 */ 380 fdt_devmap[i].pd_va = fdt_immr_va; 381 fdt_devmap[i].pd_pa = fdt_immr_pa; 382 fdt_devmap[i].pd_size = fdt_immr_size; 383 i++; 384 385 /* 386 * SRAM range. 387 */ 388 if (i < FDT_DEVMAP_MAX) 389 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 390 i++; 391 392 /* 393 * PCI range(s). 394 * PCI range(s) and localbus. 395 */ 396 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 397 if (mv_fdt_is_type(child, "pci") || 398 mv_fdt_is_type(child, "pciep")) { 399 /* 400 * Check space: each PCI node will consume 2 devmap 401 * entries. 402 */ 403 if (i + 1 >= FDT_DEVMAP_MAX) 404 return (ENOMEM); 405 406 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 407 MV_PCI_VA_MEM_BASE) != 0) 408 return (ENXIO); 409 i += 2; 410 } 411 } 412 413 return (0); 414 } 415 416 static int 417 mv_axp_platform_devmap_init(platform_t plate) 418 { 419 vm_paddr_t cur_immr_pa; 420 421 /* 422 * Acquire SoC registers' base passed by u-boot and fill devmap 423 * accordingly. DTB is going to be modified basing on this data 424 * later. 425 */ 426 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 427 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 428 if (cur_immr_pa != 0) 429 fdt_immr_pa = cur_immr_pa; 430 431 mv_a38x_platform_devmap_init(plate); 432 433 return (0); 434 } 435 436 static void 437 mv_cpu_reset(platform_t plat) 438 { 439 440 write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7); 441 write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7); 442 } 443 444 #if defined(SOC_MV_ARMADA38X) 445 static platform_method_t mv_a38x_methods[] = { 446 PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init), 447 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 448 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 449 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 450 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 451 PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init), 452 PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init), 453 PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl), 454 PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug), 455 #ifdef SMP 456 PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap), 457 PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid), 458 #endif 459 460 PLATFORMMETHOD_END, 461 }; 462 FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100); 463 #endif 464 465 static platform_method_t mv_axp_methods[] = { 466 PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init), 467 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 468 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 469 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 470 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 471 PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init), 472 #ifdef SMP 473 PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap), 474 PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid), 475 #endif 476 477 PLATFORMMETHOD_END, 478 }; 479 FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100); 480