1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/smp.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_kern.h> 38 #include <vm/vm_extern.h> 39 #include <vm/pmap.h> 40 41 #include <dev/fdt/fdt_common.h> 42 43 #include <machine/cpu.h> 44 #include <machine/smp.h> 45 #include <machine/fdt.h> 46 #include <machine/armreg.h> 47 48 #include <arm/mv/mvwin.h> 49 50 #include <machine/platformvar.h> 51 52 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) 53 #define CPU_DIVCLK_CTRL0 0x00 54 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 55 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c 56 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) 57 58 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) 59 #define CPU_PMU_BOOT 0x24 60 61 #define MP (MV_BASE + 0x20800) 62 #define MP_SW_RESET(x) ((x) * 8) 63 64 #define CPU_RESUME_CONTROL (0x20988) 65 66 void armadaxp_init_coher_fabric(void); 67 int platform_get_ncpus(void); 68 69 void mv_axp_platform_mp_setmaxid(platform_t plat); 70 void mv_axp_platform_mp_start_ap(platform_t plat); 71 72 /* Coherency Fabric registers */ 73 static uint32_t 74 read_cpu_clkdiv(uint32_t reg) 75 { 76 77 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); 78 } 79 80 static void 81 write_cpu_clkdiv(uint32_t reg, uint32_t val) 82 { 83 84 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); 85 } 86 87 void 88 mv_axp_platform_mp_setmaxid(platform_t plat) 89 { 90 91 mp_ncpus = platform_get_ncpus(); 92 mp_maxid = mp_ncpus - 1; 93 } 94 95 void mptramp(void); 96 void mptramp_end(void); 97 extern vm_offset_t mptramp_pmu_boot; 98 99 void 100 mv_axp_platform_mp_start_ap(platform_t plat) 101 { 102 uint32_t reg, *src, *dst, cpu_num, div_val, cputype; 103 vm_offset_t pmu_boot_off; 104 /* 105 * Initialization procedure depends on core revision, 106 * in this step CHIP ID is checked to choose proper procedure 107 */ 108 cputype = cp15_midr_get(); 109 cputype &= CPU_ID_CPU_MASK; 110 111 /* 112 * Set the PA of CPU0 Boot Address Redirect register used in 113 * mptramp according to the actual SoC registers' base address. 114 */ 115 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; 116 mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off; 117 dst = pmap_mapdev(0xffff0000, PAGE_SIZE); 118 for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end; 119 src++, dst++) { 120 *dst = *src; 121 } 122 pmap_unmapdev(dst, PAGE_SIZE); 123 if (cputype == CPU_ID_MV88SV584X_V7) { 124 /* Core rev A0 */ 125 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 126 div_val &= 0x3f; 127 128 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { 129 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 130 reg &= CPU_DIVCLK_MASK(cpu_num); 131 reg |= div_val << (cpu_num * 8); 132 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 133 } 134 } else { 135 /* Core rev Z1 */ 136 div_val = 0x01; 137 138 if (mp_ncpus > 1) { 139 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); 140 reg &= CPU_DIVCLK_MASK(3); 141 reg |= div_val << 24; 142 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); 143 } 144 145 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { 146 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 147 reg &= CPU_DIVCLK_MASK(cpu_num); 148 reg |= div_val << (cpu_num * 8); 149 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 150 } 151 } 152 153 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 154 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; 155 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 156 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 157 reg |= 0x01000000; 158 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 159 160 DELAY(100); 161 reg &= ~(0xf << 21); 162 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 163 DELAY(100); 164 165 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); 166 167 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 168 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, 169 pmap_kextract((vm_offset_t)mpentry)); 170 171 dcache_wbinv_poc_all(); 172 173 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 174 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); 175 176 /* XXX: Temporary workaround for hangup after releasing AP's */ 177 wmb(); 178 DELAY(10); 179 180 armadaxp_init_coher_fabric(); 181 } 182