1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <machine/fdt.h> 34 35 #include <arm/mv/mvwin.h> 36 #include <arm/mv/mvreg.h> 37 #include <arm/mv/mvvar.h> 38 39 int armada38x_open_bootrom_win(void); 40 int armada38x_scu_enable(void); 41 int armada38x_win_set_iosync_barrier(void); 42 int armada38x_mbus_optimization(void); 43 static uint64_t get_sar_value_armada38x(void); 44 45 static int hw_clockrate; 46 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 47 &hw_clockrate, 0, "CPU instruction clock rate"); 48 49 static uint64_t 50 get_sar_value_armada38x(void) 51 { 52 uint32_t sar_low, sar_high; 53 54 sar_high = 0; 55 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 56 SAMPLE_AT_RESET_ARMADA38X); 57 return (((uint64_t)sar_high << 32) | sar_low); 58 } 59 60 uint32_t 61 get_tclk_armada38x(void) 62 { 63 uint32_t sar; 64 65 /* 66 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. 67 * Current setting is read from Sample At Reset register. 68 */ 69 sar = (uint32_t)get_sar_value_armada38x(); 70 sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X; 71 if (sar == 0) 72 return (TCLK_250MHZ); 73 else 74 return (TCLK_200MHZ); 75 } 76 77 uint32_t 78 get_cpu_freq_armada38x(void) 79 { 80 uint32_t sar; 81 82 static const uint32_t cpu_frequencies[] = { 83 0, 0, 0, 0, 84 1066, 0, 0, 0, 85 1332, 0, 0, 0, 86 1600, 0, 0, 0, 87 1866, 0, 0, 2000 88 }; 89 90 sar = (uint32_t)get_sar_value_armada38x(); 91 sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT; 92 if (sar >= nitems(cpu_frequencies)) 93 return (0); 94 95 hw_clockrate = cpu_frequencies[sar]; 96 97 return (hw_clockrate * 1000 * 1000); 98 } 99 100 int 101 armada38x_win_set_iosync_barrier(void) 102 { 103 bus_space_handle_t vaddr_iowind; 104 int rv; 105 106 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 107 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 108 if (rv != 0) 109 return (rv); 110 111 /* Set Sync Barrier flags for all Mbus internal units */ 112 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL, 113 MV_SYNC_BARRIER_CTRL_ALL); 114 115 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, 116 MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE); 117 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 118 119 return (rv); 120 } 121 122 int 123 armada38x_open_bootrom_win(void) 124 { 125 bus_space_handle_t vaddr_iowind; 126 uint32_t val; 127 int rv; 128 129 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 130 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 131 if (rv != 0) 132 return (rv); 133 134 val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT; 135 val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT; 136 val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT; 137 /* Enable window and Sync Barrier */ 138 val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT; 139 val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT; 140 141 /* Configure IO Window Control Register */ 142 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET, 143 val); 144 /* Configure IO Window Base Register */ 145 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET, 146 MV_BOOTROM_MEM_ADDR); 147 148 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN, 149 BUS_SPACE_BARRIER_WRITE); 150 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 151 152 return (rv); 153 } 154 155 int 156 armada38x_mbus_optimization(void) 157 { 158 bus_space_handle_t vaddr_iowind; 159 int rv; 160 161 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE, 162 MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind); 163 if (rv != 0) 164 return (rv); 165 166 /* 167 * MBUS Units Priority Control Register - Prioritize XOR, 168 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access 169 * GbE is High and others are Medium. 170 */ 171 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180); 172 173 /* 174 * Fabric Units Priority Control Register - 175 * Prioritize CPUs requests. 176 */ 177 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A); 178 179 /* 180 * MBUS Units Prefetch Control Register - 181 * Pre-fetch enable for all IO masters. 182 */ 183 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF); 184 185 /* 186 * Fabric Units Prefetch Control Register - 187 * Enable the CPUs Instruction and Data prefetch. 188 */ 189 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303); 190 191 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN, 192 BUS_SPACE_BARRIER_WRITE); 193 194 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN); 195 196 return (rv); 197 } 198 199 int 200 armada38x_scu_enable(void) 201 { 202 bus_space_handle_t vaddr_scu; 203 int rv; 204 uint32_t val; 205 206 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 207 MV_SCU_REGS_LEN, 0, &vaddr_scu); 208 if (rv != 0) 209 return (rv); 210 211 /* Enable SCU */ 212 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL); 213 if (!(val & MV_SCU_ENABLE)) { 214 /* Enable SCU Speculative linefills to L2 */ 215 val |= MV_SCU_SL_L2_ENABLE; 216 217 bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0, 218 val | MV_SCU_ENABLE); 219 } 220 221 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 222 return (0); 223 } 224