1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/kdb.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <arm/mv/mvreg.h> 49 #include <arm/mv/mvvar.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #define INITIAL_TIMECOUNTER (0xffffffff) 55 #define MAX_WATCHDOG_TICKS (0xffffffff) 56 57 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 58 #define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */ 59 #else 60 #define MV_CLOCK_SRC get_tclk() 61 #endif 62 63 #if defined(SOC_MV_ARMADA38X) 64 #define WATCHDOG_TIMER 4 65 #else 66 #define WATCHDOG_TIMER 2 67 #endif 68 69 struct mv_wdt_softc { 70 struct resource * wdt_res; 71 struct mtx wdt_mtx; 72 }; 73 74 static struct resource_spec mv_wdt_spec[] = { 75 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 76 { -1, 0 } 77 }; 78 79 static struct ofw_compat_data mv_wdt_compat[] = { 80 {"marvell,armada-380-wdt", true}, 81 {NULL, false} 82 }; 83 84 static struct mv_wdt_softc *wdt_softc = NULL; 85 int timers_initialized = 0; 86 87 static int mv_wdt_probe(device_t); 88 static int mv_wdt_attach(device_t); 89 90 static uint32_t mv_get_timer_control(void); 91 static void mv_set_timer_control(uint32_t); 92 static void mv_set_timer(uint32_t, uint32_t); 93 94 static void mv_watchdog_enable(void); 95 static void mv_watchdog_disable(void); 96 static void mv_watchdog_event(void *, unsigned int, int *); 97 98 static device_method_t mv_wdt_methods[] = { 99 DEVMETHOD(device_probe, mv_wdt_probe), 100 DEVMETHOD(device_attach, mv_wdt_attach), 101 102 { 0, 0 } 103 }; 104 105 static driver_t mv_wdt_driver = { 106 "wdt", 107 mv_wdt_methods, 108 sizeof(struct mv_wdt_softc), 109 }; 110 111 static devclass_t mv_wdt_devclass; 112 113 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, mv_wdt_devclass, 0, 0); 114 static int 115 mv_wdt_probe(device_t dev) 116 { 117 118 if (!ofw_bus_status_okay(dev)) 119 return (ENXIO); 120 121 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) 122 return (ENXIO); 123 124 device_set_desc(dev, "Marvell Watchdog Timer"); 125 return (0); 126 } 127 128 static int 129 mv_wdt_attach(device_t dev) 130 { 131 struct mv_wdt_softc *sc; 132 int error; 133 134 if (wdt_softc != NULL) 135 return (ENXIO); 136 137 sc = device_get_softc(dev); 138 wdt_softc = sc; 139 140 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); 141 if (error) { 142 device_printf(dev, "could not allocate resources\n"); 143 return (ENXIO); 144 } 145 146 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); 147 148 mv_watchdog_disable(); 149 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 150 151 return (0); 152 } 153 154 static __inline uint32_t 155 mv_get_timer_control(void) 156 { 157 158 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); 159 } 160 161 static __inline void 162 mv_set_timer_control(uint32_t val) 163 { 164 165 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); 166 } 167 168 static __inline void 169 mv_set_timer(uint32_t timer, uint32_t val) 170 { 171 172 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); 173 } 174 175 static void 176 mv_watchdog_enable(void) 177 { 178 uint32_t val, irq_cause; 179 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) 180 uint32_t irq_mask; 181 #endif 182 183 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 184 irq_cause &= IRQ_TIMER_WD_CLR; 185 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 186 187 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 188 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 189 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 190 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 191 192 val = read_cpu_misc(RSTOUTn_MASK); 193 val &= ~RSTOUTn_MASK_WD; 194 write_cpu_misc(RSTOUTn_MASK, val); 195 #else 196 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 197 irq_mask |= IRQ_TIMER_WD_MASK; 198 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 199 200 val = read_cpu_ctrl(RSTOUTn_MASK); 201 val |= WD_RST_OUT_EN; 202 write_cpu_ctrl(RSTOUTn_MASK, val); 203 #endif 204 205 val = mv_get_timer_control(); 206 #if defined(SOC_MV_ARMADA38X) 207 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; 208 #elif defined(SOC_MV_ARMADAXP) 209 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 210 #else 211 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 212 #endif 213 mv_set_timer_control(val); 214 } 215 216 static void 217 mv_watchdog_disable(void) 218 { 219 uint32_t val, irq_cause; 220 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) 221 uint32_t irq_mask; 222 #endif 223 224 val = mv_get_timer_control(); 225 #if defined(SOC_MV_ARMADA38X) 226 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 227 #else 228 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 229 #endif 230 mv_set_timer_control(val); 231 232 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 233 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 234 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 235 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 236 237 val = read_cpu_misc(RSTOUTn_MASK); 238 val |= RSTOUTn_MASK_WD; 239 write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD); 240 #else 241 val = read_cpu_ctrl(RSTOUTn_MASK); 242 val &= ~WD_RST_OUT_EN; 243 write_cpu_ctrl(RSTOUTn_MASK, val); 244 245 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 246 irq_mask &= ~(IRQ_TIMER_WD_MASK); 247 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 248 #endif 249 250 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 251 irq_cause &= IRQ_TIMER_WD_CLR; 252 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 253 } 254 255 /* 256 * Watchdog event handler. 257 */ 258 static void 259 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 260 { 261 struct mv_wdt_softc *sc; 262 uint64_t ns; 263 uint64_t ticks; 264 265 sc = arg; 266 mtx_lock(&sc->wdt_mtx); 267 if (cmd == 0) 268 mv_watchdog_disable(); 269 else { 270 /* 271 * Watchdog timeout is in nanosecs, calculation according to 272 * watchdog(9) 273 */ 274 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 275 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000; 276 if (ticks > MAX_WATCHDOG_TICKS) 277 mv_watchdog_disable(); 278 else { 279 mv_set_timer(WATCHDOG_TIMER, ticks); 280 mv_watchdog_enable(); 281 *error = 0; 282 } 283 } 284 mtx_unlock(&sc->wdt_mtx); 285 } 286