1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/kdb.h> 43 #include <sys/timeet.h> 44 #include <sys/timetc.h> 45 #include <sys/watchdog.h> 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 #define WD_RST_OUT_EN 0x00000002 58 59 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 60 61 struct mv_wdt_config { 62 enum soc_family wdt_soc; 63 uint32_t wdt_timer; 64 void (*wdt_enable)(void); 65 void (*wdt_disable)(void); 66 unsigned int wdt_clock_src; 67 }; 68 69 static void mv_wdt_enable_armv5(void); 70 static void mv_wdt_enable_armada_38x(void); 71 static void mv_wdt_enable_armada_xp(void); 72 static inline void mv_wdt_enable_armada_38x_xp_helper(void); 73 74 static void mv_wdt_disable_armv5(void); 75 static void mv_wdt_disable_armada_38x(void); 76 static void mv_wdt_disable_armada_xp(void); 77 78 static struct mv_wdt_config mv_wdt_armada_38x_config = { 79 .wdt_soc = MV_SOC_ARMADA_38X, 80 .wdt_timer = 4, 81 .wdt_enable = &mv_wdt_enable_armada_38x, 82 .wdt_disable = &mv_wdt_disable_armada_38x, 83 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 84 }; 85 86 static struct mv_wdt_config mv_wdt_armada_xp_config = { 87 .wdt_soc = MV_SOC_ARMADA_XP, 88 .wdt_timer = 2, 89 .wdt_enable = &mv_wdt_enable_armada_xp, 90 .wdt_disable = &mv_wdt_disable_armada_xp, 91 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 92 }; 93 94 static struct mv_wdt_config mv_wdt_armv5_config = { 95 .wdt_soc = MV_SOC_ARMV5, 96 .wdt_timer = 2, 97 .wdt_enable = &mv_wdt_enable_armv5, 98 .wdt_disable = &mv_wdt_disable_armv5, 99 .wdt_clock_src = 0, 100 }; 101 102 struct mv_wdt_softc { 103 struct resource * wdt_res; 104 struct mtx wdt_mtx; 105 struct mv_wdt_config * wdt_config; 106 }; 107 108 static struct resource_spec mv_wdt_spec[] = { 109 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 110 { -1, 0 } 111 }; 112 113 static struct ofw_compat_data mv_wdt_compat[] = { 114 {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config}, 115 {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config}, 116 {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config}, 117 {NULL, (uintptr_t)NULL} 118 }; 119 120 static struct mv_wdt_softc *wdt_softc = NULL; 121 int timers_initialized = 0; 122 123 static int mv_wdt_probe(device_t); 124 static int mv_wdt_attach(device_t); 125 126 static uint32_t mv_get_timer_control(void); 127 static void mv_set_timer_control(uint32_t); 128 static void mv_set_timer(uint32_t, uint32_t); 129 130 static void mv_watchdog_event(void *, unsigned int, int *); 131 132 static device_method_t mv_wdt_methods[] = { 133 DEVMETHOD(device_probe, mv_wdt_probe), 134 DEVMETHOD(device_attach, mv_wdt_attach), 135 { 0, 0 } 136 }; 137 138 static driver_t mv_wdt_driver = { 139 "wdt", 140 mv_wdt_methods, 141 sizeof(struct mv_wdt_softc), 142 }; 143 144 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, 0, 0); 145 146 static int 147 mv_wdt_probe(device_t dev) 148 { 149 150 if (!ofw_bus_status_okay(dev)) 151 return (ENXIO); 152 153 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) 154 return (ENXIO); 155 156 device_set_desc(dev, "Marvell Watchdog Timer"); 157 return (0); 158 } 159 160 static int 161 mv_wdt_attach(device_t dev) 162 { 163 struct mv_wdt_softc *sc; 164 int error; 165 166 if (wdt_softc != NULL) 167 return (ENXIO); 168 169 sc = device_get_softc(dev); 170 wdt_softc = sc; 171 172 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); 173 if (error) { 174 device_printf(dev, "could not allocate resources\n"); 175 return (ENXIO); 176 } 177 178 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); 179 180 sc->wdt_config = (struct mv_wdt_config *) 181 ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data; 182 183 if (sc->wdt_config->wdt_clock_src == 0) 184 sc->wdt_config->wdt_clock_src = get_tclk(); 185 186 if (wdt_softc->wdt_config->wdt_disable != NULL) 187 wdt_softc->wdt_config->wdt_disable(); 188 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 189 190 return (0); 191 } 192 193 static __inline uint32_t 194 mv_get_timer_control(void) 195 { 196 197 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); 198 } 199 200 static __inline void 201 mv_set_timer_control(uint32_t val) 202 { 203 204 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); 205 } 206 207 static __inline void 208 mv_set_timer(uint32_t timer, uint32_t val) 209 { 210 211 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); 212 } 213 static void 214 mv_wdt_enable_armv5(void) 215 { 216 uint32_t val, irq_cause, irq_mask; 217 218 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 219 irq_cause &= IRQ_TIMER_WD_CLR; 220 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 221 222 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 223 irq_mask |= IRQ_TIMER_WD_MASK; 224 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 225 226 val = read_cpu_ctrl(RSTOUTn_MASK); 227 val |= WD_RST_OUT_EN; 228 write_cpu_ctrl(RSTOUTn_MASK, val); 229 230 val = mv_get_timer_control(); 231 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 232 mv_set_timer_control(val); 233 } 234 235 static inline void 236 mv_wdt_enable_armada_38x_xp_helper(void) 237 { 238 uint32_t val, irq_cause; 239 240 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 241 irq_cause &= IRQ_TIMER_WD_CLR; 242 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 243 244 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 245 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 246 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 247 248 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 249 val &= ~RSTOUTn_MASK_WD; 250 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 251 } 252 253 static void 254 mv_wdt_enable_armada_38x(void) 255 { 256 uint32_t val, irq_cause; 257 258 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 259 irq_cause &= IRQ_TIMER_WD_CLR; 260 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 261 262 mv_wdt_enable_armada_38x_xp_helper(); 263 264 val = mv_get_timer_control(); 265 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; 266 mv_set_timer_control(val); 267 } 268 269 static void 270 mv_wdt_enable_armada_xp(void) 271 { 272 uint32_t val, irq_cause; 273 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP); 274 irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP; 275 write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause); 276 277 mv_wdt_enable_armada_38x_xp_helper(); 278 279 val = mv_get_timer_control(); 280 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 281 mv_set_timer_control(val); 282 } 283 284 static void 285 mv_wdt_disable_armv5(void) 286 { 287 uint32_t val, irq_cause, irq_mask; 288 289 val = mv_get_timer_control(); 290 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 291 mv_set_timer_control(val); 292 293 val = read_cpu_ctrl(RSTOUTn_MASK); 294 val &= ~WD_RST_OUT_EN; 295 write_cpu_ctrl(RSTOUTn_MASK, val); 296 297 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 298 irq_mask &= ~(IRQ_TIMER_WD_MASK); 299 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 300 301 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 302 irq_cause &= IRQ_TIMER_WD_CLR; 303 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 304 } 305 306 static __inline void 307 mv_wdt_disable_armada_38x_xp_helper(void) 308 { 309 uint32_t val; 310 311 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 312 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 313 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 314 315 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 316 val |= RSTOUTn_MASK_WD; 317 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 318 } 319 320 static void 321 mv_wdt_disable_armada_38x(void) 322 { 323 uint32_t val; 324 325 val = mv_get_timer_control(); 326 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 327 mv_set_timer_control(val); 328 329 mv_wdt_disable_armada_38x_xp_helper(); 330 } 331 332 static void 333 mv_wdt_disable_armada_xp(void) 334 { 335 uint32_t val; 336 337 val = mv_get_timer_control(); 338 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 339 mv_set_timer_control(val); 340 341 mv_wdt_disable_armada_38x_xp_helper(); 342 } 343 344 /* 345 * Watchdog event handler. 346 */ 347 static void 348 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 349 { 350 struct mv_wdt_softc *sc; 351 uint64_t ns; 352 uint64_t ticks; 353 354 sc = arg; 355 mtx_lock(&sc->wdt_mtx); 356 if (cmd == 0) { 357 if (wdt_softc->wdt_config->wdt_disable != NULL) 358 wdt_softc->wdt_config->wdt_disable(); 359 } else { 360 /* 361 * Watchdog timeout is in nanosecs, calculation according to 362 * watchdog(9) 363 */ 364 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 365 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000; 366 if (ticks > MAX_WATCHDOG_TICKS) { 367 if (wdt_softc->wdt_config->wdt_disable != NULL) 368 wdt_softc->wdt_config->wdt_disable(); 369 } 370 else { 371 mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks); 372 if (wdt_softc->wdt_config->wdt_enable != NULL) 373 wdt_softc->wdt_config->wdt_enable(); 374 *error = 0; 375 } 376 } 377 mtx_unlock(&sc->wdt_mtx); 378 } 379