1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family 12-bit Analog to Digital Converter (ADC) 29 * Chapter 37, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 54 #include <arm/freescale/vybrid/vf_common.h> 55 #include <arm/freescale/vybrid/vf_adc.h> 56 57 #define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */ 58 #define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */ 59 #define HC_AIEN (1 << 7) /* Conversion Complete Int Control */ 60 #define HC_ADCH_M 0x1f /* Input Channel Select Mask */ 61 #define HC_ADCH_S 0 /* Input Channel Select Shift */ 62 #define ADC_HS 0x08 /* Status register for HW triggers */ 63 #define HS_COCO0 (1 << 0) /* Conversion Complete Flag */ 64 #define HS_COCO1 (1 << 1) /* Conversion Complete Flag */ 65 #define ADC_R0 0x0C /* Data result reg for HW triggers */ 66 #define ADC_R1 0x10 /* Data result reg for HW triggers */ 67 #define ADC_CFG 0x14 /* Configuration register */ 68 #define CFG_OVWREN (1 << 16) /* Data Overwrite Enable */ 69 #define CFG_AVGS_M 0x3 /* Hardware Average select Mask */ 70 #define CFG_AVGS_S 14 /* Hardware Average select Shift */ 71 #define CFG_ADTRG (1 << 13) /* Conversion Trigger Select */ 72 #define CFG_REFSEL_M 0x3 /* Voltage Reference Select Mask */ 73 #define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */ 74 #define CFG_ADHSC (1 << 10) /* High Speed Configuration */ 75 #define CFG_ADSTS_M 0x3 /* Defines the sample time duration */ 76 #define CFG_ADSTS_S 8 /* Defines the sample time duration */ 77 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration */ 78 #define CFG_ADIV_M 0x3 /* Clock Divide Select */ 79 #define CFG_ADIV_S 5 /* Clock Divide Select */ 80 #define CFG_ADLSMP (1 << 4) /* Long Sample Time Configuration */ 81 #define CFG_MODE_M 0x3 /* Conversion Mode Selection Mask */ 82 #define CFG_MODE_S 2 /* Conversion Mode Selection Shift */ 83 #define CFG_MODE_12 0x2 /* 12-bit mode */ 84 #define CFG_ADICLK_M 0x3 /* Input Clock Select Mask */ 85 #define CFG_ADICLK_S 0 /* Input Clock Select Shift */ 86 #define ADC_GC 0x18 /* General control register */ 87 #define GC_CAL (1 << 7) /* Calibration */ 88 #define GC_ADCO (1 << 6) /* Continuous Conversion Enable */ 89 #define GC_AVGE (1 << 5) /* Hardware average enable */ 90 #define GC_ACFE (1 << 4) /* Compare Function Enable */ 91 #define GC_ACFGT (1 << 3) /* Compare Function Greater Than En */ 92 #define GC_ACREN (1 << 2) /* Compare Function Range En */ 93 #define GC_DMAEN (1 << 1) /* DMA Enable */ 94 #define GC_ADACKEN (1 << 0) /* Asynchronous clock output enable */ 95 #define ADC_GS 0x1C /* General status register */ 96 #define GS_AWKST (1 << 2) /* Asynchronous wakeup int status */ 97 #define GS_CALF (1 << 1) /* Calibration Failed Flag */ 98 #define GS_ADACT (1 << 0) /* Conversion Active */ 99 #define ADC_CV 0x20 /* Compare value register */ 100 #define CV_CV2_M 0xfff /* Compare Value 2 Mask */ 101 #define CV_CV2_S 16 /* Compare Value 2 Shift */ 102 #define CV_CV1_M 0xfff /* Compare Value 1 Mask */ 103 #define CV_CV1_S 0 /* Compare Value 1 Shift */ 104 #define ADC_OFS 0x24 /* Offset correction value register */ 105 #define OFS_SIGN 12 /* Sign bit */ 106 #define OFS_M 0xfff /* Offset value Mask */ 107 #define OFS_S 0 /* Offset value Shift */ 108 #define ADC_CAL 0x28 /* Calibration value register */ 109 #define CAL_CODE_M 0xf /* Calibration Result Value Mask */ 110 #define CAL_CODE_S 0 /* Calibration Result Value Shift */ 111 #define ADC_PCTL 0x30 /* Pin control register */ 112 113 struct adc_softc { 114 struct resource *res[2]; 115 bus_space_tag_t bst; 116 bus_space_handle_t bsh; 117 void *ih; 118 }; 119 120 struct adc_softc *adc_sc; 121 122 static struct resource_spec adc_spec[] = { 123 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 124 { SYS_RES_IRQ, 0, RF_ACTIVE }, 125 { -1, 0 } 126 }; 127 128 static int 129 adc_probe(device_t dev) 130 { 131 132 if (!ofw_bus_status_okay(dev)) 133 return (ENXIO); 134 135 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc")) 136 return (ENXIO); 137 138 device_set_desc(dev, "Vybrid Family " 139 "12-bit Analog to Digital Converter"); 140 return (BUS_PROBE_DEFAULT); 141 } 142 143 static void 144 adc_intr(void *arg) 145 { 146 struct adc_softc *sc; 147 148 sc = arg; 149 150 /* Conversation complete */ 151 } 152 153 uint32_t 154 adc_read(void) 155 { 156 struct adc_softc *sc; 157 158 sc = adc_sc; 159 if (sc == NULL) 160 return (0); 161 162 return (READ4(sc, ADC_R0)); 163 } 164 165 uint32_t 166 adc_enable(int channel) 167 { 168 struct adc_softc *sc; 169 int reg; 170 171 sc = adc_sc; 172 if (sc == NULL) 173 return (1); 174 175 reg = READ4(sc, ADC_HC0); 176 reg &= ~(HC_ADCH_M << HC_ADCH_S); 177 reg |= (channel << HC_ADCH_S); 178 WRITE4(sc, ADC_HC0, reg); 179 180 return (0); 181 } 182 183 static int 184 adc_attach(device_t dev) 185 { 186 struct adc_softc *sc; 187 int err; 188 int reg; 189 190 sc = device_get_softc(dev); 191 192 if (bus_alloc_resources(dev, adc_spec, sc->res)) { 193 device_printf(dev, "could not allocate resources\n"); 194 return (ENXIO); 195 } 196 197 /* Memory interface */ 198 sc->bst = rman_get_bustag(sc->res[0]); 199 sc->bsh = rman_get_bushandle(sc->res[0]); 200 201 adc_sc = sc; 202 203 /* Setup interrupt handler */ 204 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 205 NULL, adc_intr, sc, &sc->ih); 206 if (err) { 207 device_printf(dev, "Unable to alloc interrupt resource.\n"); 208 return (ENXIO); 209 } 210 211 /* Configure 12-bit mode */ 212 reg = READ4(sc, ADC_CFG); 213 reg &= ~(CFG_MODE_M << CFG_MODE_S); 214 reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */ 215 WRITE4(sc, ADC_CFG, reg); 216 217 /* Configure for continuous conversion */ 218 reg = READ4(sc, ADC_GC); 219 reg |= (GC_ADCO | GC_AVGE); 220 WRITE4(sc, ADC_GC, reg); 221 222 /* Disable interrupts */ 223 reg = READ4(sc, ADC_HC0); 224 reg &= HC_AIEN; 225 WRITE4(sc, ADC_HC0, reg); 226 227 return (0); 228 } 229 230 static device_method_t adc_methods[] = { 231 DEVMETHOD(device_probe, adc_probe), 232 DEVMETHOD(device_attach, adc_attach), 233 { 0, 0 } 234 }; 235 236 static driver_t adc_driver = { 237 "adc", 238 adc_methods, 239 sizeof(struct adc_softc), 240 }; 241 242 static devclass_t adc_devclass; 243 244 DRIVER_MODULE(adc, simplebus, adc_driver, adc_devclass, 0, 0); 245