1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_platform.h" 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/reboot.h> 35 #include <sys/devmap.h> 36 37 #include <vm/vm.h> 38 #include <vm/pmap.h> 39 40 #include <machine/armreg.h> 41 #include <machine/bus.h> 42 #include <machine/cpu.h> 43 #include <machine/machdep.h> 44 45 #include <arm/freescale/imx/imx_machdep.h> 46 #include <arm/freescale/imx/imx_wdogreg.h> 47 48 SYSCTL_NODE(_hw, OID_AUTO, imx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 49 "i.MX container"); 50 51 static int last_reset_status; 52 SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD, 53 &last_reset_status, 0, "Last reset status register"); 54 55 SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD, 56 "unknown", 0, "Last reset reason"); 57 58 /* 59 * This code which manipulates the watchdog hardware is here to implement 60 * cpu_reset() because the watchdog is the only way for software to reset the 61 * chip. Why here and not in imx_wdog.c? Because there's no requirement that 62 * the watchdog driver be compiled in, but it's nice to be able to reboot even 63 * if it's not. 64 */ 65 void 66 imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr) 67 { 68 volatile uint16_t cr, *pcr; 69 70 if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) { 71 printf("imx_wdog_cpu_reset(): " 72 "cannot find control register... locking up now."); 73 for (;;) 74 cpu_spinwait(); 75 } 76 cr = *pcr; 77 78 /* 79 * If the watchdog hardware has been set up to trigger an external reset 80 * signal on watchdog timeout, then we do software-requested rebooting 81 * the same way, by asserting the external reset signal. 82 * 83 * Asserting external reset is supposed to result in some external 84 * component asserting the POR pin on the SoC, possibly after adjusting 85 * and stabilizing system voltages, or taking other system-wide reset 86 * actions. Just in case there is some kind of misconfiguration, we 87 * hang out and do nothing for a full second, then continue on into 88 * the code to assert a software reset as well. 89 */ 90 if (cr & WDOG_CR_WDT) { 91 cr &= ~WDOG_CR_WDA; /* Assert active-low ext reset bit. */ 92 *pcr = cr; 93 DELAY(1000000); 94 printf("imx_wdog_cpu_reset(): " 95 "External reset failed, trying internal cpu-reset\n"); 96 DELAY(10000); /* Time for printf to appear */ 97 } 98 99 /* 100 * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice 101 * within the same cycle of the 32khz clock to reliably trigger the 102 * reset. Writing it 3 times in a row ensures at least 2 of the writes 103 * happen in the same 32k clock cycle. 104 */ 105 cr &= ~WDOG_CR_SRS; /* Assert active-low software reset bit. */ 106 *pcr = cr; 107 *pcr = cr; 108 *pcr = cr; 109 110 /* Reset happens on the next tick of the 32khz clock, wait for it. */ 111 for (;;) 112 cpu_spinwait(); 113 } 114 115 void 116 imx_wdog_init_last_reset(vm_offset_t wdsr_phys) 117 { 118 volatile uint16_t * psr; 119 120 if ((psr = devmap_ptov(wdsr_phys, sizeof(*psr))) == NULL) 121 return; 122 last_reset_status = *psr; 123 if (last_reset_status & WDOG_RSR_SFTW) { 124 sysctl___hw_imx_last_reset_reason.oid_arg1 = "SoftwareReset"; 125 } else if (last_reset_status & WDOG_RSR_TOUT) { 126 sysctl___hw_imx_last_reset_reason.oid_arg1 = "WatchdogTimeout"; 127 } else if (last_reset_status & WDOG_RSR_POR) { 128 sysctl___hw_imx_last_reset_reason.oid_arg1 = "PowerOnReset"; 129 } 130 } 131