1 /*- 2 * Copyright (c) 2014 Ian Lepore 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Pin mux and pad control driver for imx5 and imx6. 31 * 32 * This driver implements the fdt_pinctrl interface for configuring the gpio and 33 * peripheral pins based on fdt configuration data. 34 * 35 * When the driver attaches, it walks the entire fdt tree and automatically 36 * configures the pins for each device which has a pinctrl-0 property and whose 37 * status is "okay". In addition it implements the fdt_pinctrl_configure() 38 * method which any other driver can call at any time to reconfigure its pins. 39 * 40 * The nature of the fsl,pins property in fdt data makes this driver's job very 41 * easy. Instead of representing each pin and pad configuration using symbolic 42 * properties such as pullup-enable="true" and so on, the data simply contains 43 * the addresses of the registers that control the pins, and the raw values to 44 * store in those registers. 45 * 46 * The imx5 and imx6 SoCs also have a small number of "general purpose 47 * registers" in the iomuxc device which are used to control an assortment 48 * of completely unrelated aspects of SoC behavior. This driver provides other 49 * drivers with direct access to those registers via simple accessor functions. 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/module.h> 57 #include <sys/malloc.h> 58 #include <sys/rman.h> 59 60 #include <machine/bus.h> 61 62 #include <dev/ofw/openfirm.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/fdt/fdt_pinctrl.h> 66 67 #include <arm/freescale/imx/imx_iomuxvar.h> 68 #include <arm/freescale/imx/imx_machdep.h> 69 70 struct iomux_softc { 71 device_t dev; 72 struct resource *mem_res; 73 u_int last_gpregaddr; 74 }; 75 76 static struct iomux_softc *iomux_sc; 77 78 static struct ofw_compat_data compat_data[] = { 79 {"fsl,imx8mq-iomuxc", true}, 80 {"fsl,imx6dl-iomuxc", true}, 81 {"fsl,imx6q-iomuxc", true}, 82 {"fsl,imx6sl-iomuxc", true}, 83 {"fsl,imx6ul-iomuxc", true}, 84 {"fsl,imx6sx-iomuxc", true}, 85 {"fsl,imx53-iomuxc", true}, 86 {"fsl,imx51-iomuxc", true}, 87 {NULL, false}, 88 }; 89 90 /* 91 * Each tuple in an fsl,pins property contains these fields. 92 */ 93 struct pincfg { 94 uint32_t mux_reg; 95 uint32_t padconf_reg; 96 uint32_t input_reg; 97 uint32_t mux_val; 98 uint32_t input_val; 99 uint32_t padconf_val; 100 }; 101 102 #define PADCONF_NONE (1U << 31) /* Do not configure pad. */ 103 #define PADCONF_SION (1U << 30) /* Force SION bit in mux register. */ 104 #define PADMUX_SION (1U << 4) /* The SION bit in the mux register. */ 105 106 static inline uint32_t 107 RD4(struct iomux_softc *sc, bus_size_t off) 108 { 109 110 return (bus_read_4(sc->mem_res, off)); 111 } 112 113 static inline void 114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) 115 { 116 117 bus_write_4(sc->mem_res, off, val); 118 } 119 120 static void 121 iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val) 122 { 123 u_int select, mask, shift, width; 124 125 /* If register and value are zero, there is nothing to configure. */ 126 if (reg == 0 && val == 0) 127 return; 128 129 /* 130 * If the config value has 0xff in the high byte it is encoded: 131 * 31 23 15 7 0 132 * | 0xff | shift | width | select | 133 * We need to mask out the old select value and OR in the new, using a 134 * mask of the given width and shifting the values up by shift. 135 */ 136 if ((val & 0xff000000) == 0xff000000) { 137 select = val & 0x000000ff; 138 width = (val & 0x0000ff00) >> 8; 139 shift = (val & 0x00ff0000) >> 16; 140 mask = ((1u << width) - 1) << shift; 141 val = (RD4(sc, reg) & ~mask) | (select << shift); 142 } 143 WR4(sc, reg, val); 144 } 145 146 static int 147 iomux_configure_pins(device_t dev, phandle_t cfgxref) 148 { 149 struct iomux_softc *sc; 150 struct pincfg *cfgtuples, *cfg; 151 phandle_t cfgnode; 152 int i, ntuples; 153 uint32_t sion; 154 155 sc = device_get_softc(dev); 156 cfgnode = OF_node_from_xref(cfgxref); 157 ntuples = OF_getencprop_alloc_multi(cfgnode, "fsl,pins", 158 sizeof(*cfgtuples), (void **)&cfgtuples); 159 if (ntuples < 0) 160 return (ENOENT); 161 if (ntuples == 0) 162 return (0); /* Empty property is not an error. */ 163 for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) { 164 sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0; 165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); 166 iomux_configure_input(sc, cfg->input_reg, cfg->input_val); 167 if ((cfg->padconf_val & PADCONF_NONE) == 0) 168 WR4(sc, cfg->padconf_reg, cfg->padconf_val); 169 if (bootverbose) { 170 char name[32]; 171 OF_getprop(cfgnode, "name", &name, sizeof(name)); 172 printf("%16s: muxreg 0x%04x muxval 0x%02x " 173 "inpreg 0x%04x inpval 0x%02x " 174 "padreg 0x%04x padval 0x%08x\n", 175 name, cfg->mux_reg, cfg->mux_val | sion, 176 cfg->input_reg, cfg->input_val, 177 cfg->padconf_reg, cfg->padconf_val); 178 } 179 } 180 OF_prop_free(cfgtuples); 181 return (0); 182 } 183 184 static int 185 iomux_probe(device_t dev) 186 { 187 188 if (!ofw_bus_status_okay(dev)) 189 return (ENXIO); 190 191 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 192 return (ENXIO); 193 194 device_set_desc(dev, "Freescale i.MX pin configuration"); 195 return (BUS_PROBE_DEFAULT); 196 } 197 198 static int 199 iomux_detach(device_t dev) 200 { 201 202 /* This device is always present. */ 203 return (EBUSY); 204 } 205 206 static int 207 iomux_attach(device_t dev) 208 { 209 struct iomux_softc * sc; 210 int rid; 211 212 sc = device_get_softc(dev); 213 sc->dev = dev; 214 215 switch (imx_soc_type()) { 216 case IMXSOC_51: 217 sc->last_gpregaddr = 1 * sizeof(uint32_t); 218 break; 219 case IMXSOC_53: 220 sc->last_gpregaddr = 2 * sizeof(uint32_t); 221 break; 222 case IMXSOC_6DL: 223 case IMXSOC_6S: 224 case IMXSOC_6SL: 225 case IMXSOC_6Q: 226 sc->last_gpregaddr = 13 * sizeof(uint32_t); 227 break; 228 case IMXSOC_6UL: 229 sc->last_gpregaddr = 14 * sizeof(uint32_t); 230 break; 231 default: 232 device_printf(dev, "Unknown SoC type\n"); 233 return (ENXIO); 234 } 235 236 rid = 0; 237 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 238 RF_ACTIVE); 239 if (sc->mem_res == NULL) { 240 device_printf(dev, "Cannot allocate memory resources\n"); 241 return (ENXIO); 242 } 243 244 iomux_sc = sc; 245 246 /* 247 * Register as a pinctrl device, and call the convenience function that 248 * walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any 249 * pinctrl-0 property cells whose xref phandle refers to a configuration 250 * that is a child node of our node in the tree. 251 * 252 * The pinctrl bindings documentation specifically mentions that the 253 * pinctrl device itself may have a pinctrl-0 property which contains 254 * static configuration to be applied at device init time. The tree 255 * walk will automatically handle this for us when it passes through our 256 * node in the tree. 257 */ 258 fdt_pinctrl_register(dev, "fsl,pins"); 259 fdt_pinctrl_configure_tree(dev); 260 261 return (0); 262 } 263 264 uint32_t 265 imx_iomux_gpr_get(u_int regaddr) 266 { 267 struct iomux_softc * sc; 268 269 sc = iomux_sc; 270 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 271 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr, 272 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr, 273 sc->last_gpregaddr)); 274 275 return (RD4(iomux_sc, regaddr)); 276 } 277 278 void 279 imx_iomux_gpr_set(u_int regaddr, uint32_t val) 280 { 281 struct iomux_softc * sc; 282 283 sc = iomux_sc; 284 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 285 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr, 286 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr, 287 sc->last_gpregaddr)); 288 289 WR4(iomux_sc, regaddr, val); 290 } 291 292 void 293 imx_iomux_gpr_set_masked(u_int regaddr, uint32_t clrbits, uint32_t setbits) 294 { 295 struct iomux_softc * sc; 296 uint32_t val; 297 298 sc = iomux_sc; 299 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__)); 300 KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr, 301 ("%s bad regaddr %u, max %u", __FUNCTION__, regaddr, 302 sc->last_gpregaddr)); 303 304 val = RD4(iomux_sc, regaddr * 4); 305 val = (val & ~clrbits) | setbits; 306 WR4(iomux_sc, regaddr, val); 307 } 308 309 static device_method_t imx_iomux_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, iomux_probe), 312 DEVMETHOD(device_attach, iomux_attach), 313 DEVMETHOD(device_detach, iomux_detach), 314 315 /* fdt_pinctrl interface */ 316 DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins), 317 318 DEVMETHOD_END 319 }; 320 321 static driver_t imx_iomux_driver = { 322 "imx_iomux", 323 imx_iomux_methods, 324 sizeof(struct iomux_softc), 325 }; 326 327 static devclass_t imx_iomux_devclass; 328 329 EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver, 330 imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE); 331