xref: /freebsd/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 676ea8e1778d671703c8901ea82ad4092b00b24a)
1be9ddf43SLuiz Otavio O Souza /*-
2af3dc4a7SPedro F. Giffuni  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3af3dc4a7SPedro F. Giffuni  *
4be9ddf43SLuiz Otavio O Souza  * Copyright (c) 2001 Tsubai Masanari.
5be9ddf43SLuiz Otavio O Souza  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
6be9ddf43SLuiz Otavio O Souza  * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
70bd904edSIan Lepore  * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
8be9ddf43SLuiz Otavio O Souza  * All rights reserved.
9be9ddf43SLuiz Otavio O Souza  *
10be9ddf43SLuiz Otavio O Souza  * Redistribution and use in source and binary forms, with or without
11be9ddf43SLuiz Otavio O Souza  * modification, are permitted provided that the following conditions
12be9ddf43SLuiz Otavio O Souza  * are met:
13be9ddf43SLuiz Otavio O Souza  * 1. Redistributions of source code must retain the above copyright
14be9ddf43SLuiz Otavio O Souza  *    notice, this list of conditions and the following disclaimer.
15be9ddf43SLuiz Otavio O Souza  * 2. Redistributions in binary form must reproduce the above copyright
16be9ddf43SLuiz Otavio O Souza  *    notice, this list of conditions and the following disclaimer in the
17be9ddf43SLuiz Otavio O Souza  *    documentation and/or other materials provided with the distribution.
18be9ddf43SLuiz Otavio O Souza  *
19be9ddf43SLuiz Otavio O Souza  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20be9ddf43SLuiz Otavio O Souza  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21be9ddf43SLuiz Otavio O Souza  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22be9ddf43SLuiz Otavio O Souza  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23be9ddf43SLuiz Otavio O Souza  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24be9ddf43SLuiz Otavio O Souza  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25be9ddf43SLuiz Otavio O Souza  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26be9ddf43SLuiz Otavio O Souza  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27be9ddf43SLuiz Otavio O Souza  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28be9ddf43SLuiz Otavio O Souza  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29be9ddf43SLuiz Otavio O Souza  * SUCH DAMAGE.
30be9ddf43SLuiz Otavio O Souza  *
31be9ddf43SLuiz Otavio O Souza  */
32be9ddf43SLuiz Otavio O Souza #include <sys/cdefs.h>
33be9ddf43SLuiz Otavio O Souza __FBSDID("$FreeBSD$");
34be9ddf43SLuiz Otavio O Souza 
350bd904edSIan Lepore /*
360bd904edSIan Lepore  * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC.
370bd904edSIan Lepore  *
380bd904edSIan Lepore  * This controller can only perform complete transfers, it does not provide
390bd904edSIan Lepore  * low-level control over sending start/repeat-start/stop sequences on the bus.
400bd904edSIan Lepore  * In addition, bugs in the silicon make it somewhat difficult to perform a
410bd904edSIan Lepore  * repeat-start, and limit the repeat-start to a read following a write on
420bd904edSIan Lepore  * the same slave device.  (The i2c protocol allows a repeat start to change
430bd904edSIan Lepore  * direction or not, and change slave address or not at any time.)
440bd904edSIan Lepore  *
450bd904edSIan Lepore  * The repeat-start bug and workaround are described in a problem report at
460bd904edSIan Lepore  * https://github.com/raspberrypi/linux/issues/254 with the crucial part being
470bd904edSIan Lepore  * in a comment block from a fragment of a GPU i2c driver, containing this:
480bd904edSIan Lepore  *
490bd904edSIan Lepore  * -----------------------------------------------------------------------------
500bd904edSIan Lepore  * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count
510bd904edSIan Lepore  * - in the IDLE state if start is set.
520bd904edSIan Lepore  * -
530bd904edSIan Lepore  * - We want to generate a ReSTART not a STOP at the end of the TX phase. In
540bd904edSIan Lepore  * - order to do that we must ensure the state machine goes RACK1 -> RACK2 ->
550bd904edSIan Lepore  * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1).
560bd904edSIan Lepore  * -
570bd904edSIan Lepore  * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have
580bd904edSIan Lepore  * - already set, ready to be sampled:
590bd904edSIan Lepore  * -  READ ; rw_bit     <= I2CC bit 0 -- must be "read"
600bd904edSIan Lepore  * -  ST;    start      <= I2CC bit 7 -- must be "Go" in order to not issue STOP
610bd904edSIan Lepore  * -  DLEN;  xfer_count <= I2CDLEN    -- must be equal to our read amount
620bd904edSIan Lepore  * -
630bd904edSIan Lepore  * - The plan to do this is:
640bd904edSIan Lepore  * -  1. Start the sub-address write, but don't let it finish
650bd904edSIan Lepore  * -     (keep xfer_count > 0)
660bd904edSIan Lepore  * -  2. Populate READ, DLEN and ST in preparation for ReSTART read sequence
670bd904edSIan Lepore  * -  3. Let TX finish (write the rest of the data)
680bd904edSIan Lepore  * -  4. Read back data as it arrives
690bd904edSIan Lepore  * -----------------------------------------------------------------------------
700bd904edSIan Lepore  *
710bd904edSIan Lepore  * The transfer function below scans the list of messages passed to it, looking
720bd904edSIan Lepore  * for a read following a write to the same slave.  When it finds that, it
730bd904edSIan Lepore  * starts the write without prefilling the tx fifo, which holds xfer_count>0,
740bd904edSIan Lepore  * then presets the direction, length, and start command for the following read,
750bd904edSIan Lepore  * as described above.  Then the tx fifo is filled and the rest of the transfer
760bd904edSIan Lepore  * proceeds as normal, with the controller automatically supplying a
770bd904edSIan Lepore  * repeat-start on the bus when the write operation finishes.
780bd904edSIan Lepore  *
790bd904edSIan Lepore  * XXX I suspect the controller may be able to do a repeat-start on any
800bd904edSIan Lepore  * write->read or write->write transition, even when the slave addresses differ.
810bd904edSIan Lepore  * It's unclear whether the slave address can be prestaged along with the
820bd904edSIan Lepore  * direction and length while the write xfer_count is being held at zero.  In
830bd904edSIan Lepore  * fact, if it can't do this, then it couldn't be used to read EDID data.
840bd904edSIan Lepore  */
850bd904edSIan Lepore 
86be9ddf43SLuiz Otavio O Souza #include <sys/param.h>
87be9ddf43SLuiz Otavio O Souza #include <sys/systm.h>
88be9ddf43SLuiz Otavio O Souza #include <sys/kernel.h>
89be9ddf43SLuiz Otavio O Souza #include <sys/lock.h>
90be9ddf43SLuiz Otavio O Souza #include <sys/module.h>
91be9ddf43SLuiz Otavio O Souza #include <sys/mutex.h>
92be9ddf43SLuiz Otavio O Souza #include <sys/bus.h>
93be9ddf43SLuiz Otavio O Souza #include <machine/resource.h>
94be9ddf43SLuiz Otavio O Souza #include <machine/bus.h>
95be9ddf43SLuiz Otavio O Souza #include <sys/rman.h>
96be9ddf43SLuiz Otavio O Souza #include <sys/sysctl.h>
97be9ddf43SLuiz Otavio O Souza 
98be9ddf43SLuiz Otavio O Souza #include <dev/iicbus/iicbus.h>
99be9ddf43SLuiz Otavio O Souza #include <dev/iicbus/iiconf.h>
100be9ddf43SLuiz Otavio O Souza #include <dev/ofw/ofw_bus.h>
101be9ddf43SLuiz Otavio O Souza #include <dev/ofw/ofw_bus_subr.h>
102be9ddf43SLuiz Otavio O Souza 
103be9ddf43SLuiz Otavio O Souza #include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
104be9ddf43SLuiz Otavio O Souza #include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
105be9ddf43SLuiz Otavio O Souza 
106be9ddf43SLuiz Otavio O Souza #include "iicbus_if.h"
107be9ddf43SLuiz Otavio O Souza 
1089d6eb8bbSOleksandr Tymoshenko static struct ofw_compat_data compat_data[] = {
1099d6eb8bbSOleksandr Tymoshenko 	{"broadcom,bcm2835-bsc",	1},
1109d6eb8bbSOleksandr Tymoshenko 	{"brcm,bcm2708-i2c",		1},
111e9804ab2SOleksandr Tymoshenko 	{"brcm,bcm2835-i2c",		1},
1129d6eb8bbSOleksandr Tymoshenko 	{NULL,				0}
1139d6eb8bbSOleksandr Tymoshenko };
1149d6eb8bbSOleksandr Tymoshenko 
1150bd904edSIan Lepore #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \
1160bd904edSIan Lepore     if ((lvl) <= (sc)->sc_debug) \
1170bd904edSIan Lepore         device_printf((sc)->sc_dev, fmt, ##args)
1180bd904edSIan Lepore 
1190bd904edSIan Lepore #define DEBUGF(sc, lvl, fmt, args...) \
1200bd904edSIan Lepore     if ((lvl) <= (sc)->sc_debug) \
1210bd904edSIan Lepore         printf(fmt, ##args)
1220bd904edSIan Lepore 
123be9ddf43SLuiz Otavio O Souza static void bcm_bsc_intr(void *);
1249e93dfcfSLuiz Otavio O Souza static int bcm_bsc_detach(device_t);
125be9ddf43SLuiz Otavio O Souza 
126be9ddf43SLuiz Otavio O Souza static void
127be9ddf43SLuiz Otavio O Souza bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
128be9ddf43SLuiz Otavio O Souza 	uint32_t value)
129be9ddf43SLuiz Otavio O Souza {
130be9ddf43SLuiz Otavio O Souza 	uint32_t reg;
131be9ddf43SLuiz Otavio O Souza 
132be9ddf43SLuiz Otavio O Souza 	mtx_assert(&sc->sc_mtx, MA_OWNED);
133be9ddf43SLuiz Otavio O Souza 	reg = BCM_BSC_READ(sc, off);
134be9ddf43SLuiz Otavio O Souza 	reg &= ~mask;
135be9ddf43SLuiz Otavio O Souza 	reg |= value;
136be9ddf43SLuiz Otavio O Souza 	BCM_BSC_WRITE(sc, off, reg);
137be9ddf43SLuiz Otavio O Souza }
138be9ddf43SLuiz Otavio O Souza 
139be9ddf43SLuiz Otavio O Souza static int
140be9ddf43SLuiz Otavio O Souza bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
141be9ddf43SLuiz Otavio O Souza {
142be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
143be9ddf43SLuiz Otavio O Souza 	uint32_t clk;
144be9ddf43SLuiz Otavio O Souza 
145be9ddf43SLuiz Otavio O Souza 	sc = (struct bcm_bsc_softc *)arg1;
146be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
147be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
148be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
149be9ddf43SLuiz Otavio O Souza 	clk &= 0xffff;
150be9ddf43SLuiz Otavio O Souza 	if (clk == 0)
151be9ddf43SLuiz Otavio O Souza 		clk = 32768;
152be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_CORE_CLK / clk;
153be9ddf43SLuiz Otavio O Souza 
1549e93dfcfSLuiz Otavio O Souza 	return (sysctl_handle_int(oidp, &clk, 0, req));
155be9ddf43SLuiz Otavio O Souza }
156be9ddf43SLuiz Otavio O Souza 
157be9ddf43SLuiz Otavio O Souza static int
158be9ddf43SLuiz Otavio O Souza bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
159be9ddf43SLuiz Otavio O Souza {
160be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
161be9ddf43SLuiz Otavio O Souza 	uint32_t clkt;
162be9ddf43SLuiz Otavio O Souza 	int error;
163be9ddf43SLuiz Otavio O Souza 
164be9ddf43SLuiz Otavio O Souza 	sc = (struct bcm_bsc_softc *)arg1;
165be9ddf43SLuiz Otavio O Souza 
166be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
167be9ddf43SLuiz Otavio O Souza 	clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
168be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
169be9ddf43SLuiz Otavio O Souza 	clkt &= 0xffff;
170be9ddf43SLuiz Otavio O Souza 	error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
171be9ddf43SLuiz Otavio O Souza 	if (error != 0 || req->newptr == NULL)
172be9ddf43SLuiz Otavio O Souza 		return (error);
173be9ddf43SLuiz Otavio O Souza 
174be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
175be9ddf43SLuiz Otavio O Souza 	BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
176be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
177be9ddf43SLuiz Otavio O Souza 
178be9ddf43SLuiz Otavio O Souza 	return (0);
179be9ddf43SLuiz Otavio O Souza }
180be9ddf43SLuiz Otavio O Souza 
181be9ddf43SLuiz Otavio O Souza static int
182be9ddf43SLuiz Otavio O Souza bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
183be9ddf43SLuiz Otavio O Souza {
184be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
185be9ddf43SLuiz Otavio O Souza 	uint32_t clk, reg;
186be9ddf43SLuiz Otavio O Souza 	int error;
187be9ddf43SLuiz Otavio O Souza 
188be9ddf43SLuiz Otavio O Souza 	sc = (struct bcm_bsc_softc *)arg1;
189be9ddf43SLuiz Otavio O Souza 
190be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
191be9ddf43SLuiz Otavio O Souza 	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
192be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
193be9ddf43SLuiz Otavio O Souza 	reg >>= 16;
194be9ddf43SLuiz Otavio O Souza 	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
195be9ddf43SLuiz Otavio O Souza 	if (error != 0 || req->newptr == NULL)
196be9ddf43SLuiz Otavio O Souza 		return (error);
197be9ddf43SLuiz Otavio O Souza 
198be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
199be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
200be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_CORE_CLK / clk;
201be9ddf43SLuiz Otavio O Souza 	if (reg > clk / 2)
202be9ddf43SLuiz Otavio O Souza 		reg = clk / 2 - 1;
203be9ddf43SLuiz Otavio O Souza 	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
204be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
205be9ddf43SLuiz Otavio O Souza 
206be9ddf43SLuiz Otavio O Souza 	return (0);
207be9ddf43SLuiz Otavio O Souza }
208be9ddf43SLuiz Otavio O Souza 
209be9ddf43SLuiz Otavio O Souza static int
210be9ddf43SLuiz Otavio O Souza bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
211be9ddf43SLuiz Otavio O Souza {
212be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
213be9ddf43SLuiz Otavio O Souza 	uint32_t clk, reg;
214be9ddf43SLuiz Otavio O Souza 	int error;
215be9ddf43SLuiz Otavio O Souza 
216be9ddf43SLuiz Otavio O Souza 	sc = (struct bcm_bsc_softc *)arg1;
217be9ddf43SLuiz Otavio O Souza 
218be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
219be9ddf43SLuiz Otavio O Souza 	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
220be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
221be9ddf43SLuiz Otavio O Souza 	reg &= 0xffff;
222be9ddf43SLuiz Otavio O Souza 	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
223be9ddf43SLuiz Otavio O Souza 	if (error != 0 || req->newptr == NULL)
224be9ddf43SLuiz Otavio O Souza 		return (error);
225be9ddf43SLuiz Otavio O Souza 
226be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
227be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
228be9ddf43SLuiz Otavio O Souza 	clk = BCM_BSC_CORE_CLK / clk;
229be9ddf43SLuiz Otavio O Souza 	if (reg > clk / 2)
230be9ddf43SLuiz Otavio O Souza 		reg = clk / 2 - 1;
231be9ddf43SLuiz Otavio O Souza 	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
232be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
233be9ddf43SLuiz Otavio O Souza 
234be9ddf43SLuiz Otavio O Souza 	return (0);
235be9ddf43SLuiz Otavio O Souza }
236be9ddf43SLuiz Otavio O Souza 
237be9ddf43SLuiz Otavio O Souza static void
238be9ddf43SLuiz Otavio O Souza bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
239be9ddf43SLuiz Otavio O Souza {
240be9ddf43SLuiz Otavio O Souza 	struct sysctl_ctx_list *ctx;
241be9ddf43SLuiz Otavio O Souza 	struct sysctl_oid *tree_node;
242be9ddf43SLuiz Otavio O Souza 	struct sysctl_oid_list *tree;
243be9ddf43SLuiz Otavio O Souza 
244be9ddf43SLuiz Otavio O Souza 	/*
245be9ddf43SLuiz Otavio O Souza 	 * Add system sysctl tree/handlers.
246be9ddf43SLuiz Otavio O Souza 	 */
247be9ddf43SLuiz Otavio O Souza 	ctx = device_get_sysctl_ctx(sc->sc_dev);
248be9ddf43SLuiz Otavio O Souza 	tree_node = device_get_sysctl_tree(sc->sc_dev);
249be9ddf43SLuiz Otavio O Souza 	tree = SYSCTL_CHILDREN(tree_node);
2509e93dfcfSLuiz Otavio O Souza 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
2517029da5cSPawel Biernacki 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
2527029da5cSPawel Biernacki 	    sc, sizeof(*sc),
253be9ddf43SLuiz Otavio O Souza 	    bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
254be9ddf43SLuiz Otavio O Souza 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
2557029da5cSPawel Biernacki 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
2567029da5cSPawel Biernacki 	    sc, sizeof(*sc),
257be9ddf43SLuiz Otavio O Souza 	    bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
258be9ddf43SLuiz Otavio O Souza 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
2597029da5cSPawel Biernacki 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
2607029da5cSPawel Biernacki 	    sc, sizeof(*sc),
261be9ddf43SLuiz Otavio O Souza 	    bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
262be9ddf43SLuiz Otavio O Souza 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
2637029da5cSPawel Biernacki 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
2647029da5cSPawel Biernacki 	    sc, sizeof(*sc),
265be9ddf43SLuiz Otavio O Souza 	    bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
2660bd904edSIan Lepore 	SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug",
2670bd904edSIan Lepore 	    CTLFLAG_RWTUN, &sc->sc_debug, 0,
2680bd904edSIan Lepore 	    "Enable debug; 1=reads/writes, 2=add starts/stops");
269be9ddf43SLuiz Otavio O Souza }
270be9ddf43SLuiz Otavio O Souza 
271be9ddf43SLuiz Otavio O Souza static void
272be9ddf43SLuiz Otavio O Souza bcm_bsc_reset(struct bcm_bsc_softc *sc)
273be9ddf43SLuiz Otavio O Souza {
274be9ddf43SLuiz Otavio O Souza 
275e50c6241SLuiz Otavio O Souza 	/* Enable the BSC Controller, disable interrupts. */
276e50c6241SLuiz Otavio O Souza 	BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
277be9ddf43SLuiz Otavio O Souza 	/* Clear pending interrupts. */
278be9ddf43SLuiz Otavio O Souza 	BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
279be9ddf43SLuiz Otavio O Souza 	    BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
280be9ddf43SLuiz Otavio O Souza 	/* Clear the FIFO. */
281be9ddf43SLuiz Otavio O Souza 	bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
282be9ddf43SLuiz Otavio O Souza 	    BCM_BSC_CTRL_CLEAR0);
283be9ddf43SLuiz Otavio O Souza }
284be9ddf43SLuiz Otavio O Souza 
285be9ddf43SLuiz Otavio O Souza static int
286be9ddf43SLuiz Otavio O Souza bcm_bsc_probe(device_t dev)
287be9ddf43SLuiz Otavio O Souza {
288be9ddf43SLuiz Otavio O Souza 
289add35ed5SIan Lepore 	if (!ofw_bus_status_okay(dev))
290add35ed5SIan Lepore 		return (ENXIO);
291add35ed5SIan Lepore 
2929d6eb8bbSOleksandr Tymoshenko 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
293be9ddf43SLuiz Otavio O Souza 		return (ENXIO);
294be9ddf43SLuiz Otavio O Souza 
295be9ddf43SLuiz Otavio O Souza 	device_set_desc(dev, "BCM2708/2835 BSC controller");
296be9ddf43SLuiz Otavio O Souza 
297be9ddf43SLuiz Otavio O Souza 	return (BUS_PROBE_DEFAULT);
298be9ddf43SLuiz Otavio O Souza }
299be9ddf43SLuiz Otavio O Souza 
300be9ddf43SLuiz Otavio O Souza static int
301be9ddf43SLuiz Otavio O Souza bcm_bsc_attach(device_t dev)
302be9ddf43SLuiz Otavio O Souza {
303be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
30491cc58afSOleksandr Tymoshenko 	int rid;
305be9ddf43SLuiz Otavio O Souza 
306be9ddf43SLuiz Otavio O Souza 	sc = device_get_softc(dev);
307be9ddf43SLuiz Otavio O Souza 	sc->sc_dev = dev;
308be9ddf43SLuiz Otavio O Souza 
309be9ddf43SLuiz Otavio O Souza 	rid = 0;
310be9ddf43SLuiz Otavio O Souza 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
311be9ddf43SLuiz Otavio O Souza 	    RF_ACTIVE);
312be9ddf43SLuiz Otavio O Souza 	if (!sc->sc_mem_res) {
313be9ddf43SLuiz Otavio O Souza 		device_printf(dev, "cannot allocate memory window\n");
314be9ddf43SLuiz Otavio O Souza 		return (ENXIO);
315be9ddf43SLuiz Otavio O Souza 	}
316be9ddf43SLuiz Otavio O Souza 
317be9ddf43SLuiz Otavio O Souza 	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
318be9ddf43SLuiz Otavio O Souza 	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
319be9ddf43SLuiz Otavio O Souza 
320be9ddf43SLuiz Otavio O Souza 	rid = 0;
321be9ddf43SLuiz Otavio O Souza 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
322be9ddf43SLuiz Otavio O Souza 	    RF_ACTIVE | RF_SHAREABLE);
323be9ddf43SLuiz Otavio O Souza 	if (!sc->sc_irq_res) {
324be9ddf43SLuiz Otavio O Souza 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
325be9ddf43SLuiz Otavio O Souza 		device_printf(dev, "cannot allocate interrupt\n");
326be9ddf43SLuiz Otavio O Souza 		return (ENXIO);
327be9ddf43SLuiz Otavio O Souza 	}
328be9ddf43SLuiz Otavio O Souza 
329be9ddf43SLuiz Otavio O Souza 	/* Hook up our interrupt handler. */
330be9ddf43SLuiz Otavio O Souza 	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
331be9ddf43SLuiz Otavio O Souza 	    NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
332be9ddf43SLuiz Otavio O Souza 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
333be9ddf43SLuiz Otavio O Souza 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
334be9ddf43SLuiz Otavio O Souza 		device_printf(dev, "cannot setup the interrupt handler\n");
335be9ddf43SLuiz Otavio O Souza 		return (ENXIO);
336be9ddf43SLuiz Otavio O Souza 	}
337be9ddf43SLuiz Otavio O Souza 
338be9ddf43SLuiz Otavio O Souza 	mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
339be9ddf43SLuiz Otavio O Souza 
340be9ddf43SLuiz Otavio O Souza 	bcm_bsc_sysctl_init(sc);
341be9ddf43SLuiz Otavio O Souza 
342be9ddf43SLuiz Otavio O Souza 	/* Enable the BSC controller.  Flush the FIFO. */
343be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
344be9ddf43SLuiz Otavio O Souza 	bcm_bsc_reset(sc);
345be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
346be9ddf43SLuiz Otavio O Souza 
3479e93dfcfSLuiz Otavio O Souza 	sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
3489e93dfcfSLuiz Otavio O Souza 	if (sc->sc_iicbus == NULL) {
3499e93dfcfSLuiz Otavio O Souza 		bcm_bsc_detach(dev);
3509e93dfcfSLuiz Otavio O Souza 		return (ENXIO);
3519e93dfcfSLuiz Otavio O Souza 	}
352be9ddf43SLuiz Otavio O Souza 
3531e4042d4SIan Lepore 	/* Probe and attach the iicbus when interrupts are available. */
3549f07ef76SWarner Losh 	return (bus_delayed_attach_children(dev));
355be9ddf43SLuiz Otavio O Souza }
356be9ddf43SLuiz Otavio O Souza 
357be9ddf43SLuiz Otavio O Souza static int
358be9ddf43SLuiz Otavio O Souza bcm_bsc_detach(device_t dev)
359be9ddf43SLuiz Otavio O Souza {
360be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
361be9ddf43SLuiz Otavio O Souza 
362be9ddf43SLuiz Otavio O Souza 	bus_generic_detach(dev);
363be9ddf43SLuiz Otavio O Souza 
364be9ddf43SLuiz Otavio O Souza 	sc = device_get_softc(dev);
3650bd904edSIan Lepore 	if (sc->sc_iicbus != NULL)
3660bd904edSIan Lepore 		device_delete_child(dev, sc->sc_iicbus);
367be9ddf43SLuiz Otavio O Souza 	mtx_destroy(&sc->sc_mtx);
368be9ddf43SLuiz Otavio O Souza 	if (sc->sc_intrhand)
369be9ddf43SLuiz Otavio O Souza 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
370be9ddf43SLuiz Otavio O Souza 	if (sc->sc_irq_res)
371be9ddf43SLuiz Otavio O Souza 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
372be9ddf43SLuiz Otavio O Souza 	if (sc->sc_mem_res)
373be9ddf43SLuiz Otavio O Souza 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
374be9ddf43SLuiz Otavio O Souza 
375be9ddf43SLuiz Otavio O Souza 	return (0);
376be9ddf43SLuiz Otavio O Souza }
377be9ddf43SLuiz Otavio O Souza 
378be9ddf43SLuiz Otavio O Souza static void
3790bd904edSIan Lepore bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc)
3800bd904edSIan Lepore {
3810bd904edSIan Lepore 	uint32_t status;
3820bd904edSIan Lepore 
3830bd904edSIan Lepore 	/* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */
3840bd904edSIan Lepore 	do {
3850bd904edSIan Lepore 		if (sc->sc_resid == 0) {
3860bd904edSIan Lepore 			sc->sc_data  = sc->sc_curmsg->buf;
3870bd904edSIan Lepore 			sc->sc_dlen  = sc->sc_curmsg->len;
3880bd904edSIan Lepore 			sc->sc_resid = sc->sc_dlen;
3890bd904edSIan Lepore 			++sc->sc_curmsg;
3900bd904edSIan Lepore 		}
3910bd904edSIan Lepore 		do {
3920bd904edSIan Lepore 			*sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA);
3930bd904edSIan Lepore 			DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
3940bd904edSIan Lepore 			++sc->sc_data;
3950bd904edSIan Lepore 			--sc->sc_resid;
3960bd904edSIan Lepore 			--sc->sc_totlen;
3970bd904edSIan Lepore 			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
3980bd904edSIan Lepore 		} while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD));
3990bd904edSIan Lepore 	} while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD));
4000bd904edSIan Lepore }
4010bd904edSIan Lepore 
4020bd904edSIan Lepore static void
4030bd904edSIan Lepore bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc)
4040bd904edSIan Lepore {
4050bd904edSIan Lepore 	uint32_t status;
4060bd904edSIan Lepore 
4070bd904edSIan Lepore 	/* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */
4080bd904edSIan Lepore 	do {
4090bd904edSIan Lepore 		if (sc->sc_resid == 0) {
4100bd904edSIan Lepore 			sc->sc_data  = sc->sc_curmsg->buf;
4110bd904edSIan Lepore 			sc->sc_dlen  = sc->sc_curmsg->len;
4120bd904edSIan Lepore 			sc->sc_resid = sc->sc_dlen;
4130bd904edSIan Lepore 			++sc->sc_curmsg;
4140bd904edSIan Lepore 		}
4150bd904edSIan Lepore 		do {
4160bd904edSIan Lepore 			BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
4170bd904edSIan Lepore 			DEBUGF(sc, 1, "0x%02x ", *sc->sc_data);
4180bd904edSIan Lepore 			++sc->sc_data;
4190bd904edSIan Lepore 			--sc->sc_resid;
4200bd904edSIan Lepore 			--sc->sc_totlen;
4210bd904edSIan Lepore 			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
4220bd904edSIan Lepore 		} while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD));
4230bd904edSIan Lepore 		/*
4240bd904edSIan Lepore 		 * If a repeat-start was pending and we just hit the end of a tx
4250bd904edSIan Lepore 		 * buffer, see if it's also the end of the writes that preceeded
4260bd904edSIan Lepore 		 * the repeat-start.  If so, log the repeat-start and the start
4270bd904edSIan Lepore 		 * of the following read, and return because we're not writing
4280bd904edSIan Lepore 		 * anymore (and TXD will be true because there's room to write
4290bd904edSIan Lepore 		 * in the fifo).
4300bd904edSIan Lepore 		 */
4310bd904edSIan Lepore 		if (sc->sc_replen > 0 && sc->sc_resid == 0) {
4320bd904edSIan Lepore 			sc->sc_replen -= sc->sc_dlen;
4330bd904edSIan Lepore 			if (sc->sc_replen == 0) {
4340bd904edSIan Lepore 				DEBUGF(sc, 1, " err=0\n");
4350bd904edSIan Lepore 				DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n",
4360bd904edSIan Lepore 				    sc->sc_curmsg->slave | 0x01);
4370bd904edSIan Lepore 				DEVICE_DEBUGF(sc, 1,
4380bd904edSIan Lepore 				    "read   0x%02x len %d: ",
4390bd904edSIan Lepore 				    sc->sc_curmsg->slave | 0x01,
4400bd904edSIan Lepore 				    sc->sc_totlen);
4410bd904edSIan Lepore 				sc->sc_flags |= BCM_I2C_READ;
4420bd904edSIan Lepore 				return;
4430bd904edSIan Lepore 			}
4440bd904edSIan Lepore 		}
4450bd904edSIan Lepore 	} while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD));
4460bd904edSIan Lepore }
4470bd904edSIan Lepore 
4480bd904edSIan Lepore static void
449be9ddf43SLuiz Otavio O Souza bcm_bsc_intr(void *arg)
450be9ddf43SLuiz Otavio O Souza {
451be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
452be9ddf43SLuiz Otavio O Souza 	uint32_t status;
453be9ddf43SLuiz Otavio O Souza 
454be9ddf43SLuiz Otavio O Souza 	sc = (struct bcm_bsc_softc *)arg;
455be9ddf43SLuiz Otavio O Souza 
456be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
457be9ddf43SLuiz Otavio O Souza 
458be9ddf43SLuiz Otavio O Souza 	/* The I2C interrupt is shared among all the BSC controllers. */
459be9ddf43SLuiz Otavio O Souza 	if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
460be9ddf43SLuiz Otavio O Souza 		BCM_BSC_UNLOCK(sc);
461be9ddf43SLuiz Otavio O Souza 		return;
462be9ddf43SLuiz Otavio O Souza 	}
463be9ddf43SLuiz Otavio O Souza 
464be9ddf43SLuiz Otavio O Souza 	status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
4650bd904edSIan Lepore 	DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status);
466be9ddf43SLuiz Otavio O Souza 
4670bd904edSIan Lepore 	/* RXD and DONE can assert together, empty fifo before checking done. */
4680bd904edSIan Lepore 	if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD))
4690bd904edSIan Lepore 		bcm_bsc_empty_rx_fifo(sc);
4700bd904edSIan Lepore 
4710bd904edSIan Lepore 	/* Check for completion. */
4720bd904edSIan Lepore 	if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) {
4730bd904edSIan Lepore 		sc->sc_flags |= BCM_I2C_DONE;
4740bd904edSIan Lepore 		if (status & BCM_BSC_STATUS_ERRBITS)
475e50c6241SLuiz Otavio O Souza 			sc->sc_flags |= BCM_I2C_ERROR;
476be9ddf43SLuiz Otavio O Souza 		/* Disable interrupts. */
477be9ddf43SLuiz Otavio O Souza 		bcm_bsc_reset(sc);
4780bd904edSIan Lepore 		wakeup(sc);
4790bd904edSIan Lepore 	} else if (!(sc->sc_flags & BCM_I2C_READ)) {
4800bd904edSIan Lepore 		/*
4810bd904edSIan Lepore 		 * Don't check for TXD until after determining whether the
4820bd904edSIan Lepore 		 * transfer is complete; TXD will be asserted along with ERR or
4830bd904edSIan Lepore 		 * DONE if there is room in the fifo.
4840bd904edSIan Lepore 		 */
485b5496277SIan Lepore 		if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0)
4860bd904edSIan Lepore 			bcm_bsc_fill_tx_fifo(sc);
487be9ddf43SLuiz Otavio O Souza 	}
488be9ddf43SLuiz Otavio O Souza 
489be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
490be9ddf43SLuiz Otavio O Souza }
491be9ddf43SLuiz Otavio O Souza 
492be9ddf43SLuiz Otavio O Souza static int
493be9ddf43SLuiz Otavio O Souza bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
494be9ddf43SLuiz Otavio O Souza {
495be9ddf43SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
4960bd904edSIan Lepore 	struct iic_msg *endmsgs, *nxtmsg;
4970bd904edSIan Lepore 	uint32_t readctl, status;
4980bd904edSIan Lepore 	int err;
4990bd904edSIan Lepore 	uint16_t curlen;
5000bd904edSIan Lepore 	uint8_t curisread, curslave, nxtisread, nxtslave;
501be9ddf43SLuiz Otavio O Souza 
502be9ddf43SLuiz Otavio O Souza 	sc = device_get_softc(dev);
503be9ddf43SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
504be9ddf43SLuiz Otavio O Souza 
505be9ddf43SLuiz Otavio O Souza 	/* If the controller is busy wait until it is available. */
506be9ddf43SLuiz Otavio O Souza 	while (sc->sc_flags & BCM_I2C_BUSY)
507a141b672SLuiz Otavio O Souza 		mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0);
508be9ddf43SLuiz Otavio O Souza 
509be9ddf43SLuiz Otavio O Souza 	/* Now we have control over the BSC controller. */
510be9ddf43SLuiz Otavio O Souza 	sc->sc_flags = BCM_I2C_BUSY;
511be9ddf43SLuiz Otavio O Souza 
5120bd904edSIan Lepore 	DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs);
5130bd904edSIan Lepore 
514be9ddf43SLuiz Otavio O Souza 	/* Clear the FIFO and the pending interrupts. */
515be9ddf43SLuiz Otavio O Souza 	bcm_bsc_reset(sc);
516be9ddf43SLuiz Otavio O Souza 
5170bd904edSIan Lepore 	/*
5180bd904edSIan Lepore 	 * Perform all the transfers requested in the array of msgs.  Note that
5190bd904edSIan Lepore 	 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance
5200bd904edSIan Lepore 	 * sc->sc_curmsg through the array of messages, as the data from each
5210bd904edSIan Lepore 	 * message is fully consumed, but it is this loop that notices when we
5220bd904edSIan Lepore 	 * have no more messages to process.
5230bd904edSIan Lepore 	 */
524be9ddf43SLuiz Otavio O Souza 	err = 0;
5250bd904edSIan Lepore 	sc->sc_resid = 0;
5260bd904edSIan Lepore 	sc->sc_curmsg = msgs;
5270bd904edSIan Lepore 	endmsgs = &msgs[nmsgs];
5280bd904edSIan Lepore 	while (sc->sc_curmsg < endmsgs) {
5290bd904edSIan Lepore 		readctl = 0;
5300bd904edSIan Lepore 		curslave = sc->sc_curmsg->slave >> 1;
5310bd904edSIan Lepore 		curisread = sc->sc_curmsg->flags & IIC_M_RD;
5320bd904edSIan Lepore 		sc->sc_replen = 0;
5330bd904edSIan Lepore 		sc->sc_totlen = sc->sc_curmsg->len;
5340bd904edSIan Lepore 		/*
5350bd904edSIan Lepore 		 * Scan for scatter/gather IO (same slave and direction) or
5360bd904edSIan Lepore 		 * repeat-start (read following write for the same slave).
5370bd904edSIan Lepore 		 */
5380bd904edSIan Lepore 		for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) {
5390bd904edSIan Lepore 			nxtslave = nxtmsg->slave >> 1;
5400bd904edSIan Lepore 			if (curslave == nxtslave) {
5410bd904edSIan Lepore 				nxtisread = nxtmsg->flags & IIC_M_RD;
5420bd904edSIan Lepore 				if (curisread == nxtisread) {
5430bd904edSIan Lepore 					/*
5440bd904edSIan Lepore 					 * Same slave and direction, this
5450bd904edSIan Lepore 					 * message will be part of the same
5460bd904edSIan Lepore 					 * transfer as the previous one.
5470bd904edSIan Lepore 					 */
5480bd904edSIan Lepore 					sc->sc_totlen += nxtmsg->len;
5490bd904edSIan Lepore 					continue;
5500bd904edSIan Lepore 				} else if (curisread == IIC_M_WR) {
5510bd904edSIan Lepore 					/*
5520bd904edSIan Lepore 					 * Read after write to same slave means
5530bd904edSIan Lepore 					 * repeat-start, remember how many bytes
5540bd904edSIan Lepore 					 * come before the repeat-start, switch
5550bd904edSIan Lepore 					 * the direction to IIC_M_RD, and gather
5560bd904edSIan Lepore 					 * up following reads to the same slave.
5570bd904edSIan Lepore 					 */
5580bd904edSIan Lepore 					curisread = IIC_M_RD;
5590bd904edSIan Lepore 					sc->sc_replen = sc->sc_totlen;
5600bd904edSIan Lepore 					sc->sc_totlen += nxtmsg->len;
5610bd904edSIan Lepore 					continue;
5620bd904edSIan Lepore 				}
5630bd904edSIan Lepore 			}
5640bd904edSIan Lepore 			break;
5650bd904edSIan Lepore 		}
5660bd904edSIan Lepore 
5670bd904edSIan Lepore 		/*
5680bd904edSIan Lepore 		 * curslave and curisread temporaries from above may refer to
5690bd904edSIan Lepore 		 * the after-repstart msg, reset them to reflect sc_curmsg.
5700bd904edSIan Lepore 		 */
5710bd904edSIan Lepore 		curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0;
5720bd904edSIan Lepore 		curslave = sc->sc_curmsg->slave | curisread;
573be9ddf43SLuiz Otavio O Souza 
574be9ddf43SLuiz Otavio O Souza 		/* Write the slave address. */
5750bd904edSIan Lepore 		BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1);
576be9ddf43SLuiz Otavio O Souza 
5770bd904edSIan Lepore 		DEVICE_DEBUGF(sc, 2, "start  0x%02x\n", curslave);
578be9ddf43SLuiz Otavio O Souza 
5790bd904edSIan Lepore 		/*
5800bd904edSIan Lepore 		 * Either set up read length and direction variables for a
5810bd904edSIan Lepore 		 * simple transfer or get the hardware started on the first
5820bd904edSIan Lepore 		 * piece of a transfer that involves a repeat-start and set up
5830bd904edSIan Lepore 		 * the read length and direction vars for the second piece.
5840bd904edSIan Lepore 		 */
5850bd904edSIan Lepore 		if (sc->sc_replen == 0) {
5860bd904edSIan Lepore 			DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
587ae992394SIan Lepore 			    (curisread) ? "read" : "write", curslave,
5880bd904edSIan Lepore 			    sc->sc_totlen);
5890bd904edSIan Lepore 			curlen = sc->sc_totlen;
5900bd904edSIan Lepore 			if (curisread) {
5910bd904edSIan Lepore 				readctl = BCM_BSC_CTRL_READ;
592be9ddf43SLuiz Otavio O Souza 				sc->sc_flags |= BCM_I2C_READ;
5930bd904edSIan Lepore 			} else {
5940bd904edSIan Lepore 				readctl = 0;
5950bd904edSIan Lepore 				sc->sc_flags &= ~BCM_I2C_READ;
596be9ddf43SLuiz Otavio O Souza 			}
5970bd904edSIan Lepore 		} else {
5980bd904edSIan Lepore 			DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ",
599ae992394SIan Lepore 			    (curisread) ? "read" : "write", curslave,
6000bd904edSIan Lepore 			    sc->sc_replen);
601be9ddf43SLuiz Otavio O Souza 
6020bd904edSIan Lepore 			/*
6030bd904edSIan Lepore 			 * Start the write transfer with an empty fifo and wait
6040bd904edSIan Lepore 			 * for the 'transfer active' status bit to light up;
6050bd904edSIan Lepore 			 * that indicates that the hardware has latched the
6060bd904edSIan Lepore 			 * direction and length for the write, and we can safely
6070bd904edSIan Lepore 			 * reload those registers and issue the start for the
6080bd904edSIan Lepore 			 * following read; interrupts are not enabled here.
6090bd904edSIan Lepore 			 */
6100bd904edSIan Lepore 			BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen);
611be9ddf43SLuiz Otavio O Souza 			BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
6120bd904edSIan Lepore 			    BCM_BSC_CTRL_ST);
6130bd904edSIan Lepore 			do {
6140bd904edSIan Lepore 				status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
6150bd904edSIan Lepore 				if (status & BCM_BSC_STATUS_ERR) {
6160bd904edSIan Lepore 					/* no ACK on slave addr */
6170bd904edSIan Lepore 					err = EIO;
6180bd904edSIan Lepore 					goto xfer_done;
6190bd904edSIan Lepore 				}
6200bd904edSIan Lepore 			} while ((status & BCM_BSC_STATUS_TA) == 0);
6210bd904edSIan Lepore 			/*
6220bd904edSIan Lepore 			 * Set curlen and readctl for the repeat-start read that
6230bd904edSIan Lepore 			 * we need to set up below, but set sc_flags to write,
6240bd904edSIan Lepore 			 * because that is the operation in progress right now.
6250bd904edSIan Lepore 			 */
6260bd904edSIan Lepore 			curlen = sc->sc_totlen - sc->sc_replen;
6270bd904edSIan Lepore 			readctl = BCM_BSC_CTRL_READ;
6280bd904edSIan Lepore 			sc->sc_flags &= ~BCM_I2C_READ;
6290bd904edSIan Lepore 		}
6300bd904edSIan Lepore 
6310bd904edSIan Lepore 		/*
6320bd904edSIan Lepore 		 * Start the transfer with interrupts enabled, then if doing a
6330bd904edSIan Lepore 		 * write, fill the tx fifo.  Not prefilling the fifo until after
6340bd904edSIan Lepore 		 * this start command is the key workaround for making
6350bd904edSIan Lepore 		 * repeat-start work, and it's harmless to do it in this order
6360bd904edSIan Lepore 		 * for a regular write too.
6370bd904edSIan Lepore 		 */
6380bd904edSIan Lepore 		BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen);
6390bd904edSIan Lepore 		BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN |
6400bd904edSIan Lepore 		    BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL);
6410bd904edSIan Lepore 
6420bd904edSIan Lepore 		if (!(sc->sc_curmsg->flags & IIC_M_RD)) {
6430bd904edSIan Lepore 			bcm_bsc_fill_tx_fifo(sc);
6440bd904edSIan Lepore 		}
645be9ddf43SLuiz Otavio O Souza 
646be9ddf43SLuiz Otavio O Souza 		/* Wait for the transaction to complete. */
6470bd904edSIan Lepore 		while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) {
6480bd904edSIan Lepore 			err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz);
6490bd904edSIan Lepore 		}
65071b37cb9SLuiz Otavio O Souza 		/* Check for errors. */
6510a39cc71SLuiz Otavio O Souza 		if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR))
652be9ddf43SLuiz Otavio O Souza 			err = EIO;
6530bd904edSIan Lepore xfer_done:
6540bd904edSIan Lepore 		DEBUGF(sc, 1, " err=%d\n", err);
6550bd904edSIan Lepore 		DEVICE_DEBUGF(sc, 2, "stop\n");
65671b37cb9SLuiz Otavio O Souza 		if (err != 0)
657be9ddf43SLuiz Otavio O Souza 			break;
658be9ddf43SLuiz Otavio O Souza 	}
659be9ddf43SLuiz Otavio O Souza 
6600bd904edSIan Lepore 	/* Disable interrupts, clean fifo, etc. */
6610bd904edSIan Lepore 	bcm_bsc_reset(sc);
6620bd904edSIan Lepore 
663be9ddf43SLuiz Otavio O Souza 	/* Clean the controller flags. */
664be9ddf43SLuiz Otavio O Souza 	sc->sc_flags = 0;
665be9ddf43SLuiz Otavio O Souza 
666a141b672SLuiz Otavio O Souza 	/* Wake up the threads waiting for bus. */
667a141b672SLuiz Otavio O Souza 	wakeup(dev);
668a141b672SLuiz Otavio O Souza 
669be9ddf43SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
670be9ddf43SLuiz Otavio O Souza 
671be9ddf43SLuiz Otavio O Souza 	return (err);
672be9ddf43SLuiz Otavio O Souza }
673be9ddf43SLuiz Otavio O Souza 
674e50c6241SLuiz Otavio O Souza static int
675e50c6241SLuiz Otavio O Souza bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
676e50c6241SLuiz Otavio O Souza {
677e50c6241SLuiz Otavio O Souza 	struct bcm_bsc_softc *sc;
6789e93dfcfSLuiz Otavio O Souza 	uint32_t busfreq;
679e50c6241SLuiz Otavio O Souza 
680e50c6241SLuiz Otavio O Souza 	sc = device_get_softc(dev);
681e50c6241SLuiz Otavio O Souza 	BCM_BSC_LOCK(sc);
682e50c6241SLuiz Otavio O Souza 	bcm_bsc_reset(sc);
6839e93dfcfSLuiz Otavio O Souza 	if (sc->sc_iicbus == NULL)
6849e93dfcfSLuiz Otavio O Souza 		busfreq = 100000;
6859e93dfcfSLuiz Otavio O Souza 	else
6869e93dfcfSLuiz Otavio O Souza 		busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
6879e93dfcfSLuiz Otavio O Souza 	BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
688e50c6241SLuiz Otavio O Souza 	BCM_BSC_UNLOCK(sc);
689e50c6241SLuiz Otavio O Souza 
690e50c6241SLuiz Otavio O Souza 	return (IIC_ENOADDR);
691e50c6241SLuiz Otavio O Souza }
692e50c6241SLuiz Otavio O Souza 
693be9ddf43SLuiz Otavio O Souza static phandle_t
694be9ddf43SLuiz Otavio O Souza bcm_bsc_get_node(device_t bus, device_t dev)
695be9ddf43SLuiz Otavio O Souza {
696be9ddf43SLuiz Otavio O Souza 
697be9ddf43SLuiz Otavio O Souza 	/* We only have one child, the I2C bus, which needs our own node. */
698be9ddf43SLuiz Otavio O Souza 	return (ofw_bus_get_node(bus));
699be9ddf43SLuiz Otavio O Souza }
700be9ddf43SLuiz Otavio O Souza 
701be9ddf43SLuiz Otavio O Souza static device_method_t bcm_bsc_methods[] = {
702be9ddf43SLuiz Otavio O Souza 	/* Device interface */
703be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(device_probe,		bcm_bsc_probe),
704be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(device_attach,	bcm_bsc_attach),
705be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(device_detach,	bcm_bsc_detach),
706be9ddf43SLuiz Otavio O Souza 
707be9ddf43SLuiz Otavio O Souza 	/* iicbus interface */
708e50c6241SLuiz Otavio O Souza 	DEVMETHOD(iicbus_reset,		bcm_bsc_iicbus_reset),
709be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
710be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(iicbus_transfer,	bcm_bsc_transfer),
711be9ddf43SLuiz Otavio O Souza 
712be9ddf43SLuiz Otavio O Souza 	/* ofw_bus interface */
713be9ddf43SLuiz Otavio O Souza 	DEVMETHOD(ofw_bus_get_node,	bcm_bsc_get_node),
714be9ddf43SLuiz Otavio O Souza 
715be9ddf43SLuiz Otavio O Souza 	DEVMETHOD_END
716be9ddf43SLuiz Otavio O Souza };
717be9ddf43SLuiz Otavio O Souza 
718be9ddf43SLuiz Otavio O Souza static devclass_t bcm_bsc_devclass;
719be9ddf43SLuiz Otavio O Souza 
720be9ddf43SLuiz Otavio O Souza static driver_t bcm_bsc_driver = {
721be9ddf43SLuiz Otavio O Souza 	"iichb",
722be9ddf43SLuiz Otavio O Souza 	bcm_bsc_methods,
723be9ddf43SLuiz Otavio O Souza 	sizeof(struct bcm_bsc_softc),
724be9ddf43SLuiz Otavio O Souza };
725be9ddf43SLuiz Otavio O Souza 
726*676ea8e1SJohn Baldwin DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, 0, 0);
727be9ddf43SLuiz Otavio O Souza DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);
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