1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 6 * Copyright (c) 2012 Luiz Otavio O Souza. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/gpio.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <arm/allwinner/aw_machdep.h> 55 #include <arm/allwinner/allwinner_pinctrl.h> 56 #include <dev/extres/clk/clk.h> 57 #include <dev/extres/hwreset/hwreset.h> 58 59 #if defined(__aarch64__) 60 #include "opt_soc.h" 61 #endif 62 63 #include "gpio_if.h" 64 65 #define AW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 66 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) 67 68 #define AW_GPIO_NONE 0 69 #define AW_GPIO_PULLUP 1 70 #define AW_GPIO_PULLDOWN 2 71 72 #define AW_GPIO_INPUT 0 73 #define AW_GPIO_OUTPUT 1 74 75 #define AW_GPIO_DRV_MASK 0x3 76 #define AW_GPIO_PUD_MASK 0x3 77 78 #define AW_PINCTRL 1 79 #define AW_R_PINCTRL 2 80 81 /* Defined in aw_padconf.c */ 82 #ifdef SOC_ALLWINNER_A10 83 extern const struct allwinner_padconf a10_padconf; 84 #endif 85 86 /* Defined in a13_padconf.c */ 87 #ifdef SOC_ALLWINNER_A13 88 extern const struct allwinner_padconf a13_padconf; 89 #endif 90 91 /* Defined in a20_padconf.c */ 92 #ifdef SOC_ALLWINNER_A20 93 extern const struct allwinner_padconf a20_padconf; 94 #endif 95 96 /* Defined in a31_padconf.c */ 97 #ifdef SOC_ALLWINNER_A31 98 extern const struct allwinner_padconf a31_padconf; 99 #endif 100 101 /* Defined in a31s_padconf.c */ 102 #ifdef SOC_ALLWINNER_A31S 103 extern const struct allwinner_padconf a31s_padconf; 104 #endif 105 106 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 107 extern const struct allwinner_padconf a31_r_padconf; 108 #endif 109 110 /* Defined in a33_padconf.c */ 111 #ifdef SOC_ALLWINNER_A33 112 extern const struct allwinner_padconf a33_padconf; 113 #endif 114 115 /* Defined in h3_padconf.c */ 116 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 117 extern const struct allwinner_padconf h3_padconf; 118 extern const struct allwinner_padconf h3_r_padconf; 119 #endif 120 121 /* Defined in a83t_padconf.c */ 122 #ifdef SOC_ALLWINNER_A83T 123 extern const struct allwinner_padconf a83t_padconf; 124 extern const struct allwinner_padconf a83t_r_padconf; 125 #endif 126 127 /* Defined in a64_padconf.c */ 128 #ifdef SOC_ALLWINNER_A64 129 extern const struct allwinner_padconf a64_padconf; 130 extern const struct allwinner_padconf a64_r_padconf; 131 #endif 132 133 /* Defined in h6_padconf.c */ 134 #ifdef SOC_ALLWINNER_H6 135 extern const struct allwinner_padconf h6_padconf; 136 extern const struct allwinner_padconf h6_r_padconf; 137 #endif 138 139 static struct ofw_compat_data compat_data[] = { 140 #ifdef SOC_ALLWINNER_A10 141 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf}, 142 #endif 143 #ifdef SOC_ALLWINNER_A13 144 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_padconf}, 145 #endif 146 #ifdef SOC_ALLWINNER_A20 147 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf}, 148 #endif 149 #ifdef SOC_ALLWINNER_A31 150 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf}, 151 #endif 152 #ifdef SOC_ALLWINNER_A31S 153 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf}, 154 #endif 155 #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) 156 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf}, 157 #endif 158 #ifdef SOC_ALLWINNER_A33 159 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_padconf}, 160 #endif 161 #ifdef SOC_ALLWINNER_A83T 162 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf}, 163 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf}, 164 #endif 165 #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) 166 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf}, 167 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_padconf}, 168 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf}, 169 #endif 170 #ifdef SOC_ALLWINNER_A64 171 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf}, 172 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf}, 173 #endif 174 #ifdef SOC_ALLWINNER_H6 175 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_padconf}, 176 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_padconf}, 177 #endif 178 {NULL, 0} 179 }; 180 181 struct clk_list { 182 TAILQ_ENTRY(clk_list) next; 183 clk_t clk; 184 }; 185 186 struct aw_gpio_softc { 187 device_t sc_dev; 188 device_t sc_busdev; 189 struct mtx sc_mtx; 190 struct resource * sc_mem_res; 191 struct resource * sc_irq_res; 192 bus_space_tag_t sc_bst; 193 bus_space_handle_t sc_bsh; 194 void * sc_intrhand; 195 const struct allwinner_padconf * padconf; 196 TAILQ_HEAD(, clk_list) clk_list; 197 }; 198 199 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 200 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 201 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 202 203 #define AW_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) 204 #define AW_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) 205 #define AW_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) 206 #define AW_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) 207 208 #define AW_GPIO_GP_INT_CFG0 0x200 209 #define AW_GPIO_GP_INT_CFG1 0x204 210 #define AW_GPIO_GP_INT_CFG2 0x208 211 #define AW_GPIO_GP_INT_CFG3 0x20c 212 213 #define AW_GPIO_GP_INT_CTL 0x210 214 #define AW_GPIO_GP_INT_STA 0x214 215 #define AW_GPIO_GP_INT_DEB 0x218 216 217 static char *aw_gpio_parse_function(phandle_t node); 218 static const char **aw_gpio_parse_pins(phandle_t node, int *pins_nb); 219 static uint32_t aw_gpio_parse_bias(phandle_t node); 220 static int aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive); 221 222 static int aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value); 223 static int aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); 224 static int aw_gpio_pin_get_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int *value); 225 static int aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, unsigned int value); 226 227 #define AW_GPIO_WRITE(_sc, _off, _val) \ 228 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 229 #define AW_GPIO_READ(_sc, _off) \ 230 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 231 232 static uint32_t 233 aw_gpio_get_function(struct aw_gpio_softc *sc, uint32_t pin) 234 { 235 uint32_t bank, func, offset; 236 237 /* Must be called with lock held. */ 238 AW_GPIO_LOCK_ASSERT(sc); 239 240 if (pin > sc->padconf->npins) 241 return (0); 242 bank = sc->padconf->pins[pin].port; 243 pin = sc->padconf->pins[pin].pin; 244 offset = ((pin & 0x07) << 2); 245 246 func = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 247 248 return ((func >> offset) & 0x7); 249 } 250 251 static int 252 aw_gpio_set_function(struct aw_gpio_softc *sc, uint32_t pin, uint32_t f) 253 { 254 uint32_t bank, data, offset; 255 256 /* Check if the function exists in the padconf data */ 257 if (sc->padconf->pins[pin].functions[f] == NULL) 258 return (EINVAL); 259 260 /* Must be called with lock held. */ 261 AW_GPIO_LOCK_ASSERT(sc); 262 263 bank = sc->padconf->pins[pin].port; 264 pin = sc->padconf->pins[pin].pin; 265 offset = ((pin & 0x07) << 2); 266 267 data = AW_GPIO_READ(sc, AW_GPIO_GP_CFG(bank, pin >> 3)); 268 data &= ~(7 << offset); 269 data |= (f << offset); 270 AW_GPIO_WRITE(sc, AW_GPIO_GP_CFG(bank, pin >> 3), data); 271 272 return (0); 273 } 274 275 static uint32_t 276 aw_gpio_get_pud(struct aw_gpio_softc *sc, uint32_t pin) 277 { 278 uint32_t bank, offset, val; 279 280 /* Must be called with lock held. */ 281 AW_GPIO_LOCK_ASSERT(sc); 282 283 bank = sc->padconf->pins[pin].port; 284 pin = sc->padconf->pins[pin].pin; 285 offset = ((pin & 0x0f) << 1); 286 287 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 288 289 return ((val >> offset) & AW_GPIO_PUD_MASK); 290 } 291 292 static void 293 aw_gpio_set_pud(struct aw_gpio_softc *sc, uint32_t pin, uint32_t state) 294 { 295 uint32_t bank, offset, val; 296 297 if (aw_gpio_get_pud(sc, pin) == state) 298 return; 299 300 /* Must be called with lock held. */ 301 AW_GPIO_LOCK_ASSERT(sc); 302 303 bank = sc->padconf->pins[pin].port; 304 pin = sc->padconf->pins[pin].pin; 305 offset = ((pin & 0x0f) << 1); 306 307 val = AW_GPIO_READ(sc, AW_GPIO_GP_PUL(bank, pin >> 4)); 308 val &= ~(AW_GPIO_PUD_MASK << offset); 309 val |= (state << offset); 310 AW_GPIO_WRITE(sc, AW_GPIO_GP_PUL(bank, pin >> 4), val); 311 } 312 313 static uint32_t 314 aw_gpio_get_drv(struct aw_gpio_softc *sc, uint32_t pin) 315 { 316 uint32_t bank, offset, val; 317 318 /* Must be called with lock held. */ 319 AW_GPIO_LOCK_ASSERT(sc); 320 321 bank = sc->padconf->pins[pin].port; 322 pin = sc->padconf->pins[pin].pin; 323 offset = ((pin & 0x0f) << 1); 324 325 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 326 327 return ((val >> offset) & AW_GPIO_DRV_MASK); 328 } 329 330 static void 331 aw_gpio_set_drv(struct aw_gpio_softc *sc, uint32_t pin, uint32_t drive) 332 { 333 uint32_t bank, offset, val; 334 335 if (aw_gpio_get_drv(sc, pin) == drive) 336 return; 337 338 /* Must be called with lock held. */ 339 AW_GPIO_LOCK_ASSERT(sc); 340 341 bank = sc->padconf->pins[pin].port; 342 pin = sc->padconf->pins[pin].pin; 343 offset = ((pin & 0x0f) << 1); 344 345 val = AW_GPIO_READ(sc, AW_GPIO_GP_DRV(bank, pin >> 4)); 346 val &= ~(AW_GPIO_DRV_MASK << offset); 347 val |= (drive << offset); 348 AW_GPIO_WRITE(sc, AW_GPIO_GP_DRV(bank, pin >> 4), val); 349 } 350 351 static int 352 aw_gpio_pin_configure(struct aw_gpio_softc *sc, uint32_t pin, uint32_t flags) 353 { 354 u_int val; 355 int err = 0; 356 357 /* Must be called with lock held. */ 358 AW_GPIO_LOCK_ASSERT(sc); 359 360 if (pin > sc->padconf->npins) 361 return (EINVAL); 362 363 /* Manage input/output. */ 364 if (flags & GPIO_PIN_INPUT) { 365 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 366 } else if ((flags & GPIO_PIN_OUTPUT) && 367 aw_gpio_get_function(sc, pin) != AW_GPIO_OUTPUT) { 368 if (flags & GPIO_PIN_PRESET_LOW) { 369 aw_gpio_pin_set_locked(sc, pin, 0); 370 } else if (flags & GPIO_PIN_PRESET_HIGH) { 371 aw_gpio_pin_set_locked(sc, pin, 1); 372 } else { 373 /* Read the pin and preset output to current state. */ 374 err = aw_gpio_set_function(sc, pin, AW_GPIO_INPUT); 375 if (err == 0) { 376 aw_gpio_pin_get_locked(sc, pin, &val); 377 aw_gpio_pin_set_locked(sc, pin, val); 378 } 379 } 380 if (err == 0) 381 err = aw_gpio_set_function(sc, pin, AW_GPIO_OUTPUT); 382 } 383 384 if (err) 385 return (err); 386 387 /* Manage Pull-up/pull-down. */ 388 if (flags & GPIO_PIN_PULLUP) 389 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLUP); 390 else if (flags & GPIO_PIN_PULLDOWN) 391 aw_gpio_set_pud(sc, pin, AW_GPIO_PULLDOWN); 392 else 393 aw_gpio_set_pud(sc, pin, AW_GPIO_NONE); 394 395 return (0); 396 } 397 398 static device_t 399 aw_gpio_get_bus(device_t dev) 400 { 401 struct aw_gpio_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 return (sc->sc_busdev); 406 } 407 408 static int 409 aw_gpio_pin_max(device_t dev, int *maxpin) 410 { 411 struct aw_gpio_softc *sc; 412 413 sc = device_get_softc(dev); 414 415 *maxpin = sc->padconf->npins - 1; 416 return (0); 417 } 418 419 static int 420 aw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 421 { 422 struct aw_gpio_softc *sc; 423 424 sc = device_get_softc(dev); 425 if (pin >= sc->padconf->npins) 426 return (EINVAL); 427 428 *caps = AW_GPIO_DEFAULT_CAPS; 429 430 return (0); 431 } 432 433 static int 434 aw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 435 { 436 struct aw_gpio_softc *sc; 437 uint32_t func; 438 uint32_t pud; 439 440 sc = device_get_softc(dev); 441 if (pin >= sc->padconf->npins) 442 return (EINVAL); 443 444 AW_GPIO_LOCK(sc); 445 func = aw_gpio_get_function(sc, pin); 446 switch (func) { 447 case AW_GPIO_INPUT: 448 *flags = GPIO_PIN_INPUT; 449 break; 450 case AW_GPIO_OUTPUT: 451 *flags = GPIO_PIN_OUTPUT; 452 break; 453 default: 454 *flags = 0; 455 break; 456 } 457 458 pud = aw_gpio_get_pud(sc, pin); 459 switch (pud) { 460 case AW_GPIO_PULLDOWN: 461 *flags |= GPIO_PIN_PULLDOWN; 462 break; 463 case AW_GPIO_PULLUP: 464 *flags |= GPIO_PIN_PULLUP; 465 break; 466 default: 467 break; 468 } 469 470 AW_GPIO_UNLOCK(sc); 471 472 return (0); 473 } 474 475 static int 476 aw_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 477 { 478 struct aw_gpio_softc *sc; 479 480 sc = device_get_softc(dev); 481 if (pin >= sc->padconf->npins) 482 return (EINVAL); 483 484 snprintf(name, GPIOMAXNAME - 1, "%s", 485 sc->padconf->pins[pin].name); 486 name[GPIOMAXNAME - 1] = '\0'; 487 488 return (0); 489 } 490 491 static int 492 aw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 493 { 494 struct aw_gpio_softc *sc; 495 int err; 496 497 sc = device_get_softc(dev); 498 if (pin > sc->padconf->npins) 499 return (EINVAL); 500 501 AW_GPIO_LOCK(sc); 502 err = aw_gpio_pin_configure(sc, pin, flags); 503 AW_GPIO_UNLOCK(sc); 504 505 return (err); 506 } 507 508 static int 509 aw_gpio_pin_set_locked(struct aw_gpio_softc *sc, uint32_t pin, 510 unsigned int value) 511 { 512 uint32_t bank, data; 513 514 AW_GPIO_LOCK_ASSERT(sc); 515 516 if (pin > sc->padconf->npins) 517 return (EINVAL); 518 519 bank = sc->padconf->pins[pin].port; 520 pin = sc->padconf->pins[pin].pin; 521 522 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 523 if (value) 524 data |= (1 << pin); 525 else 526 data &= ~(1 << pin); 527 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 528 529 return (0); 530 } 531 532 static int 533 aw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 534 { 535 struct aw_gpio_softc *sc; 536 int ret; 537 538 sc = device_get_softc(dev); 539 540 AW_GPIO_LOCK(sc); 541 ret = aw_gpio_pin_set_locked(sc, pin, value); 542 AW_GPIO_UNLOCK(sc); 543 544 return (ret); 545 } 546 547 static int 548 aw_gpio_pin_get_locked(struct aw_gpio_softc *sc,uint32_t pin, 549 unsigned int *val) 550 { 551 uint32_t bank, reg_data; 552 553 AW_GPIO_LOCK_ASSERT(sc); 554 555 if (pin > sc->padconf->npins) 556 return (EINVAL); 557 558 bank = sc->padconf->pins[pin].port; 559 pin = sc->padconf->pins[pin].pin; 560 561 reg_data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 562 *val = (reg_data & (1 << pin)) ? 1 : 0; 563 564 return (0); 565 } 566 567 static char * 568 aw_gpio_parse_function(phandle_t node) 569 { 570 char *function; 571 572 if (OF_getprop_alloc(node, "function", 573 (void **)&function) != -1) 574 return (function); 575 if (OF_getprop_alloc(node, "allwinner,function", 576 (void **)&function) != -1) 577 return (function); 578 579 return (NULL); 580 } 581 582 static const char ** 583 aw_gpio_parse_pins(phandle_t node, int *pins_nb) 584 { 585 const char **pinlist; 586 587 *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist); 588 if (*pins_nb > 0) 589 return (pinlist); 590 591 *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", 592 &pinlist); 593 if (*pins_nb > 0) 594 return (pinlist); 595 596 return (NULL); 597 } 598 599 static uint32_t 600 aw_gpio_parse_bias(phandle_t node) 601 { 602 uint32_t bias; 603 604 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1) 605 return (bias); 606 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1) 607 return (bias); 608 if (OF_hasprop(node, "bias-disable")) 609 return (AW_GPIO_NONE); 610 if (OF_hasprop(node, "bias-pull-up")) 611 return (AW_GPIO_PULLUP); 612 if (OF_hasprop(node, "bias-pull-down")) 613 return (AW_GPIO_PULLDOWN); 614 615 return (AW_GPIO_NONE); 616 } 617 618 static int 619 aw_gpio_parse_drive_strength(phandle_t node, uint32_t *drive) 620 { 621 uint32_t drive_str; 622 623 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1) 624 return (0); 625 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1) 626 return (0); 627 if (OF_getencprop(node, "drive-strength", &drive_str, 628 sizeof(drive_str)) != -1) { 629 *drive = (drive_str / 10) - 1; 630 return (0); 631 } 632 633 return (1); 634 } 635 636 static int 637 aw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 638 { 639 struct aw_gpio_softc *sc; 640 int ret; 641 642 sc = device_get_softc(dev); 643 644 AW_GPIO_LOCK(sc); 645 ret = aw_gpio_pin_get_locked(sc, pin, val); 646 AW_GPIO_UNLOCK(sc); 647 648 return (ret); 649 } 650 651 static int 652 aw_gpio_pin_toggle(device_t dev, uint32_t pin) 653 { 654 struct aw_gpio_softc *sc; 655 uint32_t bank, data; 656 657 sc = device_get_softc(dev); 658 if (pin > sc->padconf->npins) 659 return (EINVAL); 660 661 bank = sc->padconf->pins[pin].port; 662 pin = sc->padconf->pins[pin].pin; 663 664 AW_GPIO_LOCK(sc); 665 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 666 if (data & (1 << pin)) 667 data &= ~(1 << pin); 668 else 669 data |= (1 << pin); 670 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), data); 671 AW_GPIO_UNLOCK(sc); 672 673 return (0); 674 } 675 676 static int 677 aw_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 678 uint32_t change_pins, uint32_t *orig_pins) 679 { 680 struct aw_gpio_softc *sc; 681 uint32_t bank, data, pin; 682 683 sc = device_get_softc(dev); 684 if (first_pin > sc->padconf->npins) 685 return (EINVAL); 686 687 /* 688 * We require that first_pin refers to the first pin in a bank, because 689 * this API is not about convenience, it's for making a set of pins 690 * change simultaneously (required) with reasonably high performance 691 * (desired); we need to do a read-modify-write on a single register. 692 */ 693 bank = sc->padconf->pins[first_pin].port; 694 pin = sc->padconf->pins[first_pin].pin; 695 if (pin != 0) 696 return (EINVAL); 697 698 AW_GPIO_LOCK(sc); 699 data = AW_GPIO_READ(sc, AW_GPIO_GP_DAT(bank)); 700 if ((clear_pins | change_pins) != 0) 701 AW_GPIO_WRITE(sc, AW_GPIO_GP_DAT(bank), 702 (data & ~clear_pins) ^ change_pins); 703 AW_GPIO_UNLOCK(sc); 704 705 if (orig_pins != NULL) 706 *orig_pins = data; 707 708 return (0); 709 } 710 711 static int 712 aw_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 713 uint32_t *pin_flags) 714 { 715 struct aw_gpio_softc *sc; 716 uint32_t bank, pin; 717 int err; 718 719 sc = device_get_softc(dev); 720 if (first_pin > sc->padconf->npins) 721 return (EINVAL); 722 723 bank = sc->padconf->pins[first_pin].port; 724 if (sc->padconf->pins[first_pin].pin != 0) 725 return (EINVAL); 726 727 /* 728 * The configuration for a bank of pins is scattered among several 729 * registers; we cannot g'tee to simultaneously change the state of all 730 * the pins in the flags array. So just loop through the array 731 * configuring each pin for now. If there was a strong need, it might 732 * be possible to support some limited simultaneous config, such as 733 * adjacent groups of 8 pins that line up the same as the config regs. 734 */ 735 for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) { 736 if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 737 err = aw_gpio_pin_configure(sc, pin, pin_flags[pin]); 738 } 739 740 return (err); 741 } 742 743 static int 744 aw_find_pinnum_by_name(struct aw_gpio_softc *sc, const char *pinname) 745 { 746 int i; 747 748 for (i = 0; i < sc->padconf->npins; i++) 749 if (!strcmp(pinname, sc->padconf->pins[i].name)) 750 return i; 751 752 return (-1); 753 } 754 755 static int 756 aw_find_pin_func(struct aw_gpio_softc *sc, int pin, const char *func) 757 { 758 int i; 759 760 for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++) 761 if (sc->padconf->pins[pin].functions[i] && 762 !strcmp(func, sc->padconf->pins[pin].functions[i])) 763 return (i); 764 765 return (-1); 766 } 767 768 static int 769 aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) 770 { 771 struct aw_gpio_softc *sc; 772 phandle_t node; 773 const char **pinlist = NULL; 774 char *pin_function = NULL; 775 uint32_t pin_drive, pin_pull; 776 int pins_nb, pin_num, pin_func, i, ret; 777 bool set_drive; 778 779 sc = device_get_softc(dev); 780 node = OF_node_from_xref(cfgxref); 781 ret = 0; 782 set_drive = false; 783 784 /* Getting all prop for configuring pins */ 785 pinlist = aw_gpio_parse_pins(node, &pins_nb); 786 if (pinlist == NULL) 787 return (ENOENT); 788 789 pin_function = aw_gpio_parse_function(node); 790 if (pin_function == NULL) { 791 ret = ENOENT; 792 goto out; 793 } 794 795 if (aw_gpio_parse_drive_strength(node, &pin_drive) == 0) 796 set_drive = true; 797 798 pin_pull = aw_gpio_parse_bias(node); 799 800 /* Configure each pin to the correct function, drive and pull */ 801 for (i = 0; i < pins_nb; i++) { 802 pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); 803 if (pin_num == -1) { 804 ret = ENOENT; 805 goto out; 806 } 807 pin_func = aw_find_pin_func(sc, pin_num, pin_function); 808 if (pin_func == -1) { 809 ret = ENOENT; 810 goto out; 811 } 812 813 AW_GPIO_LOCK(sc); 814 815 if (aw_gpio_get_function(sc, pin_num) != pin_func) 816 aw_gpio_set_function(sc, pin_num, pin_func); 817 if (set_drive) 818 aw_gpio_set_drv(sc, pin_num, pin_drive); 819 if (pin_pull != AW_GPIO_NONE) 820 aw_gpio_set_pud(sc, pin_num, pin_pull); 821 822 AW_GPIO_UNLOCK(sc); 823 } 824 825 out: 826 OF_prop_free(pinlist); 827 OF_prop_free(pin_function); 828 return (ret); 829 } 830 831 static int 832 aw_gpio_probe(device_t dev) 833 { 834 835 if (!ofw_bus_status_okay(dev)) 836 return (ENXIO); 837 838 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 839 return (ENXIO); 840 841 device_set_desc(dev, "Allwinner GPIO/Pinmux controller"); 842 return (BUS_PROBE_DEFAULT); 843 } 844 845 static int 846 aw_gpio_attach(device_t dev) 847 { 848 int rid, error; 849 phandle_t gpio; 850 struct aw_gpio_softc *sc; 851 struct clk_list *clkp, *clkp_tmp; 852 clk_t clk; 853 hwreset_t rst = NULL; 854 int off, err, clkret; 855 856 sc = device_get_softc(dev); 857 sc->sc_dev = dev; 858 859 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN); 860 861 rid = 0; 862 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 863 RF_ACTIVE); 864 if (!sc->sc_mem_res) { 865 device_printf(dev, "cannot allocate memory window\n"); 866 goto fail; 867 } 868 869 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 870 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 871 872 rid = 0; 873 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 874 RF_ACTIVE); 875 if (!sc->sc_irq_res) { 876 device_printf(dev, "cannot allocate interrupt\n"); 877 goto fail; 878 } 879 880 /* Find our node. */ 881 gpio = ofw_bus_get_node(sc->sc_dev); 882 if (!OF_hasprop(gpio, "gpio-controller")) 883 /* Node is not a GPIO controller. */ 884 goto fail; 885 886 /* Use the right pin data for the current SoC */ 887 sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev, 888 compat_data)->ocd_data; 889 890 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 891 error = hwreset_deassert(rst); 892 if (error != 0) { 893 device_printf(dev, "cannot de-assert reset\n"); 894 goto fail; 895 } 896 } 897 898 TAILQ_INIT(&sc->clk_list); 899 for (off = 0, clkret = 0; clkret == 0; off++) { 900 clkret = clk_get_by_ofw_index(dev, 0, off, &clk); 901 if (clkret != 0) 902 break; 903 err = clk_enable(clk); 904 if (err != 0) { 905 device_printf(dev, "Could not enable clock %s\n", 906 clk_get_name(clk)); 907 goto fail; 908 } 909 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 910 clkp->clk = clk; 911 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 912 } 913 if (clkret != 0 && clkret != ENOENT) { 914 device_printf(dev, "Could not find clock at offset %d (%d)\n", 915 off, clkret); 916 goto fail; 917 } 918 919 sc->sc_busdev = gpiobus_attach_bus(dev); 920 if (sc->sc_busdev == NULL) 921 goto fail; 922 923 /* 924 * Register as a pinctrl device 925 */ 926 fdt_pinctrl_register(dev, "pins"); 927 fdt_pinctrl_configure_tree(dev); 928 fdt_pinctrl_register(dev, "allwinner,pins"); 929 fdt_pinctrl_configure_tree(dev); 930 931 return (0); 932 933 fail: 934 if (sc->sc_irq_res) 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 936 if (sc->sc_mem_res) 937 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 938 mtx_destroy(&sc->sc_mtx); 939 940 /* Disable clock */ 941 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 942 err = clk_disable(clkp->clk); 943 if (err != 0) 944 device_printf(dev, "Could not disable clock %s\n", 945 clk_get_name(clkp->clk)); 946 err = clk_release(clkp->clk); 947 if (err != 0) 948 device_printf(dev, "Could not release clock %s\n", 949 clk_get_name(clkp->clk)); 950 TAILQ_REMOVE(&sc->clk_list, clkp, next); 951 free(clkp, M_DEVBUF); 952 } 953 954 /* Assert resets */ 955 if (rst) { 956 hwreset_assert(rst); 957 hwreset_release(rst); 958 } 959 960 return (ENXIO); 961 } 962 963 static int 964 aw_gpio_detach(device_t dev) 965 { 966 967 return (EBUSY); 968 } 969 970 static phandle_t 971 aw_gpio_get_node(device_t dev, device_t bus) 972 { 973 974 /* We only have one child, the GPIO bus, which needs our own node. */ 975 return (ofw_bus_get_node(dev)); 976 } 977 978 static int 979 aw_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 980 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 981 { 982 struct aw_gpio_softc *sc; 983 int i; 984 985 sc = device_get_softc(bus); 986 987 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */ 988 for (i = 0; i < sc->padconf->npins; i++) 989 if (sc->padconf->pins[i].port == gpios[0] && 990 sc->padconf->pins[i].pin == gpios[1]) { 991 *pin = i; 992 break; 993 } 994 *flags = gpios[gcells - 1]; 995 996 return (0); 997 } 998 999 static device_method_t aw_gpio_methods[] = { 1000 /* Device interface */ 1001 DEVMETHOD(device_probe, aw_gpio_probe), 1002 DEVMETHOD(device_attach, aw_gpio_attach), 1003 DEVMETHOD(device_detach, aw_gpio_detach), 1004 1005 /* GPIO protocol */ 1006 DEVMETHOD(gpio_get_bus, aw_gpio_get_bus), 1007 DEVMETHOD(gpio_pin_max, aw_gpio_pin_max), 1008 DEVMETHOD(gpio_pin_getname, aw_gpio_pin_getname), 1009 DEVMETHOD(gpio_pin_getflags, aw_gpio_pin_getflags), 1010 DEVMETHOD(gpio_pin_getcaps, aw_gpio_pin_getcaps), 1011 DEVMETHOD(gpio_pin_setflags, aw_gpio_pin_setflags), 1012 DEVMETHOD(gpio_pin_get, aw_gpio_pin_get), 1013 DEVMETHOD(gpio_pin_set, aw_gpio_pin_set), 1014 DEVMETHOD(gpio_pin_toggle, aw_gpio_pin_toggle), 1015 DEVMETHOD(gpio_pin_access_32, aw_gpio_pin_access_32), 1016 DEVMETHOD(gpio_pin_config_32, aw_gpio_pin_config_32), 1017 DEVMETHOD(gpio_map_gpios, aw_gpio_map_gpios), 1018 1019 /* ofw_bus interface */ 1020 DEVMETHOD(ofw_bus_get_node, aw_gpio_get_node), 1021 1022 /* fdt_pinctrl interface */ 1023 DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins), 1024 1025 DEVMETHOD_END 1026 }; 1027 1028 static devclass_t aw_gpio_devclass; 1029 1030 static driver_t aw_gpio_driver = { 1031 "gpio", 1032 aw_gpio_methods, 1033 sizeof(struct aw_gpio_softc), 1034 }; 1035 1036 EARLY_DRIVER_MODULE(aw_gpio, simplebus, aw_gpio_driver, aw_gpio_devclass, 0, 0, 1037 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 1038