1 /*- 2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner Consumer IR controller 29 */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #include <dev/extres/clk/clk.h> 45 #include <dev/extres/hwreset/hwreset.h> 46 47 #include <dev/evdev/input.h> 48 #include <dev/evdev/evdev.h> 49 50 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r)) 51 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v)) 52 53 /* IR Control */ 54 #define AW_IR_CTL 0x00 55 /* Global Enable */ 56 #define AW_IR_CTL_GEN (1 << 0) 57 /* RX enable */ 58 #define AW_IR_CTL_RXEN (1 << 1) 59 /* CIR mode enable */ 60 #define AW_IR_CTL_MD (1 << 4) | (1 << 5) 61 62 /* RX Config Reg */ 63 #define AW_IR_RXCTL 0x10 64 /* Pulse Polarity Invert flag */ 65 #define AW_IR_RXCTL_RPPI (1 << 2) 66 67 /* RX Data */ 68 #define AW_IR_RXFIFO 0x20 69 70 /* RX Interrupt Control */ 71 #define AW_IR_RXINT 0x2C 72 /* RX FIFO Overflow */ 73 #define AW_IR_RXINT_ROI_EN (1 << 0) 74 /* RX Packet End */ 75 #define AW_IR_RXINT_RPEI_EN (1 << 1) 76 /* RX FIFO Data Available */ 77 #define AW_IR_RXINT_RAI_EN (1 << 4) 78 /* RX FIFO available byte level */ 79 #define AW_IR_RXINT_RAL(val) ((val) << 8) 80 81 /* RX Interrupt Status Reg */ 82 #define AW_IR_RXSTA 0x30 83 /* RX FIFO Get Available Counter */ 84 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1)) 85 /* Clear all interrupt status */ 86 #define AW_IR_RXSTA_CLEARALL 0xff 87 88 /* IR Sample Configure Reg */ 89 #define AW_IR_CIR 0x34 90 91 /* 92 * Frequency sample: 23437.5Hz (Cycle: 42.7us) 93 * Pulse of NEC Remote > 560us 94 */ 95 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */ 96 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2) 97 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */ 98 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8) 99 100 /* Bit 15 - value (pulse/space) */ 101 #define VAL_MASK 0x80 102 /* Bits 0:14 - sample duration */ 103 #define PERIOD_MASK 0x7f 104 105 /* Clock rate for IR0 or IR1 clock in CIR mode */ 106 #define AW_IR_BASE_CLK 3000000 107 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */ 108 #define AW_IR_SAMPLE_64 (0 << 0) 109 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */ 110 #define AW_IR_SAMPLE_128 (1 << 0) 111 112 #define AW_IR_ERROR_CODE 0xffffffff 113 #define AW_IR_REPEAT_CODE 0x0 114 115 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */ 116 #define AW_IR_L1_MIN 80 117 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */ 118 #define AW_IR_L0_MIN 40 119 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */ 120 #define AW_IR_PMAX 26 121 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */ 122 #define AW_IR_DMID 26 123 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */ 124 #define AW_IR_DMAX 53 125 126 /* Active Thresholds */ 127 #define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN 128 #define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16) 129 #define AW_IR_ACTIVE_T_C_VAL 0 130 #define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23) 131 132 /* Code masks */ 133 #define CODE_MASK 0x00ff00ff 134 #define INV_CODE_MASK 0xff00ff00 135 #define VALID_CODE_MASK 0x00ff0000 136 137 enum { 138 A10_IR = 1, 139 A13_IR, 140 A31_IR, 141 }; 142 143 #define AW_IR_RAW_BUF_SIZE 128 144 145 SYSCTL_NODE(_hw, OID_AUTO, aw_cir, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 146 "aw_cir driver"); 147 148 static int aw_cir_debug = 0; 149 SYSCTL_INT(_hw_aw_cir, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_cir_debug, 0, 150 "Debug 1=on 0=off"); 151 152 struct aw_ir_softc { 153 device_t dev; 154 struct resource *res[2]; 155 void * intrhand; 156 int fifo_size; 157 int dcnt; /* Packet Count */ 158 unsigned char buf[AW_IR_RAW_BUF_SIZE]; 159 struct evdev_dev *sc_evdev; 160 }; 161 162 static struct resource_spec aw_ir_spec[] = { 163 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 164 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 165 { -1, 0 } 166 }; 167 168 static struct ofw_compat_data compat_data[] = { 169 { "allwinner,sun4i-a10-ir", A10_IR }, 170 { "allwinner,sun5i-a13-ir", A13_IR }, 171 { "allwinner,sun6i-a31-ir", A31_IR }, 172 { NULL, 0 } 173 }; 174 175 static void 176 aw_ir_buf_reset(struct aw_ir_softc *sc) 177 { 178 179 sc->dcnt = 0; 180 } 181 182 static void 183 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data) 184 { 185 186 if (sc->dcnt < AW_IR_RAW_BUF_SIZE) 187 sc->buf[sc->dcnt++] = data; 188 else 189 if (bootverbose) 190 device_printf(sc->dev, "IR RX Buffer Full!\n"); 191 } 192 193 static int 194 aw_ir_buf_full(struct aw_ir_softc *sc) 195 { 196 197 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE); 198 } 199 200 static unsigned char 201 aw_ir_read_data(struct aw_ir_softc *sc) 202 { 203 204 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff); 205 } 206 207 static unsigned long 208 aw_ir_decode_packets(struct aw_ir_softc *sc) 209 { 210 unsigned int len, code; 211 unsigned int active_delay; 212 unsigned char val, last; 213 int i, bitcount; 214 215 if (bootverbose && __predict_false(aw_cir_debug) != 0) 216 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt); 217 218 /* Find Lead 1 (bit separator) */ 219 active_delay = AW_IR_ACTIVE_T_VAL * 220 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1); 221 len = active_delay; 222 if (bootverbose && __predict_false(aw_cir_debug) != 0) 223 device_printf(sc->dev, "Initial len: %d\n", len); 224 for (i = 0; i < sc->dcnt; i++) { 225 val = sc->buf[i]; 226 if (val & VAL_MASK) 227 len += (val & PERIOD_MASK) + 1; 228 else { 229 if (len > AW_IR_L1_MIN) 230 break; 231 len = 0; 232 } 233 } 234 if (bootverbose && __predict_false(aw_cir_debug) != 0) 235 device_printf(sc->dev, "len = %d\n", len); 236 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) { 237 if (bootverbose && __predict_false(aw_cir_debug) != 0) 238 device_printf(sc->dev, "Bit separator error\n"); 239 goto error_code; 240 } 241 242 /* Find Lead 0 (bit length) */ 243 len = 0; 244 for (; i < sc->dcnt; i++) { 245 val = sc->buf[i]; 246 if (val & VAL_MASK) { 247 if(len > AW_IR_L0_MIN) 248 break; 249 len = 0; 250 } else 251 len += (val & PERIOD_MASK) + 1; 252 } 253 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) { 254 if (bootverbose && __predict_false(aw_cir_debug) != 0) 255 device_printf(sc->dev, "Bit length error\n"); 256 goto error_code; 257 } 258 259 /* Start decoding */ 260 code = 0; 261 bitcount = 0; 262 last = 1; 263 len = 0; 264 for (; i < sc->dcnt; i++) { 265 val = sc->buf[i]; 266 if (last) { 267 if (val & VAL_MASK) 268 len += (val & PERIOD_MASK) + 1; 269 else { 270 if (len > AW_IR_PMAX) { 271 if (bootverbose) 272 device_printf(sc->dev, 273 "Pulse error, len=%d\n", 274 len); 275 goto error_code; 276 } 277 last = 0; 278 len = (val & PERIOD_MASK) + 1; 279 } 280 } else { 281 if (val & VAL_MASK) { 282 if (len > AW_IR_DMAX) { 283 if (bootverbose) 284 device_printf(sc->dev, 285 "Distance error, len=%d\n", 286 len); 287 goto error_code; 288 } else { 289 if (len > AW_IR_DMID) { 290 /* Decode */ 291 code |= 1 << bitcount; 292 } 293 bitcount++; 294 if (bitcount == 32) 295 break; /* Finish decoding */ 296 } 297 last = 1; 298 len = (val & PERIOD_MASK) + 1; 299 } else 300 len += (val & PERIOD_MASK) + 1; 301 } 302 } 303 return (code); 304 305 error_code: 306 307 return (AW_IR_ERROR_CODE); 308 } 309 310 static int 311 aw_ir_validate_code(unsigned long code) 312 { 313 unsigned long v1, v2; 314 315 /* Don't check address */ 316 v1 = code & CODE_MASK; 317 v2 = (code & INV_CODE_MASK) >> 8; 318 319 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK) 320 return (0); /* valid */ 321 else 322 return (1); /* invalid */ 323 } 324 325 static void 326 aw_ir_intr(void *arg) 327 { 328 struct aw_ir_softc *sc; 329 uint32_t val; 330 int i, dcnt; 331 unsigned long ir_code; 332 int stat; 333 334 sc = (struct aw_ir_softc *)arg; 335 336 /* Read RX interrupt status */ 337 val = READ(sc, AW_IR_RXSTA); 338 if (bootverbose && __predict_false(aw_cir_debug) != 0) 339 device_printf(sc->dev, "RX interrupt status: %x\n", val); 340 341 /* Clean all pending interrupt statuses */ 342 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL); 343 344 /* When Rx FIFO Data available or Packet end */ 345 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) { 346 if (bootverbose && __predict_false(aw_cir_debug) != 0) 347 device_printf(sc->dev, 348 "RX FIFO Data available or Packet end\n"); 349 /* Get available message count in RX FIFO */ 350 dcnt = AW_IR_RXSTA_COUNTER(val); 351 /* Read FIFO */ 352 for (i = 0; i < dcnt; i++) { 353 if (aw_ir_buf_full(sc)) { 354 if (bootverbose) 355 device_printf(sc->dev, 356 "raw buffer full\n"); 357 break; 358 } else 359 aw_ir_buf_write(sc, aw_ir_read_data(sc)); 360 } 361 } 362 363 if (val & AW_IR_RXINT_RPEI_EN) { 364 /* RX Packet end */ 365 if (bootverbose && __predict_false(aw_cir_debug) != 0) 366 device_printf(sc->dev, "RX Packet end\n"); 367 ir_code = aw_ir_decode_packets(sc); 368 stat = aw_ir_validate_code(ir_code); 369 if (stat == 0) { 370 evdev_push_event(sc->sc_evdev, 371 EV_MSC, MSC_SCAN, ir_code); 372 evdev_sync(sc->sc_evdev); 373 } 374 if (bootverbose && __predict_false(aw_cir_debug) != 0) { 375 device_printf(sc->dev, "Final IR code: %lx\n", 376 ir_code); 377 device_printf(sc->dev, "IR code status: %d\n", 378 stat); 379 } 380 aw_ir_buf_reset(sc); 381 } 382 if (val & AW_IR_RXINT_ROI_EN) { 383 /* RX FIFO overflow */ 384 if (bootverbose) 385 device_printf(sc->dev, "RX FIFO overflow\n"); 386 /* Flush raw buffer */ 387 aw_ir_buf_reset(sc); 388 } 389 } 390 391 static int 392 aw_ir_probe(device_t dev) 393 { 394 395 if (!ofw_bus_status_okay(dev)) 396 return (ENXIO); 397 398 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 399 return (ENXIO); 400 401 device_set_desc(dev, "Allwinner CIR controller"); 402 return (BUS_PROBE_DEFAULT); 403 } 404 405 static int 406 aw_ir_attach(device_t dev) 407 { 408 struct aw_ir_softc *sc; 409 hwreset_t rst_apb; 410 clk_t clk_ir, clk_gate; 411 int err; 412 uint32_t val = 0; 413 414 clk_ir = clk_gate = NULL; 415 rst_apb = NULL; 416 417 sc = device_get_softc(dev); 418 sc->dev = dev; 419 420 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) { 421 device_printf(dev, "could not allocate memory resource\n"); 422 return (ENXIO); 423 } 424 425 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 426 case A10_IR: 427 sc->fifo_size = 16; 428 break; 429 case A13_IR: 430 case A31_IR: 431 sc->fifo_size = 64; 432 break; 433 } 434 435 /* De-assert reset */ 436 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) { 437 err = hwreset_deassert(rst_apb); 438 if (err != 0) { 439 device_printf(dev, "cannot de-assert reset\n"); 440 goto error; 441 } 442 } 443 444 /* Reset buffer */ 445 aw_ir_buf_reset(sc); 446 447 /* Get clocks and enable them */ 448 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate); 449 if (err != 0) { 450 device_printf(dev, "Cannot get gate clock\n"); 451 goto error; 452 } 453 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir); 454 if (err != 0) { 455 device_printf(dev, "Cannot get IR clock\n"); 456 goto error; 457 } 458 /* Set clock rate */ 459 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0); 460 if (err != 0) { 461 device_printf(dev, "cannot set IR clock rate\n"); 462 goto error; 463 } 464 /* Enable clocks */ 465 err = clk_enable(clk_gate); 466 if (err != 0) { 467 device_printf(dev, "Cannot enable clk gate\n"); 468 goto error; 469 } 470 err = clk_enable(clk_ir); 471 if (err != 0) { 472 device_printf(dev, "Cannot enable IR clock\n"); 473 goto error; 474 } 475 476 if (bus_setup_intr(dev, sc->res[1], 477 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc, 478 &sc->intrhand)) { 479 bus_release_resources(dev, aw_ir_spec, sc->res); 480 device_printf(dev, "cannot setup interrupt handler\n"); 481 err = ENXIO; 482 goto error; 483 } 484 485 /* Enable CIR Mode */ 486 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD); 487 488 /* 489 * Set clock sample, filter, idle thresholds. 490 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) 491 */ 492 val = AW_IR_SAMPLE_128; 493 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL); 494 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C); 495 WRITE(sc, AW_IR_CIR, val); 496 497 /* Invert Input Signal */ 498 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI); 499 500 /* Clear All RX Interrupt Status */ 501 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL); 502 503 /* 504 * Enable RX interrupt in case of overflow, packet end 505 * and FIFO available. 506 * RX FIFO Threshold = FIFO size / 2 507 */ 508 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN | 509 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1)); 510 511 /* Enable IR Module */ 512 val = READ(sc, AW_IR_CTL); 513 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN); 514 515 sc->sc_evdev = evdev_alloc(); 516 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev)); 517 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev)); 518 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0); 519 evdev_support_event(sc->sc_evdev, EV_SYN); 520 evdev_support_event(sc->sc_evdev, EV_MSC); 521 evdev_support_msc(sc->sc_evdev, MSC_SCAN); 522 523 err = evdev_register(sc->sc_evdev); 524 if (err) { 525 device_printf(dev, 526 "failed to register evdev: error=%d\n", err); 527 goto error; 528 } 529 530 return (0); 531 error: 532 if (clk_gate != NULL) 533 clk_release(clk_gate); 534 if (clk_ir != NULL) 535 clk_release(clk_ir); 536 if (rst_apb != NULL) 537 hwreset_release(rst_apb); 538 evdev_free(sc->sc_evdev); 539 sc->sc_evdev = NULL; /* Avoid double free */ 540 541 bus_release_resources(dev, aw_ir_spec, sc->res); 542 return (ENXIO); 543 } 544 545 static device_method_t aw_ir_methods[] = { 546 DEVMETHOD(device_probe, aw_ir_probe), 547 DEVMETHOD(device_attach, aw_ir_attach), 548 549 DEVMETHOD_END 550 }; 551 552 static driver_t aw_ir_driver = { 553 "aw_ir", 554 aw_ir_methods, 555 sizeof(struct aw_ir_softc), 556 }; 557 558 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, 0, 0); 559 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1); 560