1 /*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/kernel.h>
31 #include <sys/module.h>
32 #include <sys/malloc.h>
33 #include <sys/rman.h>
34 #include <sys/timeet.h>
35 #include <sys/timetc.h>
36 #include <sys/watchdog.h>
37 #include <machine/bus.h>
38 #include <machine/intr.h>
39 #include <machine/machdep.h>
40
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44
45 #include <dev/clk/clk.h>
46
47 #if defined(__aarch64__)
48 #include "opt_soc.h"
49 #else
50 #include <arm/allwinner/aw_machdep.h>
51 #endif
52
53 /**
54 * Timer registers addr
55 *
56 */
57 #define TIMER_IRQ_EN_REG 0x00
58 #define TIMER_IRQ_ENABLE(x) (1 << x)
59
60 #define TIMER_IRQ_STA_REG 0x04
61 #define TIMER_IRQ_PENDING(x) (1 << x)
62
63 /*
64 * On A10, A13, A20 and A31/A31s 6 timers are available
65 */
66 #define TIMER_CTRL_REG(x) (0x10 + 0x10 * x)
67 #define TIMER_CTRL_START (1 << 0)
68 #define TIMER_CTRL_AUTORELOAD (1 << 1)
69 #define TIMER_CTRL_CLKSRC_MASK (3 << 2)
70 #define TIMER_CTRL_OSC24M (1 << 2)
71 #define TIMER_CTRL_PRESCALAR_MASK (0x7 << 4)
72 #define TIMER_CTRL_PRESCALAR(x) ((x - 1) << 4)
73 #define TIMER_CTRL_MODE_MASK (1 << 7)
74 #define TIMER_CTRL_MODE_SINGLE (1 << 7)
75 #define TIMER_CTRL_MODE_CONTINUOUS (0 << 7)
76 #define TIMER_INTV_REG(x) (0x14 + 0x10 * x)
77 #define TIMER_CURV_REG(x) (0x18 + 0x10 * x)
78
79 /* 64 bit counter, available in A10 and A13 */
80 #define CNT64_CTRL_REG 0xa0
81 #define CNT64_CTRL_RL_EN 0x02 /* read latch enable */
82 #define CNT64_LO_REG 0xa4
83 #define CNT64_HI_REG 0xa8
84
85 #define SYS_TIMER_CLKSRC 24000000 /* clock source */
86
87 enum a10_timer_type {
88 A10_TIMER = 1,
89 A23_TIMER,
90 };
91
92 struct a10_timer_softc {
93 device_t sc_dev;
94 struct resource *res[2];
95 void *sc_ih; /* interrupt handler */
96 uint32_t sc_period;
97 uint64_t timer0_freq;
98 struct eventtimer et;
99 enum a10_timer_type type;
100 };
101
102 #define timer_read_4(sc, reg) \
103 bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
104 #define timer_write_4(sc, reg, val) \
105 bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
106
107 static u_int a10_timer_get_timecount(struct timecounter *);
108 #if defined(__arm__)
109 static int a10_timer_timer_start(struct eventtimer *,
110 sbintime_t first, sbintime_t period);
111 static int a10_timer_timer_stop(struct eventtimer *);
112 #endif
113
114 static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
115 #if defined(__arm__)
116 static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
117 #endif
118
119 #if defined(__aarch64__)
120 static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
121 static u_int a23_timer_get_timecount(struct timecounter *tc);
122 #endif
123
124 static int a10_timer_irq(void *);
125 static int a10_timer_probe(device_t);
126 static int a10_timer_attach(device_t);
127
128 #if defined(__arm__)
129 static delay_func a10_timer_delay;
130 #endif
131
132 static struct timecounter a10_timer_timecounter = {
133 .tc_name = "a10_timer timer0",
134 .tc_get_timecount = a10_timer_get_timecount,
135 .tc_counter_mask = ~0u,
136 .tc_frequency = 0,
137 .tc_quality = 1000,
138 };
139
140 #if defined(__aarch64__)
141 static struct timecounter a23_timer_timecounter = {
142 .tc_name = "a10_timer timer0",
143 .tc_get_timecount = a23_timer_get_timecount,
144 .tc_counter_mask = ~0u,
145 .tc_frequency = 0,
146 /* We want it to be selected over the arm generic timecounter */
147 .tc_quality = 2000,
148 };
149 #endif
150
151 #define A10_TIMER_MEMRES 0
152 #define A10_TIMER_IRQRES 1
153
154 static struct resource_spec a10_timer_spec[] = {
155 { SYS_RES_MEMORY, 0, RF_ACTIVE },
156 { SYS_RES_IRQ, 0, RF_ACTIVE },
157 { -1, 0 }
158 };
159
160 static struct ofw_compat_data compat_data[] = {
161 {"allwinner,sun4i-a10-timer", A10_TIMER},
162 #if defined(__aarch64__)
163 {"allwinner,sun8i-a23-timer", A23_TIMER},
164 #endif
165 {NULL, 0},
166 };
167
168 static int
a10_timer_probe(device_t dev)169 a10_timer_probe(device_t dev)
170 {
171 #if defined(__arm__)
172 u_int soc_family;
173 #endif
174
175 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
176 return (ENXIO);
177
178 #if defined(__arm__)
179 /* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
180 soc_family = allwinner_soc_family();
181 if (soc_family != ALLWINNERSOC_SUN4I &&
182 soc_family != ALLWINNERSOC_SUN5I)
183 return (ENXIO);
184 #endif
185
186 device_set_desc(dev, "Allwinner timer");
187 return (BUS_PROBE_DEFAULT);
188 }
189
190 static int
a10_timer_attach(device_t dev)191 a10_timer_attach(device_t dev)
192 {
193 struct a10_timer_softc *sc;
194 clk_t clk;
195 int err;
196
197 sc = device_get_softc(dev);
198 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
199
200 if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
201 device_printf(dev, "could not allocate resources\n");
202 return (ENXIO);
203 }
204
205 sc->sc_dev = dev;
206
207 /* Setup and enable the timer interrupt */
208 err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
209 a10_timer_irq, NULL, sc, &sc->sc_ih);
210 if (err != 0) {
211 bus_release_resources(dev, a10_timer_spec, sc->res);
212 device_printf(dev, "Unable to setup the clock irq handler, "
213 "err = %d\n", err);
214 return (ENXIO);
215 }
216
217 if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
218 sc->timer0_freq = SYS_TIMER_CLKSRC;
219 else {
220 if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
221 device_printf(dev, "Cannot get clock source frequency\n");
222 return (ENXIO);
223 }
224 }
225
226 #if defined(__arm__)
227 a10_timer_eventtimer_setup(sc);
228 arm_set_delay(a10_timer_delay, sc);
229 a10_timer_timecounter.tc_priv = sc;
230 a10_timer_timecounter.tc_frequency = sc->timer0_freq;
231 tc_init(&a10_timer_timecounter);
232 #elif defined(__aarch64__)
233 a23_timer_timecounter_setup(sc);
234 #endif
235
236 if (bootverbose) {
237 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
238
239 device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
240 sc->timer0_freq);
241 device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
242 a10_timer_timecounter.tc_frequency);
243 }
244
245 return (0);
246 }
247
248 static int
a10_timer_irq(void * arg)249 a10_timer_irq(void *arg)
250 {
251 struct a10_timer_softc *sc;
252 uint32_t val;
253
254 sc = (struct a10_timer_softc *)arg;
255
256 /* Clear interrupt pending bit. */
257 timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
258
259 val = timer_read_4(sc, TIMER_CTRL_REG(0));
260
261 /*
262 * Disabled autoreload and sc_period > 0 means
263 * timer_start was called with non NULL first value.
264 * Now we will set periodic timer with the given period
265 * value.
266 */
267 if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
268 /* Update timer */
269 timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
270
271 /* Make periodic and enable */
272 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
273 timer_write_4(sc, TIMER_CTRL_REG(0), val);
274 }
275
276 if (sc->et.et_active)
277 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
278
279 return (FILTER_HANDLED);
280 }
281
282 /*
283 * Event timer function for A10 and A13
284 */
285
286 #if defined(__arm__)
287 static void
a10_timer_eventtimer_setup(struct a10_timer_softc * sc)288 a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
289 {
290 uint32_t val;
291
292 /* Set clock source to OSC24M, 1 pre-division, continuous mode */
293 val = timer_read_4(sc, TIMER_CTRL_REG(0));
294 val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
295 val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
296 timer_write_4(sc, TIMER_CTRL_REG(0), val);
297
298 /* Enable timer0 */
299 val = timer_read_4(sc, TIMER_IRQ_EN_REG);
300 val |= TIMER_IRQ_ENABLE(0);
301 timer_write_4(sc, TIMER_IRQ_EN_REG, val);
302
303 /* Set desired frequency in event timer and timecounter */
304 sc->et.et_frequency = sc->timer0_freq;
305 sc->et.et_name = "a10_timer Eventtimer";
306 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
307 sc->et.et_quality = 1000;
308 sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
309 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
310 sc->et.et_start = a10_timer_timer_start;
311 sc->et.et_stop = a10_timer_timer_stop;
312 sc->et.et_priv = sc;
313 et_register(&sc->et);
314 }
315
316 static int
a10_timer_timer_start(struct eventtimer * et,sbintime_t first,sbintime_t period)317 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
318 sbintime_t period)
319 {
320 struct a10_timer_softc *sc;
321 uint32_t count;
322 uint32_t val;
323
324 sc = (struct a10_timer_softc *)et->et_priv;
325
326 if (period != 0)
327 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
328 else
329 sc->sc_period = 0;
330 if (first != 0)
331 count = ((uint32_t)et->et_frequency * first) >> 32;
332 else
333 count = sc->sc_period;
334
335 /* Update timer values */
336 timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
337 timer_write_4(sc, TIMER_CURV_REG(0), count);
338
339 val = timer_read_4(sc, TIMER_CTRL_REG(0));
340 if (period != 0) {
341 /* periodic */
342 val |= TIMER_CTRL_AUTORELOAD;
343 } else {
344 /* oneshot */
345 val &= ~TIMER_CTRL_AUTORELOAD;
346 }
347 /* Enable timer0 */
348 val |= TIMER_IRQ_ENABLE(0);
349 timer_write_4(sc, TIMER_CTRL_REG(0), val);
350
351 return (0);
352 }
353
354 static int
a10_timer_timer_stop(struct eventtimer * et)355 a10_timer_timer_stop(struct eventtimer *et)
356 {
357 struct a10_timer_softc *sc;
358 uint32_t val;
359
360 sc = (struct a10_timer_softc *)et->et_priv;
361
362 /* Disable timer0 */
363 val = timer_read_4(sc, TIMER_CTRL_REG(0));
364 val &= ~TIMER_CTRL_START;
365 timer_write_4(sc, TIMER_CTRL_REG(0), val);
366
367 sc->sc_period = 0;
368
369 return (0);
370 }
371 #endif
372
373 /*
374 * Timecounter functions for A23 and above
375 */
376
377 #if defined(__aarch64__)
378 static void
a23_timer_timecounter_setup(struct a10_timer_softc * sc)379 a23_timer_timecounter_setup(struct a10_timer_softc *sc)
380 {
381 uint32_t val;
382
383 /* Set clock source to OSC24M, 1 pre-division, continuous mode */
384 val = timer_read_4(sc, TIMER_CTRL_REG(0));
385 val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
386 val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
387 timer_write_4(sc, TIMER_CTRL_REG(0), val);
388
389 /* Set reload value */
390 timer_write_4(sc, TIMER_INTV_REG(0), ~0);
391 val = timer_read_4(sc, TIMER_INTV_REG(0));
392
393 /* Enable timer0 */
394 val = timer_read_4(sc, TIMER_CTRL_REG(0));
395 val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
396 timer_write_4(sc, TIMER_CTRL_REG(0), val);
397
398 val = timer_read_4(sc, TIMER_CURV_REG(0));
399
400 a23_timer_timecounter.tc_priv = sc;
401 a23_timer_timecounter.tc_frequency = sc->timer0_freq;
402 tc_init(&a23_timer_timecounter);
403 }
404
405 static u_int
a23_timer_get_timecount(struct timecounter * tc)406 a23_timer_get_timecount(struct timecounter *tc)
407 {
408 struct a10_timer_softc *sc;
409 uint32_t val;
410
411 sc = (struct a10_timer_softc *)tc->tc_priv;
412 if (sc == NULL)
413 return (0);
414
415 val = timer_read_4(sc, TIMER_CURV_REG(0));
416 /* Counter count backwards */
417 return (~0u - val);
418 }
419 #endif
420
421 /*
422 * Timecounter functions for A10 and A13, using the 64 bits counter
423 */
424
425 static uint64_t
timer_read_counter64(struct a10_timer_softc * sc)426 timer_read_counter64(struct a10_timer_softc *sc)
427 {
428 uint32_t lo, hi;
429
430 /* Latch counter, wait for it to be ready to read. */
431 timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
432 while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
433 continue;
434
435 hi = timer_read_4(sc, CNT64_HI_REG);
436 lo = timer_read_4(sc, CNT64_LO_REG);
437
438 return (((uint64_t)hi << 32) | lo);
439 }
440
441 #if defined(__arm__)
442 static void
a10_timer_delay(int usec,void * arg)443 a10_timer_delay(int usec, void *arg)
444 {
445 struct a10_timer_softc *sc = arg;
446 uint64_t end, now;
447
448 now = timer_read_counter64(sc);
449 end = now + (sc->timer0_freq / 1000000) * (usec + 1);
450
451 while (now < end)
452 now = timer_read_counter64(sc);
453 }
454 #endif
455
456 static u_int
a10_timer_get_timecount(struct timecounter * tc)457 a10_timer_get_timecount(struct timecounter *tc)
458 {
459
460 if (tc->tc_priv == NULL)
461 return (0);
462
463 return ((u_int)timer_read_counter64(tc->tc_priv));
464 }
465
466 static device_method_t a10_timer_methods[] = {
467 DEVMETHOD(device_probe, a10_timer_probe),
468 DEVMETHOD(device_attach, a10_timer_attach),
469
470 DEVMETHOD_END
471 };
472
473 static driver_t a10_timer_driver = {
474 "a10_timer",
475 a10_timer_methods,
476 sizeof(struct a10_timer_softc),
477 };
478
479 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, 0, 0,
480 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
481