1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _VMM_DEV_H_ 32 #define _VMM_DEV_H_ 33 34 struct vm_snapshot_meta; 35 36 #ifdef _KERNEL 37 void vmmdev_init(void); 38 int vmmdev_cleanup(void); 39 #endif 40 41 struct vm_memmap { 42 vm_paddr_t gpa; 43 int segid; /* memory segment */ 44 vm_ooffset_t segoff; /* offset into memory segment */ 45 size_t len; /* mmap length */ 46 int prot; /* RWX */ 47 int flags; 48 }; 49 #define VM_MEMMAP_F_WIRED 0x01 50 #define VM_MEMMAP_F_IOMMU 0x02 51 52 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL) 53 struct vm_memseg { 54 int segid; 55 size_t len; 56 char name[VM_MAX_SUFFIXLEN + 1]; 57 }; 58 59 struct vm_memseg_fbsd12 { 60 int segid; 61 size_t len; 62 char name[64]; 63 }; 64 _Static_assert(sizeof(struct vm_memseg_fbsd12) == 80, "COMPAT_FREEBSD12 ABI"); 65 66 struct vm_register { 67 int cpuid; 68 int regnum; /* enum vm_reg_name */ 69 uint64_t regval; 70 }; 71 72 struct vm_seg_desc { /* data or code segment */ 73 int cpuid; 74 int regnum; /* enum vm_reg_name */ 75 struct seg_desc desc; 76 }; 77 78 struct vm_register_set { 79 int cpuid; 80 unsigned int count; 81 const int *regnums; /* enum vm_reg_name */ 82 uint64_t *regvals; 83 }; 84 85 struct vm_run { 86 int cpuid; 87 struct vm_exit vm_exit; 88 }; 89 90 struct vm_exception { 91 int cpuid; 92 int vector; 93 uint32_t error_code; 94 int error_code_valid; 95 int restart_instruction; 96 }; 97 98 struct vm_lapic_msi { 99 uint64_t msg; 100 uint64_t addr; 101 }; 102 103 struct vm_lapic_irq { 104 int cpuid; 105 int vector; 106 }; 107 108 struct vm_ioapic_irq { 109 int irq; 110 }; 111 112 struct vm_isa_irq { 113 int atpic_irq; 114 int ioapic_irq; 115 }; 116 117 struct vm_isa_irq_trigger { 118 int atpic_irq; 119 enum vm_intr_trigger trigger; 120 }; 121 122 struct vm_capability { 123 int cpuid; 124 enum vm_cap_type captype; 125 int capval; 126 int allcpus; 127 }; 128 129 struct vm_pptdev { 130 int bus; 131 int slot; 132 int func; 133 }; 134 135 struct vm_pptdev_mmio { 136 int bus; 137 int slot; 138 int func; 139 vm_paddr_t gpa; 140 vm_paddr_t hpa; 141 size_t len; 142 }; 143 144 struct vm_pptdev_msi { 145 int vcpu; 146 int bus; 147 int slot; 148 int func; 149 int numvec; /* 0 means disabled */ 150 uint64_t msg; 151 uint64_t addr; 152 }; 153 154 struct vm_pptdev_msix { 155 int vcpu; 156 int bus; 157 int slot; 158 int func; 159 int idx; 160 uint64_t msg; 161 uint32_t vector_control; 162 uint64_t addr; 163 }; 164 165 struct vm_nmi { 166 int cpuid; 167 }; 168 169 #define MAX_VM_STATS 64 170 struct vm_stats { 171 int cpuid; /* in */ 172 int num_entries; /* out */ 173 struct timeval tv; 174 uint64_t statbuf[MAX_VM_STATS]; 175 }; 176 177 struct vm_stat_desc { 178 int index; /* in */ 179 char desc[128]; /* out */ 180 }; 181 182 struct vm_x2apic { 183 int cpuid; 184 enum x2apic_state state; 185 }; 186 187 struct vm_gpa_pte { 188 uint64_t gpa; /* in */ 189 uint64_t pte[4]; /* out */ 190 int ptenum; 191 }; 192 193 struct vm_hpet_cap { 194 uint32_t capabilities; /* lower 32 bits of HPET capabilities */ 195 }; 196 197 struct vm_suspend { 198 enum vm_suspend_how how; 199 }; 200 201 struct vm_gla2gpa { 202 int vcpuid; /* inputs */ 203 int prot; /* PROT_READ or PROT_WRITE */ 204 uint64_t gla; 205 struct vm_guest_paging paging; 206 int fault; /* outputs */ 207 uint64_t gpa; 208 }; 209 210 struct vm_activate_cpu { 211 int vcpuid; 212 }; 213 214 struct vm_cpuset { 215 int which; 216 int cpusetsize; 217 cpuset_t *cpus; 218 }; 219 #define VM_ACTIVE_CPUS 0 220 #define VM_SUSPENDED_CPUS 1 221 #define VM_DEBUG_CPUS 2 222 223 struct vm_intinfo { 224 int vcpuid; 225 uint64_t info1; 226 uint64_t info2; 227 }; 228 229 struct vm_rtc_time { 230 time_t secs; 231 }; 232 233 struct vm_rtc_data { 234 int offset; 235 uint8_t value; 236 }; 237 238 struct vm_cpu_topology { 239 uint16_t sockets; 240 uint16_t cores; 241 uint16_t threads; 242 uint16_t maxcpus; 243 }; 244 245 struct vm_readwrite_kernemu_device { 246 int vcpuid; 247 unsigned access_width : 3; 248 unsigned _unused : 29; 249 uint64_t gpa; 250 uint64_t value; 251 }; 252 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI"); 253 254 enum { 255 /* general routines */ 256 IOCNUM_ABIVERS = 0, 257 IOCNUM_RUN = 1, 258 IOCNUM_SET_CAPABILITY = 2, 259 IOCNUM_GET_CAPABILITY = 3, 260 IOCNUM_SUSPEND = 4, 261 IOCNUM_REINIT = 5, 262 263 /* memory apis */ 264 IOCNUM_MAP_MEMORY = 10, /* deprecated */ 265 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */ 266 IOCNUM_GET_GPA_PMAP = 12, 267 IOCNUM_GLA2GPA = 13, 268 IOCNUM_ALLOC_MEMSEG = 14, 269 IOCNUM_GET_MEMSEG = 15, 270 IOCNUM_MMAP_MEMSEG = 16, 271 IOCNUM_MMAP_GETNEXT = 17, 272 IOCNUM_GLA2GPA_NOFAULT = 18, 273 274 /* register/state accessors */ 275 IOCNUM_SET_REGISTER = 20, 276 IOCNUM_GET_REGISTER = 21, 277 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22, 278 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23, 279 IOCNUM_SET_REGISTER_SET = 24, 280 IOCNUM_GET_REGISTER_SET = 25, 281 IOCNUM_GET_KERNEMU_DEV = 26, 282 IOCNUM_SET_KERNEMU_DEV = 27, 283 284 /* interrupt injection */ 285 IOCNUM_GET_INTINFO = 28, 286 IOCNUM_SET_INTINFO = 29, 287 IOCNUM_INJECT_EXCEPTION = 30, 288 IOCNUM_LAPIC_IRQ = 31, 289 IOCNUM_INJECT_NMI = 32, 290 IOCNUM_IOAPIC_ASSERT_IRQ = 33, 291 IOCNUM_IOAPIC_DEASSERT_IRQ = 34, 292 IOCNUM_IOAPIC_PULSE_IRQ = 35, 293 IOCNUM_LAPIC_MSI = 36, 294 IOCNUM_LAPIC_LOCAL_IRQ = 37, 295 IOCNUM_IOAPIC_PINCOUNT = 38, 296 IOCNUM_RESTART_INSTRUCTION = 39, 297 298 /* PCI pass-thru */ 299 IOCNUM_BIND_PPTDEV = 40, 300 IOCNUM_UNBIND_PPTDEV = 41, 301 IOCNUM_MAP_PPTDEV_MMIO = 42, 302 IOCNUM_PPTDEV_MSI = 43, 303 IOCNUM_PPTDEV_MSIX = 44, 304 305 /* statistics */ 306 IOCNUM_VM_STATS = 50, 307 IOCNUM_VM_STAT_DESC = 51, 308 309 /* kernel device state */ 310 IOCNUM_SET_X2APIC_STATE = 60, 311 IOCNUM_GET_X2APIC_STATE = 61, 312 IOCNUM_GET_HPET_CAPABILITIES = 62, 313 314 /* CPU Topology */ 315 IOCNUM_SET_TOPOLOGY = 63, 316 IOCNUM_GET_TOPOLOGY = 64, 317 318 /* legacy interrupt injection */ 319 IOCNUM_ISA_ASSERT_IRQ = 80, 320 IOCNUM_ISA_DEASSERT_IRQ = 81, 321 IOCNUM_ISA_PULSE_IRQ = 82, 322 IOCNUM_ISA_SET_IRQ_TRIGGER = 83, 323 324 /* vm_cpuset */ 325 IOCNUM_ACTIVATE_CPU = 90, 326 IOCNUM_GET_CPUSET = 91, 327 IOCNUM_SUSPEND_CPU = 92, 328 IOCNUM_RESUME_CPU = 93, 329 330 /* RTC */ 331 IOCNUM_RTC_READ = 100, 332 IOCNUM_RTC_WRITE = 101, 333 IOCNUM_RTC_SETTIME = 102, 334 IOCNUM_RTC_GETTIME = 103, 335 336 /* checkpoint */ 337 IOCNUM_SNAPSHOT_REQ = 113, 338 339 IOCNUM_RESTORE_TIME = 115 340 }; 341 342 #define VM_RUN \ 343 _IOWR('v', IOCNUM_RUN, struct vm_run) 344 #define VM_SUSPEND \ 345 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend) 346 #define VM_REINIT \ 347 _IO('v', IOCNUM_REINIT) 348 #define VM_ALLOC_MEMSEG_FBSD12 \ 349 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg_fbsd12) 350 #define VM_ALLOC_MEMSEG \ 351 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg) 352 #define VM_GET_MEMSEG_FBSD12 \ 353 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg_fbsd12) 354 #define VM_GET_MEMSEG \ 355 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg) 356 #define VM_MMAP_MEMSEG \ 357 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap) 358 #define VM_MMAP_GETNEXT \ 359 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap) 360 #define VM_SET_REGISTER \ 361 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register) 362 #define VM_GET_REGISTER \ 363 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register) 364 #define VM_SET_SEGMENT_DESCRIPTOR \ 365 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 366 #define VM_GET_SEGMENT_DESCRIPTOR \ 367 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc) 368 #define VM_SET_REGISTER_SET \ 369 _IOW('v', IOCNUM_SET_REGISTER_SET, struct vm_register_set) 370 #define VM_GET_REGISTER_SET \ 371 _IOWR('v', IOCNUM_GET_REGISTER_SET, struct vm_register_set) 372 #define VM_SET_KERNEMU_DEV \ 373 _IOW('v', IOCNUM_SET_KERNEMU_DEV, \ 374 struct vm_readwrite_kernemu_device) 375 #define VM_GET_KERNEMU_DEV \ 376 _IOWR('v', IOCNUM_GET_KERNEMU_DEV, \ 377 struct vm_readwrite_kernemu_device) 378 #define VM_INJECT_EXCEPTION \ 379 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception) 380 #define VM_LAPIC_IRQ \ 381 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq) 382 #define VM_LAPIC_LOCAL_IRQ \ 383 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq) 384 #define VM_LAPIC_MSI \ 385 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi) 386 #define VM_IOAPIC_ASSERT_IRQ \ 387 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq) 388 #define VM_IOAPIC_DEASSERT_IRQ \ 389 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq) 390 #define VM_IOAPIC_PULSE_IRQ \ 391 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq) 392 #define VM_IOAPIC_PINCOUNT \ 393 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int) 394 #define VM_ISA_ASSERT_IRQ \ 395 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq) 396 #define VM_ISA_DEASSERT_IRQ \ 397 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq) 398 #define VM_ISA_PULSE_IRQ \ 399 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq) 400 #define VM_ISA_SET_IRQ_TRIGGER \ 401 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger) 402 #define VM_SET_CAPABILITY \ 403 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability) 404 #define VM_GET_CAPABILITY \ 405 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability) 406 #define VM_BIND_PPTDEV \ 407 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev) 408 #define VM_UNBIND_PPTDEV \ 409 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev) 410 #define VM_MAP_PPTDEV_MMIO \ 411 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio) 412 #define VM_PPTDEV_MSI \ 413 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi) 414 #define VM_PPTDEV_MSIX \ 415 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix) 416 #define VM_INJECT_NMI \ 417 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi) 418 #define VM_STATS \ 419 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats) 420 #define VM_STAT_DESC \ 421 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc) 422 #define VM_SET_X2APIC_STATE \ 423 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic) 424 #define VM_GET_X2APIC_STATE \ 425 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic) 426 #define VM_GET_HPET_CAPABILITIES \ 427 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap) 428 #define VM_SET_TOPOLOGY \ 429 _IOW('v', IOCNUM_SET_TOPOLOGY, struct vm_cpu_topology) 430 #define VM_GET_TOPOLOGY \ 431 _IOR('v', IOCNUM_GET_TOPOLOGY, struct vm_cpu_topology) 432 #define VM_GET_GPA_PMAP \ 433 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte) 434 #define VM_GLA2GPA \ 435 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) 436 #define VM_GLA2GPA_NOFAULT \ 437 _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) 438 #define VM_ACTIVATE_CPU \ 439 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) 440 #define VM_GET_CPUS \ 441 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) 442 #define VM_SUSPEND_CPU \ 443 _IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) 444 #define VM_RESUME_CPU \ 445 _IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) 446 #define VM_SET_INTINFO \ 447 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) 448 #define VM_GET_INTINFO \ 449 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) 450 #define VM_RTC_WRITE \ 451 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) 452 #define VM_RTC_READ \ 453 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) 454 #define VM_RTC_SETTIME \ 455 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) 456 #define VM_RTC_GETTIME \ 457 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) 458 #define VM_RESTART_INSTRUCTION \ 459 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) 460 #define VM_SNAPSHOT_REQ \ 461 _IOWR('v', IOCNUM_SNAPSHOT_REQ, struct vm_snapshot_meta) 462 #define VM_RESTORE_TIME \ 463 _IOWR('v', IOCNUM_RESTORE_TIME, int) 464 #endif 465