xref: /freebsd/sys/amd64/include/pcpu.h (revision b0d29bc47dba79f6f38e67eabadfb4b32ffd9390)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) Peter Wemm <peter@netplex.com.au>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #ifndef _MACHINE_PCPU_H_
32 #define	_MACHINE_PCPU_H_
33 
34 #ifndef _SYS_CDEFS_H_
35 #error "sys/cdefs.h is a prerequisite for this file"
36 #endif
37 
38 #include <machine/segments.h>
39 #include <machine/tss.h>
40 
41 #define	PC_PTI_STACK_SZ	16
42 
43 struct monitorbuf {
44 	int idle_state;		/* Used by cpu_idle_mwait. */
45 	int stop_state;		/* Used by cpustop_handler. */
46 	char padding[128 - (2 * sizeof(int))];
47 };
48 _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
49 
50 /*
51  * The SMP parts are setup in pmap.c and locore.s for the BSP, and
52  * mp_machdep.c sets up the data for the AP's to "see" when they awake.
53  * The reason for doing it via a struct is so that an array of pointers
54  * to each CPU's data can be set up for things like "check curproc on all
55  * other processors"
56  */
57 #define	PCPU_MD_FIELDS							\
58 	struct monitorbuf pc_monitorbuf __aligned(128);	/* cache line */\
59 	struct	pcpu *pc_prvspace;	/* Self-reference */		\
60 	struct	pmap *pc_curpmap;					\
61 	struct	amd64tss *pc_tssp;	/* TSS segment active on CPU */	\
62 	void	*pc_pad0;						\
63 	uint64_t pc_kcr3;						\
64 	uint64_t pc_ucr3;						\
65 	uint64_t pc_saved_ucr3;						\
66 	register_t pc_rsp0;						\
67 	register_t pc_scratch_rsp;	/* User %rsp in syscall */	\
68 	register_t pc_scratch_rax;					\
69 	u_int	pc_apic_id;						\
70 	u_int   pc_acpi_id;		/* ACPI CPU id */		\
71 	/* Pointer to the CPU %fs descriptor */				\
72 	struct user_segment_descriptor	*pc_fs32p;			\
73 	/* Pointer to the CPU %gs descriptor */				\
74 	struct user_segment_descriptor	*pc_gs32p;			\
75 	/* Pointer to the CPU LDT descriptor */				\
76 	struct system_segment_descriptor *pc_ldt;			\
77 	/* Pointer to the CPU TSS descriptor */				\
78 	struct system_segment_descriptor *pc_tss;			\
79 	uint64_t	pc_pm_save_cnt;					\
80 	u_int	pc_cmci_mask;		/* MCx banks for CMCI */	\
81 	uint64_t pc_dbreg[16];		/* ddb debugging regs */	\
82 	uint64_t pc_pti_stack[PC_PTI_STACK_SZ];				\
83 	register_t pc_pti_rsp0;						\
84 	int pc_dbreg_cmd;		/* ddb debugging reg cmd */	\
85 	u_int	pc_vcpu_id;		/* Xen vCPU ID */		\
86 	uint32_t pc_pcid_next;						\
87 	uint32_t pc_pcid_gen;						\
88 	uint32_t pc_smp_tlb_done;	/* TLB op acknowledgement */	\
89 	uint32_t pc_ibpb_set;						\
90 	void	*pc_mds_buf;						\
91 	void	*pc_mds_buf64;						\
92 	uint32_t pc_pad[2];						\
93 	uint8_t	pc_mds_tmp[64];						\
94 	u_int 	pc_ipi_bitmap;						\
95 	struct amd64tss pc_common_tss;					\
96 	struct user_segment_descriptor pc_gdt[NGDT];			\
97 	char	__pad[2956]		/* pad to UMA_PCPU_ALLOC_SIZE */
98 
99 #define	PC_DBREG_CMD_NONE	0
100 #define	PC_DBREG_CMD_LOAD	1
101 
102 #ifdef _KERNEL
103 
104 #define MONITOR_STOPSTATE_RUNNING	0
105 #define MONITOR_STOPSTATE_STOPPED	1
106 
107 #if defined(__GNUCLIKE_ASM) && defined(__GNUCLIKE___TYPEOF)
108 
109 /*
110  * Evaluates to the byte offset of the per-cpu variable name.
111  */
112 #define	__pcpu_offset(name)						\
113 	__offsetof(struct pcpu, name)
114 
115 /*
116  * Evaluates to the type of the per-cpu variable name.
117  */
118 #define	__pcpu_type(name)						\
119 	__typeof(((struct pcpu *)0)->name)
120 
121 /*
122  * Evaluates to the address of the per-cpu variable name.
123  */
124 #define	__PCPU_PTR(name) __extension__ ({				\
125 	__pcpu_type(name) *__p;						\
126 									\
127 	__asm __volatile("movq %%gs:%1,%0; addq %2,%0"			\
128 	    : "=r" (__p)						\
129 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))),	\
130 	      "i" (__pcpu_offset(name)));				\
131 									\
132 	__p;								\
133 })
134 
135 /*
136  * Evaluates to the value of the per-cpu variable name.
137  */
138 #define	__PCPU_GET(name) __extension__ ({				\
139 	__pcpu_type(name) __res;					\
140 	struct __s {							\
141 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
142 	} __s;								\
143 									\
144 	if (sizeof(__res) == 1 || sizeof(__res) == 2 ||			\
145 	    sizeof(__res) == 4 || sizeof(__res) == 8) {			\
146 		__asm __volatile("mov %%gs:%1,%0"			\
147 		    : "=r" (__s)					\
148 		    : "m" (*(struct __s *)(__pcpu_offset(name))));	\
149 		*(struct __s *)(void *)&__res = __s;			\
150 	} else {							\
151 		__res = *__PCPU_PTR(name);				\
152 	}								\
153 	__res;								\
154 })
155 
156 /*
157  * Adds the value to the per-cpu counter name.  The implementation
158  * must be atomic with respect to interrupts.
159  */
160 #define	__PCPU_ADD(name, val) do {					\
161 	__pcpu_type(name) __val;					\
162 	struct __s {							\
163 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
164 	} __s;								\
165 									\
166 	__val = (val);							\
167 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
168 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
169 		__s = *(struct __s *)(void *)&__val;			\
170 		__asm __volatile("add %1,%%gs:%0"			\
171 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
172 		    : "r" (__s));					\
173 	} else								\
174 		*__PCPU_PTR(name) += __val;				\
175 } while (0)
176 
177 /*
178  * Increments the value of the per-cpu counter name.  The implementation
179  * must be atomic with respect to interrupts.
180  */
181 #define	__PCPU_INC(name) do {						\
182 	CTASSERT(sizeof(__pcpu_type(name)) == 1 ||			\
183 	    sizeof(__pcpu_type(name)) == 2 ||				\
184 	    sizeof(__pcpu_type(name)) == 4 ||				\
185 	    sizeof(__pcpu_type(name)) == 8);				\
186 	if (sizeof(__pcpu_type(name)) == 1) {				\
187 		__asm __volatile("incb %%gs:%0"				\
188 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
189 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
190 	} else if (sizeof(__pcpu_type(name)) == 2) {			\
191 		__asm __volatile("incw %%gs:%0"				\
192 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
193 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
194 	} else if (sizeof(__pcpu_type(name)) == 4) {			\
195 		__asm __volatile("incl %%gs:%0"				\
196 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
197 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
198 	} else if (sizeof(__pcpu_type(name)) == 8) {			\
199 		__asm __volatile("incq %%gs:%0"				\
200 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
201 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
202 	}								\
203 } while (0)
204 
205 /*
206  * Sets the value of the per-cpu variable name to value val.
207  */
208 #define	__PCPU_SET(name, val) {						\
209 	__pcpu_type(name) __val;					\
210 	struct __s {							\
211 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
212 	} __s;								\
213 									\
214 	__val = (val);							\
215 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
216 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
217 		__s = *(struct __s *)(void *)&__val;			\
218 		__asm __volatile("mov %1,%%gs:%0"			\
219 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
220 		    : "r" (__s));					\
221 	} else {							\
222 		*__PCPU_PTR(name) = __val;				\
223 	}								\
224 }
225 
226 #define	get_pcpu() __extension__ ({					\
227 	struct pcpu *__pc;						\
228 									\
229 	__asm __volatile("movq %%gs:%1,%0"				\
230 	    : "=r" (__pc)						\
231 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))));	\
232 	__pc;								\
233 })
234 
235 #define	PCPU_GET(member)	__PCPU_GET(pc_ ## member)
236 #define	PCPU_ADD(member, val)	__PCPU_ADD(pc_ ## member, val)
237 #define	PCPU_INC(member)	__PCPU_INC(pc_ ## member)
238 #define	PCPU_PTR(member)	__PCPU_PTR(pc_ ## member)
239 #define	PCPU_SET(member, val)	__PCPU_SET(pc_ ## member, val)
240 
241 #define	IS_BSP()	(PCPU_GET(cpuid) == 0)
242 
243 #define zpcpu_offset_cpu(cpu)	((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu)
244 #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0])
245 #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0])
246 
247 #define zpcpu_sub_protected(base, n) do {				\
248 	ZPCPU_ASSERT_PROTECTED();					\
249 	zpcpu_sub(base, n);						\
250 } while (0)
251 
252 #define zpcpu_set_protected(base, n) do {				\
253 	__typeof(*base) __n = (n);					\
254 	ZPCPU_ASSERT_PROTECTED();					\
255 	switch (sizeof(*base)) {					\
256 	case 4:								\
257 		__asm __volatile("movl\t%1,%%gs:(%0)"			\
258 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
259 		break;							\
260 	case 8:								\
261 		__asm __volatile("movq\t%1,%%gs:(%0)"			\
262 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
263 		break;							\
264 	default:							\
265 		*zpcpu_get(base) = __n;					\
266 	}								\
267 } while (0);
268 
269 #define zpcpu_add(base, n) do {						\
270 	__typeof(*base) __n = (n);					\
271 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
272 	switch (sizeof(*base)) {					\
273 	case 4:								\
274 		__asm __volatile("addl\t%1,%%gs:(%0)"			\
275 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
276 		break;							\
277 	case 8:								\
278 		__asm __volatile("addq\t%1,%%gs:(%0)"			\
279 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
280 		break;							\
281 	}								\
282 } while (0)
283 
284 #define zpcpu_add_protected(base, n) do {				\
285 	ZPCPU_ASSERT_PROTECTED();					\
286 	zpcpu_add(base, n);						\
287 } while (0)
288 
289 #define zpcpu_sub(base, n) do {						\
290 	__typeof(*base) __n = (n);					\
291 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
292 	switch (sizeof(*base)) {					\
293 	case 4:								\
294 		__asm __volatile("subl\t%1,%%gs:(%0)"			\
295 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
296 		break;							\
297 	case 8:								\
298 		__asm __volatile("subq\t%1,%%gs:(%0)"			\
299 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
300 		break;							\
301 	}								\
302 } while (0);
303 
304 #else /* !__GNUCLIKE_ASM || !__GNUCLIKE___TYPEOF */
305 
306 #error "this file needs to be ported to your compiler"
307 
308 #endif /* __GNUCLIKE_ASM && __GNUCLIKE___TYPEOF */
309 
310 #endif /* _KERNEL */
311 
312 #endif /* !_MACHINE_PCPU_H_ */
313