1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/domainset.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/mutex.h> 43 #include <sys/proc.h> 44 #include <sys/sysctl.h> 45 #include <sys/sysent.h> 46 #include <sys/tslog.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <sys/signalvar.h> 50 #include <vm/uma.h> 51 52 #include <machine/cputypes.h> 53 #include <machine/frame.h> 54 #include <machine/intr_machdep.h> 55 #include <machine/md_var.h> 56 #include <machine/pcb.h> 57 #include <machine/psl.h> 58 #include <machine/resource.h> 59 #include <machine/specialreg.h> 60 #include <machine/segments.h> 61 #include <machine/ucontext.h> 62 #include <x86/ifunc.h> 63 64 /* 65 * Floating point support. 66 */ 67 68 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 69 #define fnclex() __asm __volatile("fnclex") 70 #define fninit() __asm __volatile("fninit") 71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 73 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 76 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 77 78 static __inline void 79 xrstor32(char *addr, uint64_t mask) 80 { 81 uint32_t low, hi; 82 83 low = mask; 84 hi = mask >> 32; 85 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 86 } 87 88 static __inline void 89 xrstor64(char *addr, uint64_t mask) 90 { 91 uint32_t low, hi; 92 93 low = mask; 94 hi = mask >> 32; 95 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 96 } 97 98 static __inline void 99 xsave32(char *addr, uint64_t mask) 100 { 101 uint32_t low, hi; 102 103 low = mask; 104 hi = mask >> 32; 105 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 106 "memory"); 107 } 108 109 static __inline void 110 xsave64(char *addr, uint64_t mask) 111 { 112 uint32_t low, hi; 113 114 low = mask; 115 hi = mask >> 32; 116 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 117 "memory"); 118 } 119 120 static __inline void 121 xsaveopt32(char *addr, uint64_t mask) 122 { 123 uint32_t low, hi; 124 125 low = mask; 126 hi = mask >> 32; 127 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 128 "memory"); 129 } 130 131 static __inline void 132 xsaveopt64(char *addr, uint64_t mask) 133 { 134 uint32_t low, hi; 135 136 low = mask; 137 hi = mask >> 32; 138 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 139 "memory"); 140 } 141 142 CTASSERT(sizeof(struct savefpu) == 512); 143 CTASSERT(sizeof(struct xstate_hdr) == 64); 144 CTASSERT(sizeof(struct savefpu_ymm) == 832); 145 146 /* 147 * This requirement is to make it easier for asm code to calculate 148 * offset of the fpu save area from the pcb address. FPU save area 149 * must be 64-byte aligned. 150 */ 151 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 152 153 /* 154 * Ensure the copy of XCR0 saved in a core is contained in the padding 155 * area. 156 */ 157 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 158 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 159 160 static void fpu_clean_state(void); 161 162 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 163 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 164 165 int use_xsave; /* non-static for cpu_switch.S */ 166 uint64_t xsave_mask; /* the same */ 167 static uma_zone_t fpu_save_area_zone; 168 static struct savefpu *fpu_initialstate; 169 170 static struct xsave_area_elm_descr { 171 u_int offset; 172 u_int size; 173 } *xsave_area_desc; 174 175 static void 176 fpusave_xsaveopt64(void *addr) 177 { 178 xsaveopt64((char *)addr, xsave_mask); 179 } 180 181 static void 182 fpusave_xsaveopt3264(void *addr) 183 { 184 if (SV_CURPROC_FLAG(SV_ILP32)) 185 xsaveopt32((char *)addr, xsave_mask); 186 else 187 xsaveopt64((char *)addr, xsave_mask); 188 } 189 190 static void 191 fpusave_xsave64(void *addr) 192 { 193 xsave64((char *)addr, xsave_mask); 194 } 195 196 static void 197 fpusave_xsave3264(void *addr) 198 { 199 if (SV_CURPROC_FLAG(SV_ILP32)) 200 xsave32((char *)addr, xsave_mask); 201 else 202 xsave64((char *)addr, xsave_mask); 203 } 204 205 static void 206 fpurestore_xrstor64(void *addr) 207 { 208 xrstor64((char *)addr, xsave_mask); 209 } 210 211 static void 212 fpurestore_xrstor3264(void *addr) 213 { 214 if (SV_CURPROC_FLAG(SV_ILP32)) 215 xrstor32((char *)addr, xsave_mask); 216 else 217 xrstor64((char *)addr, xsave_mask); 218 } 219 220 static void 221 fpusave_fxsave(void *addr) 222 { 223 224 fxsave((char *)addr); 225 } 226 227 static void 228 fpurestore_fxrstor(void *addr) 229 { 230 231 fxrstor((char *)addr); 232 } 233 234 DEFINE_IFUNC(, void, fpusave, (void *)) 235 { 236 u_int cp[4]; 237 238 if (!use_xsave) 239 return (fpusave_fxsave); 240 cpuid_count(0xd, 0x1, cp); 241 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 242 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 243 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 244 } 245 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 246 fpusave_xsave64 : fpusave_xsave3264); 247 } 248 249 DEFINE_IFUNC(, void, fpurestore, (void *)) 250 { 251 if (!use_xsave) 252 return (fpurestore_fxrstor); 253 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 254 fpurestore_xrstor64 : fpurestore_xrstor3264); 255 } 256 257 void 258 fpususpend(void *addr) 259 { 260 u_long cr0; 261 262 cr0 = rcr0(); 263 fpu_enable(); 264 fpusave(addr); 265 load_cr0(cr0); 266 } 267 268 void 269 fpuresume(void *addr) 270 { 271 u_long cr0; 272 273 cr0 = rcr0(); 274 fpu_enable(); 275 fninit(); 276 if (use_xsave) 277 load_xcr(XCR0, xsave_mask); 278 fpurestore(addr); 279 load_cr0(cr0); 280 } 281 282 /* 283 * Enable XSAVE if supported and allowed by user. 284 * Calculate the xsave_mask. 285 */ 286 static void 287 fpuinit_bsp1(void) 288 { 289 u_int cp[4]; 290 uint64_t xsave_mask_user; 291 bool old_wp; 292 293 if (!use_xsave) 294 return; 295 cpuid_count(0xd, 0x0, cp); 296 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 297 if ((cp[0] & xsave_mask) != xsave_mask) 298 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 299 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 300 xsave_mask_user = xsave_mask; 301 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 302 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 303 xsave_mask &= xsave_mask_user; 304 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 305 xsave_mask &= ~XFEATURE_AVX512; 306 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 307 xsave_mask &= ~XFEATURE_MPX; 308 309 cpuid_count(0xd, 0x1, cp); 310 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 311 /* 312 * Patch the XSAVE instruction in the cpu_switch code 313 * to XSAVEOPT. We assume that XSAVE encoding used 314 * REX byte, and set the bit 4 of the r/m byte. 315 * 316 * It seems that some BIOSes give control to the OS 317 * with CR0.WP already set, making the kernel text 318 * read-only before cpu_startup(). 319 */ 320 old_wp = disable_wp(); 321 ctx_switch_xsave32[3] |= 0x10; 322 ctx_switch_xsave[3] |= 0x10; 323 restore_wp(old_wp); 324 } 325 } 326 327 /* 328 * Calculate the fpu save area size. 329 */ 330 static void 331 fpuinit_bsp2(void) 332 { 333 u_int cp[4]; 334 335 if (use_xsave) { 336 cpuid_count(0xd, 0x0, cp); 337 cpu_max_ext_state_size = cp[1]; 338 339 /* 340 * Reload the cpu_feature2, since we enabled OSXSAVE. 341 */ 342 do_cpuid(1, cp); 343 cpu_feature2 = cp[2]; 344 } else 345 cpu_max_ext_state_size = sizeof(struct savefpu); 346 } 347 348 /* 349 * Initialize the floating point unit. 350 */ 351 void 352 fpuinit(void) 353 { 354 register_t saveintr; 355 uint64_t cr4; 356 u_int mxcsr; 357 u_short control; 358 359 TSENTER(); 360 if (IS_BSP()) 361 fpuinit_bsp1(); 362 363 if (use_xsave) { 364 cr4 = rcr4(); 365 366 /* 367 * Revert enablement of PKRU if user disabled its 368 * saving on context switches by clearing the bit in 369 * the xsave mask. Also redundantly clear the bit in 370 * cpu_stdext_feature2 to prevent pmap from ever 371 * trying to set the page table bits. 372 */ 373 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0 && 374 (xsave_mask & XFEATURE_ENABLED_PKRU) == 0) { 375 cr4 &= ~CR4_PKE; 376 cpu_stdext_feature2 &= ~CPUID_STDEXT2_PKU; 377 } 378 379 load_cr4(cr4 | CR4_XSAVE); 380 load_xcr(XCR0, xsave_mask); 381 } 382 383 /* 384 * XCR0 shall be set up before CPU can report the save area size. 385 */ 386 if (IS_BSP()) 387 fpuinit_bsp2(); 388 389 /* 390 * It is too early for critical_enter() to work on AP. 391 */ 392 saveintr = intr_disable(); 393 fpu_enable(); 394 fninit(); 395 control = __INITIAL_FPUCW__; 396 fldcw(control); 397 mxcsr = __INITIAL_MXCSR__; 398 ldmxcsr(mxcsr); 399 fpu_disable(); 400 intr_restore(saveintr); 401 TSEXIT(); 402 } 403 404 /* 405 * On the boot CPU we generate a clean state that is used to 406 * initialize the floating point unit when it is first used by a 407 * process. 408 */ 409 static void 410 fpuinitstate(void *arg __unused) 411 { 412 uint64_t *xstate_bv; 413 register_t saveintr; 414 int cp[4], i, max_ext_n; 415 416 /* Do potentially blocking operations before disabling interrupts. */ 417 fpu_save_area_zone = uma_zcreate("FPU_save_area", 418 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 419 XSAVE_AREA_ALIGN - 1, 0); 420 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 421 if (use_xsave) { 422 max_ext_n = flsl(xsave_mask); 423 xsave_area_desc = malloc(max_ext_n * sizeof(struct 424 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 425 } 426 427 cpu_thread_alloc(&thread0); 428 429 saveintr = intr_disable(); 430 fpu_enable(); 431 432 fpusave_fxsave(fpu_initialstate); 433 if (fpu_initialstate->sv_env.en_mxcsr_mask) 434 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 435 else 436 cpu_mxcsr_mask = 0xFFBF; 437 438 /* 439 * The fninit instruction does not modify XMM registers or x87 440 * registers (MM/ST). The fpusave call dumped the garbage 441 * contained in the registers after reset to the initial state 442 * saved. Clear XMM and x87 registers file image to make the 443 * startup program state and signal handler XMM/x87 register 444 * content predictable. 445 */ 446 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 447 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 448 449 /* 450 * Create a table describing the layout of the CPU Extended 451 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 452 * Region of an XSAVE Area" for the source of offsets/sizes. 453 */ 454 if (use_xsave) { 455 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 456 offsetof(struct xstate_hdr, xstate_bv)); 457 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 458 459 /* x87 state */ 460 xsave_area_desc[0].offset = 0; 461 xsave_area_desc[0].size = 160; 462 /* XMM */ 463 xsave_area_desc[1].offset = 160; 464 xsave_area_desc[1].size = 416 - 160; 465 466 for (i = 2; i < max_ext_n; i++) { 467 cpuid_count(0xd, i, cp); 468 xsave_area_desc[i].offset = cp[1]; 469 xsave_area_desc[i].size = cp[0]; 470 } 471 } 472 473 fpu_disable(); 474 intr_restore(saveintr); 475 } 476 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 477 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 478 479 /* 480 * Free coprocessor (if we have it). 481 */ 482 void 483 fpuexit(struct thread *td) 484 { 485 486 critical_enter(); 487 if (curthread == PCPU_GET(fpcurthread)) { 488 fpu_enable(); 489 fpusave(curpcb->pcb_save); 490 fpu_disable(); 491 PCPU_SET(fpcurthread, NULL); 492 } 493 critical_exit(); 494 } 495 496 int 497 fpuformat(void) 498 { 499 500 return (_MC_FPFMT_XMM); 501 } 502 503 /* 504 * The following mechanism is used to ensure that the FPE_... value 505 * that is passed as a trapcode to the signal handler of the user 506 * process does not have more than one bit set. 507 * 508 * Multiple bits may be set if the user process modifies the control 509 * word while a status word bit is already set. While this is a sign 510 * of bad coding, we have no choice than to narrow them down to one 511 * bit, since we must not send a trapcode that is not exactly one of 512 * the FPE_ macros. 513 * 514 * The mechanism has a static table with 127 entries. Each combination 515 * of the 7 FPU status word exception bits directly translates to a 516 * position in this table, where a single FPE_... value is stored. 517 * This FPE_... value stored there is considered the "most important" 518 * of the exception bits and will be sent as the signal code. The 519 * precedence of the bits is based upon Intel Document "Numerical 520 * Applications", Chapter "Special Computational Situations". 521 * 522 * The macro to choose one of these values does these steps: 1) Throw 523 * away status word bits that cannot be masked. 2) Throw away the bits 524 * currently masked in the control word, assuming the user isn't 525 * interested in them anymore. 3) Reinsert status word bit 7 (stack 526 * fault) if it is set, which cannot be masked but must be presered. 527 * 4) Use the remaining bits to point into the trapcode table. 528 * 529 * The 6 maskable bits in order of their preference, as stated in the 530 * above referenced Intel manual: 531 * 1 Invalid operation (FP_X_INV) 532 * 1a Stack underflow 533 * 1b Stack overflow 534 * 1c Operand of unsupported format 535 * 1d SNaN operand. 536 * 2 QNaN operand (not an exception, irrelavant here) 537 * 3 Any other invalid-operation not mentioned above or zero divide 538 * (FP_X_INV, FP_X_DZ) 539 * 4 Denormal operand (FP_X_DNML) 540 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 541 * 6 Inexact result (FP_X_IMP) 542 */ 543 static char fpetable[128] = { 544 0, 545 FPE_FLTINV, /* 1 - INV */ 546 FPE_FLTUND, /* 2 - DNML */ 547 FPE_FLTINV, /* 3 - INV | DNML */ 548 FPE_FLTDIV, /* 4 - DZ */ 549 FPE_FLTINV, /* 5 - INV | DZ */ 550 FPE_FLTDIV, /* 6 - DNML | DZ */ 551 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 552 FPE_FLTOVF, /* 8 - OFL */ 553 FPE_FLTINV, /* 9 - INV | OFL */ 554 FPE_FLTUND, /* A - DNML | OFL */ 555 FPE_FLTINV, /* B - INV | DNML | OFL */ 556 FPE_FLTDIV, /* C - DZ | OFL */ 557 FPE_FLTINV, /* D - INV | DZ | OFL */ 558 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 559 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 560 FPE_FLTUND, /* 10 - UFL */ 561 FPE_FLTINV, /* 11 - INV | UFL */ 562 FPE_FLTUND, /* 12 - DNML | UFL */ 563 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 564 FPE_FLTDIV, /* 14 - DZ | UFL */ 565 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 566 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 567 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 568 FPE_FLTOVF, /* 18 - OFL | UFL */ 569 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 570 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 571 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 572 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 573 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 574 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 575 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 576 FPE_FLTRES, /* 20 - IMP */ 577 FPE_FLTINV, /* 21 - INV | IMP */ 578 FPE_FLTUND, /* 22 - DNML | IMP */ 579 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 580 FPE_FLTDIV, /* 24 - DZ | IMP */ 581 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 582 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 583 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 584 FPE_FLTOVF, /* 28 - OFL | IMP */ 585 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 586 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 587 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 588 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 589 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 590 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 591 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 592 FPE_FLTUND, /* 30 - UFL | IMP */ 593 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 594 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 595 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 596 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 597 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 598 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 599 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 600 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 601 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 602 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 603 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 604 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 605 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 606 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 607 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 608 FPE_FLTSUB, /* 40 - STK */ 609 FPE_FLTSUB, /* 41 - INV | STK */ 610 FPE_FLTUND, /* 42 - DNML | STK */ 611 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 612 FPE_FLTDIV, /* 44 - DZ | STK */ 613 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 614 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 615 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 616 FPE_FLTOVF, /* 48 - OFL | STK */ 617 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 618 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 619 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 620 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 621 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 622 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 623 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 624 FPE_FLTUND, /* 50 - UFL | STK */ 625 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 626 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 627 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 628 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 629 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 630 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 631 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 632 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 633 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 634 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 635 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 636 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 637 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 638 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 639 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 640 FPE_FLTRES, /* 60 - IMP | STK */ 641 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 642 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 643 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 644 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 645 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 646 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 647 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 648 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 649 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 650 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 651 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 652 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 653 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 654 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 655 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 656 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 657 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 658 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 659 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 660 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 661 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 662 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 663 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 664 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 665 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 666 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 667 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 668 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 669 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 670 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 671 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 672 }; 673 674 /* 675 * Read the FP status and control words, then generate si_code value 676 * for SIGFPE. The error code chosen will be one of the 677 * FPE_... macros. It will be sent as the second argument to old 678 * BSD-style signal handlers and as "siginfo_t->si_code" (second 679 * argument) to SA_SIGINFO signal handlers. 680 * 681 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 682 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 683 * usermode code which understands the FPU hardware enough to enable 684 * the exceptions, can also handle clearing the exception state in the 685 * handler. The only consequence of not clearing the exception is the 686 * rethrow of the SIGFPE on return from the signal handler and 687 * reexecution of the corresponding instruction. 688 * 689 * For XMM traps, the exceptions were never cleared. 690 */ 691 int 692 fputrap_x87(void) 693 { 694 struct savefpu *pcb_save; 695 u_short control, status; 696 697 critical_enter(); 698 699 /* 700 * Interrupt handling (for another interrupt) may have pushed the 701 * state to memory. Fetch the relevant parts of the state from 702 * wherever they are. 703 */ 704 if (PCPU_GET(fpcurthread) != curthread) { 705 pcb_save = curpcb->pcb_save; 706 control = pcb_save->sv_env.en_cw; 707 status = pcb_save->sv_env.en_sw; 708 } else { 709 fnstcw(&control); 710 fnstsw(&status); 711 } 712 713 critical_exit(); 714 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 715 } 716 717 int 718 fputrap_sse(void) 719 { 720 u_int mxcsr; 721 722 critical_enter(); 723 if (PCPU_GET(fpcurthread) != curthread) 724 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 725 else 726 stmxcsr(&mxcsr); 727 critical_exit(); 728 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 729 } 730 731 static void 732 restore_fpu_curthread(struct thread *td) 733 { 734 struct pcb *pcb; 735 736 /* 737 * Record new context early in case frstor causes a trap. 738 */ 739 PCPU_SET(fpcurthread, td); 740 741 fpu_enable(); 742 fpu_clean_state(); 743 pcb = td->td_pcb; 744 745 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 746 /* 747 * This is the first time this thread has used the FPU or 748 * the PCB doesn't contain a clean FPU state. Explicitly 749 * load an initial state. 750 * 751 * We prefer to restore the state from the actual save 752 * area in PCB instead of directly loading from 753 * fpu_initialstate, to ignite the XSAVEOPT 754 * tracking engine. 755 */ 756 bcopy(fpu_initialstate, pcb->pcb_save, 757 cpu_max_ext_state_size); 758 fpurestore(pcb->pcb_save); 759 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 760 fldcw(pcb->pcb_initial_fpucw); 761 if (PCB_USER_FPU(pcb)) 762 set_pcb_flags(pcb, PCB_FPUINITDONE | 763 PCB_USERFPUINITDONE); 764 else 765 set_pcb_flags(pcb, PCB_FPUINITDONE); 766 } else 767 fpurestore(pcb->pcb_save); 768 } 769 770 /* 771 * Device Not Available (DNA, #NM) exception handler. 772 * 773 * It would be better to switch FP context here (if curthread != 774 * fpcurthread) and not necessarily for every context switch, but it 775 * is too hard to access foreign pcb's. 776 */ 777 void 778 fpudna(void) 779 { 780 struct thread *td; 781 782 td = curthread; 783 /* 784 * This handler is entered with interrupts enabled, so context 785 * switches may occur before critical_enter() is executed. If 786 * a context switch occurs, then when we regain control, our 787 * state will have been completely restored. The CPU may 788 * change underneath us, but the only part of our context that 789 * lives in the CPU is CR0.TS and that will be "restored" by 790 * setting it on the new CPU. 791 */ 792 critical_enter(); 793 794 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 795 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 796 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 797 /* 798 * Some virtual machines seems to set %cr0.TS at 799 * arbitrary moments. Silently clear the TS bit 800 * regardless of the eager/lazy FPU context switch 801 * mode. 802 */ 803 fpu_enable(); 804 } else { 805 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 806 panic( 807 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 808 PCPU_GET(fpcurthread), 809 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 810 } 811 restore_fpu_curthread(td); 812 } 813 critical_exit(); 814 } 815 816 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 817 void 818 fpu_activate_sw(struct thread *td) 819 { 820 821 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 822 PCPU_SET(fpcurthread, NULL); 823 fpu_disable(); 824 } else if (PCPU_GET(fpcurthread) != td) { 825 restore_fpu_curthread(td); 826 } 827 } 828 829 void 830 fpudrop(void) 831 { 832 struct thread *td; 833 834 td = PCPU_GET(fpcurthread); 835 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 836 CRITICAL_ASSERT(td); 837 PCPU_SET(fpcurthread, NULL); 838 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 839 fpu_disable(); 840 } 841 842 /* 843 * Get the user state of the FPU into pcb->pcb_user_save without 844 * dropping ownership (if possible). It returns the FPU ownership 845 * status. 846 */ 847 int 848 fpugetregs(struct thread *td) 849 { 850 struct pcb *pcb; 851 uint64_t *xstate_bv, bit; 852 char *sa; 853 struct savefpu *s; 854 uint32_t mxcsr, mxcsr_mask; 855 int max_ext_n, i, owned; 856 bool do_mxcsr; 857 858 pcb = td->td_pcb; 859 critical_enter(); 860 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 861 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 862 cpu_max_ext_state_size); 863 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 864 pcb->pcb_initial_fpucw; 865 fpuuserinited(td); 866 critical_exit(); 867 return (_MC_FPOWNED_PCB); 868 } 869 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 870 fpusave(get_pcb_user_save_pcb(pcb)); 871 owned = _MC_FPOWNED_FPU; 872 } else { 873 owned = _MC_FPOWNED_PCB; 874 } 875 if (use_xsave) { 876 /* 877 * Handle partially saved state. 878 */ 879 sa = (char *)get_pcb_user_save_pcb(pcb); 880 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 881 offsetof(struct xstate_hdr, xstate_bv)); 882 max_ext_n = flsl(xsave_mask); 883 for (i = 0; i < max_ext_n; i++) { 884 bit = 1ULL << i; 885 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 886 continue; 887 do_mxcsr = false; 888 if (i == 0 && (*xstate_bv & (XFEATURE_ENABLED_SSE | 889 XFEATURE_ENABLED_AVX)) != 0) { 890 /* 891 * x87 area was not saved by XSAVEOPT, 892 * but one of XMM or AVX was. Then we need 893 * to preserve MXCSR from being overwritten 894 * with the default value. 895 */ 896 s = (struct savefpu *)sa; 897 mxcsr = s->sv_env.en_mxcsr; 898 mxcsr_mask = s->sv_env.en_mxcsr_mask; 899 do_mxcsr = true; 900 } 901 bcopy((char *)fpu_initialstate + 902 xsave_area_desc[i].offset, 903 sa + xsave_area_desc[i].offset, 904 xsave_area_desc[i].size); 905 if (do_mxcsr) { 906 s->sv_env.en_mxcsr = mxcsr; 907 s->sv_env.en_mxcsr_mask = mxcsr_mask; 908 } 909 *xstate_bv |= bit; 910 } 911 } 912 critical_exit(); 913 return (owned); 914 } 915 916 void 917 fpuuserinited(struct thread *td) 918 { 919 struct pcb *pcb; 920 921 CRITICAL_ASSERT(td); 922 pcb = td->td_pcb; 923 if (PCB_USER_FPU(pcb)) 924 set_pcb_flags(pcb, 925 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 926 else 927 set_pcb_flags(pcb, PCB_FPUINITDONE); 928 } 929 930 int 931 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 932 { 933 struct xstate_hdr *hdr, *ehdr; 934 size_t len, max_len; 935 uint64_t bv; 936 937 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 938 if (xfpustate == NULL) 939 return (0); 940 if (!use_xsave) 941 return (EOPNOTSUPP); 942 943 len = xfpustate_size; 944 if (len < sizeof(struct xstate_hdr)) 945 return (EINVAL); 946 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 947 if (len > max_len) 948 return (EINVAL); 949 950 ehdr = (struct xstate_hdr *)xfpustate; 951 bv = ehdr->xstate_bv; 952 953 /* 954 * Avoid #gp. 955 */ 956 if (bv & ~xsave_mask) 957 return (EINVAL); 958 959 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 960 961 hdr->xstate_bv = bv; 962 bcopy(xfpustate + sizeof(struct xstate_hdr), 963 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 964 965 return (0); 966 } 967 968 /* 969 * Set the state of the FPU. 970 */ 971 int 972 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 973 size_t xfpustate_size) 974 { 975 struct pcb *pcb; 976 int error; 977 978 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 979 pcb = td->td_pcb; 980 error = 0; 981 critical_enter(); 982 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 983 error = fpusetxstate(td, xfpustate, xfpustate_size); 984 if (error == 0) { 985 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 986 fpurestore(get_pcb_user_save_td(td)); 987 set_pcb_flags(pcb, PCB_FPUINITDONE | 988 PCB_USERFPUINITDONE); 989 } 990 } else { 991 error = fpusetxstate(td, xfpustate, xfpustate_size); 992 if (error == 0) { 993 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 994 fpuuserinited(td); 995 } 996 } 997 critical_exit(); 998 return (error); 999 } 1000 1001 /* 1002 * On AuthenticAMD processors, the fxrstor instruction does not restore 1003 * the x87's stored last instruction pointer, last data pointer, and last 1004 * opcode values, except in the rare case in which the exception summary 1005 * (ES) bit in the x87 status word is set to 1. 1006 * 1007 * In order to avoid leaking this information across processes, we clean 1008 * these values by performing a dummy load before executing fxrstor(). 1009 */ 1010 static void 1011 fpu_clean_state(void) 1012 { 1013 static float dummy_variable = 0.0; 1014 u_short status; 1015 1016 /* 1017 * Clear the ES bit in the x87 status word if it is currently 1018 * set, in order to avoid causing a fault in the upcoming load. 1019 */ 1020 fnstsw(&status); 1021 if (status & 0x80) 1022 fnclex(); 1023 1024 /* 1025 * Load the dummy variable into the x87 stack. This mangles 1026 * the x87 stack, but we don't care since we're about to call 1027 * fxrstor() anyway. 1028 */ 1029 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1030 } 1031 1032 /* 1033 * This really sucks. We want the acpi version only, but it requires 1034 * the isa_if.h file in order to get the definitions. 1035 */ 1036 #include "opt_isa.h" 1037 #ifdef DEV_ISA 1038 #include <isa/isavar.h> 1039 /* 1040 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1041 */ 1042 static struct isa_pnp_id fpupnp_ids[] = { 1043 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1044 { 0 } 1045 }; 1046 1047 static int 1048 fpupnp_probe(device_t dev) 1049 { 1050 int result; 1051 1052 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1053 if (result <= 0) 1054 device_quiet(dev); 1055 return (result); 1056 } 1057 1058 static int 1059 fpupnp_attach(device_t dev) 1060 { 1061 1062 return (0); 1063 } 1064 1065 static device_method_t fpupnp_methods[] = { 1066 /* Device interface */ 1067 DEVMETHOD(device_probe, fpupnp_probe), 1068 DEVMETHOD(device_attach, fpupnp_attach), 1069 DEVMETHOD(device_detach, bus_generic_detach), 1070 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1071 DEVMETHOD(device_suspend, bus_generic_suspend), 1072 DEVMETHOD(device_resume, bus_generic_resume), 1073 { 0, 0 } 1074 }; 1075 1076 static driver_t fpupnp_driver = { 1077 "fpupnp", 1078 fpupnp_methods, 1079 1, /* no softc */ 1080 }; 1081 1082 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, 0, 0); 1083 ISA_PNP_INFO(fpupnp_ids); 1084 #endif /* DEV_ISA */ 1085 1086 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1087 "Kernel contexts for FPU state"); 1088 1089 #define FPU_KERN_CTX_FPUINITDONE 0x01 1090 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1091 #define FPU_KERN_CTX_INUSE 0x04 1092 1093 struct fpu_kern_ctx { 1094 struct savefpu *prev; 1095 uint32_t flags; 1096 char hwstate1[]; 1097 }; 1098 1099 static inline size_t __pure2 1100 fpu_kern_alloc_sz(u_int max_est) 1101 { 1102 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1103 } 1104 1105 static inline int __pure2 1106 fpu_kern_malloc_flags(u_int fpflags) 1107 { 1108 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1109 } 1110 1111 struct fpu_kern_ctx * 1112 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1113 { 1114 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1115 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1116 fpu_kern_malloc_flags(flags))); 1117 } 1118 1119 struct fpu_kern_ctx * 1120 fpu_kern_alloc_ctx(u_int flags) 1121 { 1122 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1123 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1124 } 1125 1126 void 1127 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1128 { 1129 1130 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1131 /* XXXKIB clear the memory ? */ 1132 free(ctx, M_FPUKERN_CTX); 1133 } 1134 1135 static struct savefpu * 1136 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1137 { 1138 vm_offset_t p; 1139 1140 p = (vm_offset_t)&ctx->hwstate1; 1141 p = roundup2(p, XSAVE_AREA_ALIGN); 1142 return ((struct savefpu *)p); 1143 } 1144 1145 void 1146 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1147 { 1148 struct pcb *pcb; 1149 1150 pcb = td->td_pcb; 1151 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1152 ("ctx is required when !FPU_KERN_NOCTX")); 1153 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1154 ("using inuse ctx")); 1155 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1156 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1157 1158 if ((flags & FPU_KERN_NOCTX) != 0) { 1159 critical_enter(); 1160 fpu_enable(); 1161 if (curthread == PCPU_GET(fpcurthread)) { 1162 fpusave(curpcb->pcb_save); 1163 PCPU_SET(fpcurthread, NULL); 1164 } else { 1165 KASSERT(PCPU_GET(fpcurthread) == NULL, 1166 ("invalid fpcurthread")); 1167 } 1168 1169 /* 1170 * This breaks XSAVEOPT tracker, but 1171 * PCB_FPUNOSAVE state is supposed to never need to 1172 * save FPU context at all. 1173 */ 1174 fpurestore(fpu_initialstate); 1175 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1176 PCB_FPUINITDONE); 1177 return; 1178 } 1179 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1180 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1181 return; 1182 } 1183 critical_enter(); 1184 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1185 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1186 ctx->flags = FPU_KERN_CTX_INUSE; 1187 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1188 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1189 fpuexit(td); 1190 ctx->prev = pcb->pcb_save; 1191 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1192 set_pcb_flags(pcb, PCB_KERNFPU); 1193 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1194 critical_exit(); 1195 } 1196 1197 int 1198 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1199 { 1200 struct pcb *pcb; 1201 1202 pcb = td->td_pcb; 1203 1204 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1205 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1206 KASSERT(PCPU_GET(fpcurthread) == NULL, 1207 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1208 CRITICAL_ASSERT(td); 1209 1210 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1211 fpu_disable(); 1212 } else { 1213 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1214 ("leaving not inuse ctx")); 1215 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1216 1217 if (is_fpu_kern_thread(0) && 1218 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1219 return (0); 1220 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1221 ("dummy ctx")); 1222 critical_enter(); 1223 if (curthread == PCPU_GET(fpcurthread)) 1224 fpudrop(); 1225 pcb->pcb_save = ctx->prev; 1226 } 1227 1228 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1229 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1230 set_pcb_flags(pcb, PCB_FPUINITDONE); 1231 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1232 clear_pcb_flags(pcb, PCB_KERNFPU); 1233 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1234 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1235 } else { 1236 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1237 set_pcb_flags(pcb, PCB_FPUINITDONE); 1238 else 1239 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1240 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1241 } 1242 critical_exit(); 1243 return (0); 1244 } 1245 1246 int 1247 fpu_kern_thread(u_int flags) 1248 { 1249 1250 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1251 ("Only kthread may use fpu_kern_thread")); 1252 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1253 ("mangled pcb_save")); 1254 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1255 1256 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1257 return (0); 1258 } 1259 1260 int 1261 is_fpu_kern_thread(u_int flags) 1262 { 1263 1264 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1265 return (0); 1266 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1267 } 1268 1269 /* 1270 * FPU save area alloc/free/init utility routines 1271 */ 1272 struct savefpu * 1273 fpu_save_area_alloc(void) 1274 { 1275 1276 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1277 } 1278 1279 void 1280 fpu_save_area_free(struct savefpu *fsa) 1281 { 1282 1283 uma_zfree(fpu_save_area_zone, fsa); 1284 } 1285 1286 void 1287 fpu_save_area_reset(struct savefpu *fsa) 1288 { 1289 1290 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1291 } 1292