1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1990 William Jolitz. 5 * Copyright (c) 1991 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 33 */ 34 35 #include <sys/cdefs.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/domainset.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/mutex.h> 46 #include <sys/proc.h> 47 #include <sys/sysctl.h> 48 #include <sys/sysent.h> 49 #include <sys/tslog.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <sys/signalvar.h> 53 #include <vm/uma.h> 54 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/md_var.h> 59 #include <machine/pcb.h> 60 #include <machine/psl.h> 61 #include <machine/resource.h> 62 #include <machine/specialreg.h> 63 #include <machine/segments.h> 64 #include <machine/ucontext.h> 65 #include <x86/ifunc.h> 66 67 /* 68 * Floating point support. 69 */ 70 71 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 72 #define fnclex() __asm __volatile("fnclex") 73 #define fninit() __asm __volatile("fninit") 74 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 75 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 76 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 77 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 78 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 79 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr))) 80 81 static __inline void 82 xrstor32(char *addr, uint64_t mask) 83 { 84 uint32_t low, hi; 85 86 low = mask; 87 hi = mask >> 32; 88 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 89 } 90 91 static __inline void 92 xrstor64(char *addr, uint64_t mask) 93 { 94 uint32_t low, hi; 95 96 low = mask; 97 hi = mask >> 32; 98 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi)); 99 } 100 101 static __inline void 102 xsave32(char *addr, uint64_t mask) 103 { 104 uint32_t low, hi; 105 106 low = mask; 107 hi = mask >> 32; 108 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 109 "memory"); 110 } 111 112 static __inline void 113 xsave64(char *addr, uint64_t mask) 114 { 115 uint32_t low, hi; 116 117 low = mask; 118 hi = mask >> 32; 119 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 120 "memory"); 121 } 122 123 static __inline void 124 xsaveopt32(char *addr, uint64_t mask) 125 { 126 uint32_t low, hi; 127 128 low = mask; 129 hi = mask >> 32; 130 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 131 "memory"); 132 } 133 134 static __inline void 135 xsaveopt64(char *addr, uint64_t mask) 136 { 137 uint32_t low, hi; 138 139 low = mask; 140 hi = mask >> 32; 141 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) : 142 "memory"); 143 } 144 145 #define start_emulating() load_cr0(rcr0() | CR0_TS) 146 #define stop_emulating() clts() 147 148 CTASSERT(sizeof(struct savefpu) == 512); 149 CTASSERT(sizeof(struct xstate_hdr) == 64); 150 CTASSERT(sizeof(struct savefpu_ymm) == 832); 151 152 /* 153 * This requirement is to make it easier for asm code to calculate 154 * offset of the fpu save area from the pcb address. FPU save area 155 * must be 64-byte aligned. 156 */ 157 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 158 159 /* 160 * Ensure the copy of XCR0 saved in a core is contained in the padding 161 * area. 162 */ 163 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) && 164 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu)); 165 166 static void fpu_clean_state(void); 167 168 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 169 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware"); 170 171 int use_xsave; /* non-static for cpu_switch.S */ 172 uint64_t xsave_mask; /* the same */ 173 static uma_zone_t fpu_save_area_zone; 174 static struct savefpu *fpu_initialstate; 175 176 static struct xsave_area_elm_descr { 177 u_int offset; 178 u_int size; 179 } *xsave_area_desc; 180 181 static void 182 fpusave_xsaveopt64(void *addr) 183 { 184 xsaveopt64((char *)addr, xsave_mask); 185 } 186 187 static void 188 fpusave_xsaveopt3264(void *addr) 189 { 190 if (SV_CURPROC_FLAG(SV_ILP32)) 191 xsaveopt32((char *)addr, xsave_mask); 192 else 193 xsaveopt64((char *)addr, xsave_mask); 194 } 195 196 static void 197 fpusave_xsave64(void *addr) 198 { 199 xsave64((char *)addr, xsave_mask); 200 } 201 202 static void 203 fpusave_xsave3264(void *addr) 204 { 205 if (SV_CURPROC_FLAG(SV_ILP32)) 206 xsave32((char *)addr, xsave_mask); 207 else 208 xsave64((char *)addr, xsave_mask); 209 } 210 211 static void 212 fpurestore_xrstor64(void *addr) 213 { 214 xrstor64((char *)addr, xsave_mask); 215 } 216 217 static void 218 fpurestore_xrstor3264(void *addr) 219 { 220 if (SV_CURPROC_FLAG(SV_ILP32)) 221 xrstor32((char *)addr, xsave_mask); 222 else 223 xrstor64((char *)addr, xsave_mask); 224 } 225 226 static void 227 fpusave_fxsave(void *addr) 228 { 229 230 fxsave((char *)addr); 231 } 232 233 static void 234 fpurestore_fxrstor(void *addr) 235 { 236 237 fxrstor((char *)addr); 238 } 239 240 DEFINE_IFUNC(, void, fpusave, (void *)) 241 { 242 if (!use_xsave) 243 return (fpusave_fxsave); 244 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) { 245 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 246 fpusave_xsaveopt64 : fpusave_xsaveopt3264); 247 } 248 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 249 fpusave_xsave64 : fpusave_xsave3264); 250 } 251 252 DEFINE_IFUNC(, void, fpurestore, (void *)) 253 { 254 if (!use_xsave) 255 return (fpurestore_fxrstor); 256 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ? 257 fpurestore_xrstor64 : fpurestore_xrstor3264); 258 } 259 260 void 261 fpususpend(void *addr) 262 { 263 u_long cr0; 264 265 cr0 = rcr0(); 266 stop_emulating(); 267 fpusave(addr); 268 load_cr0(cr0); 269 } 270 271 void 272 fpuresume(void *addr) 273 { 274 u_long cr0; 275 276 cr0 = rcr0(); 277 stop_emulating(); 278 fninit(); 279 if (use_xsave) 280 load_xcr(XCR0, xsave_mask); 281 fpurestore(addr); 282 load_cr0(cr0); 283 } 284 285 /* 286 * Enable XSAVE if supported and allowed by user. 287 * Calculate the xsave_mask. 288 */ 289 static void 290 fpuinit_bsp1(void) 291 { 292 u_int cp[4]; 293 uint64_t xsave_mask_user; 294 bool old_wp; 295 296 if (!use_xsave) 297 return; 298 cpuid_count(0xd, 0x0, cp); 299 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 300 if ((cp[0] & xsave_mask) != xsave_mask) 301 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 302 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 303 xsave_mask_user = xsave_mask; 304 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user); 305 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 306 xsave_mask &= xsave_mask_user; 307 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 308 xsave_mask &= ~XFEATURE_AVX512; 309 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 310 xsave_mask &= ~XFEATURE_MPX; 311 312 cpuid_count(0xd, 0x1, cp); 313 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) { 314 /* 315 * Patch the XSAVE instruction in the cpu_switch code 316 * to XSAVEOPT. We assume that XSAVE encoding used 317 * REX byte, and set the bit 4 of the r/m byte. 318 * 319 * It seems that some BIOSes give control to the OS 320 * with CR0.WP already set, making the kernel text 321 * read-only before cpu_startup(). 322 */ 323 old_wp = disable_wp(); 324 ctx_switch_xsave32[3] |= 0x10; 325 ctx_switch_xsave[3] |= 0x10; 326 restore_wp(old_wp); 327 } 328 } 329 330 /* 331 * Calculate the fpu save area size. 332 */ 333 static void 334 fpuinit_bsp2(void) 335 { 336 u_int cp[4]; 337 338 if (use_xsave) { 339 cpuid_count(0xd, 0x0, cp); 340 cpu_max_ext_state_size = cp[1]; 341 342 /* 343 * Reload the cpu_feature2, since we enabled OSXSAVE. 344 */ 345 do_cpuid(1, cp); 346 cpu_feature2 = cp[2]; 347 } else 348 cpu_max_ext_state_size = sizeof(struct savefpu); 349 } 350 351 /* 352 * Initialize the floating point unit. 353 */ 354 void 355 fpuinit(void) 356 { 357 register_t saveintr; 358 uint64_t cr4; 359 u_int mxcsr; 360 u_short control; 361 362 TSENTER(); 363 if (IS_BSP()) 364 fpuinit_bsp1(); 365 366 if (use_xsave) { 367 cr4 = rcr4(); 368 369 /* 370 * Revert enablement of PKRU if user disabled its 371 * saving on context switches by clearing the bit in 372 * the xsave mask. Also redundantly clear the bit in 373 * cpu_stdext_feature2 to prevent pmap from ever 374 * trying to set the page table bits. 375 */ 376 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0 && 377 (xsave_mask & XFEATURE_ENABLED_PKRU) == 0) { 378 cr4 &= ~CR4_PKE; 379 cpu_stdext_feature2 &= ~CPUID_STDEXT2_PKU; 380 } 381 382 load_cr4(cr4 | CR4_XSAVE); 383 load_xcr(XCR0, xsave_mask); 384 } 385 386 /* 387 * XCR0 shall be set up before CPU can report the save area size. 388 */ 389 if (IS_BSP()) 390 fpuinit_bsp2(); 391 392 /* 393 * It is too early for critical_enter() to work on AP. 394 */ 395 saveintr = intr_disable(); 396 stop_emulating(); 397 fninit(); 398 control = __INITIAL_FPUCW__; 399 fldcw(control); 400 mxcsr = __INITIAL_MXCSR__; 401 ldmxcsr(mxcsr); 402 start_emulating(); 403 intr_restore(saveintr); 404 TSEXIT(); 405 } 406 407 /* 408 * On the boot CPU we generate a clean state that is used to 409 * initialize the floating point unit when it is first used by a 410 * process. 411 */ 412 static void 413 fpuinitstate(void *arg __unused) 414 { 415 uint64_t *xstate_bv; 416 register_t saveintr; 417 int cp[4], i, max_ext_n; 418 419 /* Do potentially blocking operations before disabling interrupts. */ 420 fpu_save_area_zone = uma_zcreate("FPU_save_area", 421 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 422 XSAVE_AREA_ALIGN - 1, 0); 423 fpu_initialstate = uma_zalloc(fpu_save_area_zone, M_WAITOK | M_ZERO); 424 if (use_xsave) { 425 max_ext_n = flsl(xsave_mask); 426 xsave_area_desc = malloc(max_ext_n * sizeof(struct 427 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 428 } 429 430 cpu_thread_alloc(&thread0); 431 432 saveintr = intr_disable(); 433 stop_emulating(); 434 435 fpusave_fxsave(fpu_initialstate); 436 if (fpu_initialstate->sv_env.en_mxcsr_mask) 437 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask; 438 else 439 cpu_mxcsr_mask = 0xFFBF; 440 441 /* 442 * The fninit instruction does not modify XMM registers or x87 443 * registers (MM/ST). The fpusave call dumped the garbage 444 * contained in the registers after reset to the initial state 445 * saved. Clear XMM and x87 registers file image to make the 446 * startup program state and signal handler XMM/x87 register 447 * content predictable. 448 */ 449 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp)); 450 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm)); 451 452 /* 453 * Create a table describing the layout of the CPU Extended 454 * Save Area. See Intel SDM rev. 075 Vol. 1 13.4.1 "Legacy 455 * Region of an XSAVE Area" for the source of offsets/sizes. 456 */ 457 if (use_xsave) { 458 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) + 459 offsetof(struct xstate_hdr, xstate_bv)); 460 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 461 462 /* x87 state */ 463 xsave_area_desc[0].offset = 0; 464 xsave_area_desc[0].size = 160; 465 /* XMM */ 466 xsave_area_desc[1].offset = 160; 467 xsave_area_desc[1].size = 416 - 160; 468 469 for (i = 2; i < max_ext_n; i++) { 470 cpuid_count(0xd, i, cp); 471 xsave_area_desc[i].offset = cp[1]; 472 xsave_area_desc[i].size = cp[0]; 473 } 474 } 475 476 start_emulating(); 477 intr_restore(saveintr); 478 } 479 /* EFIRT needs this to be initialized before we can enter our EFI environment */ 480 SYSINIT(fpuinitstate, SI_SUB_CPU, SI_ORDER_ANY, fpuinitstate, NULL); 481 482 /* 483 * Free coprocessor (if we have it). 484 */ 485 void 486 fpuexit(struct thread *td) 487 { 488 489 critical_enter(); 490 if (curthread == PCPU_GET(fpcurthread)) { 491 stop_emulating(); 492 fpusave(curpcb->pcb_save); 493 start_emulating(); 494 PCPU_SET(fpcurthread, NULL); 495 } 496 critical_exit(); 497 } 498 499 int 500 fpuformat(void) 501 { 502 503 return (_MC_FPFMT_XMM); 504 } 505 506 /* 507 * The following mechanism is used to ensure that the FPE_... value 508 * that is passed as a trapcode to the signal handler of the user 509 * process does not have more than one bit set. 510 * 511 * Multiple bits may be set if the user process modifies the control 512 * word while a status word bit is already set. While this is a sign 513 * of bad coding, we have no choice than to narrow them down to one 514 * bit, since we must not send a trapcode that is not exactly one of 515 * the FPE_ macros. 516 * 517 * The mechanism has a static table with 127 entries. Each combination 518 * of the 7 FPU status word exception bits directly translates to a 519 * position in this table, where a single FPE_... value is stored. 520 * This FPE_... value stored there is considered the "most important" 521 * of the exception bits and will be sent as the signal code. The 522 * precedence of the bits is based upon Intel Document "Numerical 523 * Applications", Chapter "Special Computational Situations". 524 * 525 * The macro to choose one of these values does these steps: 1) Throw 526 * away status word bits that cannot be masked. 2) Throw away the bits 527 * currently masked in the control word, assuming the user isn't 528 * interested in them anymore. 3) Reinsert status word bit 7 (stack 529 * fault) if it is set, which cannot be masked but must be presered. 530 * 4) Use the remaining bits to point into the trapcode table. 531 * 532 * The 6 maskable bits in order of their preference, as stated in the 533 * above referenced Intel manual: 534 * 1 Invalid operation (FP_X_INV) 535 * 1a Stack underflow 536 * 1b Stack overflow 537 * 1c Operand of unsupported format 538 * 1d SNaN operand. 539 * 2 QNaN operand (not an exception, irrelavant here) 540 * 3 Any other invalid-operation not mentioned above or zero divide 541 * (FP_X_INV, FP_X_DZ) 542 * 4 Denormal operand (FP_X_DNML) 543 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 544 * 6 Inexact result (FP_X_IMP) 545 */ 546 static char fpetable[128] = { 547 0, 548 FPE_FLTINV, /* 1 - INV */ 549 FPE_FLTUND, /* 2 - DNML */ 550 FPE_FLTINV, /* 3 - INV | DNML */ 551 FPE_FLTDIV, /* 4 - DZ */ 552 FPE_FLTINV, /* 5 - INV | DZ */ 553 FPE_FLTDIV, /* 6 - DNML | DZ */ 554 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 555 FPE_FLTOVF, /* 8 - OFL */ 556 FPE_FLTINV, /* 9 - INV | OFL */ 557 FPE_FLTUND, /* A - DNML | OFL */ 558 FPE_FLTINV, /* B - INV | DNML | OFL */ 559 FPE_FLTDIV, /* C - DZ | OFL */ 560 FPE_FLTINV, /* D - INV | DZ | OFL */ 561 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 562 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 563 FPE_FLTUND, /* 10 - UFL */ 564 FPE_FLTINV, /* 11 - INV | UFL */ 565 FPE_FLTUND, /* 12 - DNML | UFL */ 566 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 567 FPE_FLTDIV, /* 14 - DZ | UFL */ 568 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 569 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 570 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 571 FPE_FLTOVF, /* 18 - OFL | UFL */ 572 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 573 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 574 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 575 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 576 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 577 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 578 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 579 FPE_FLTRES, /* 20 - IMP */ 580 FPE_FLTINV, /* 21 - INV | IMP */ 581 FPE_FLTUND, /* 22 - DNML | IMP */ 582 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 583 FPE_FLTDIV, /* 24 - DZ | IMP */ 584 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 585 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 586 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 587 FPE_FLTOVF, /* 28 - OFL | IMP */ 588 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 589 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 590 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 591 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 592 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 593 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 594 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 595 FPE_FLTUND, /* 30 - UFL | IMP */ 596 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 597 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 598 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 599 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 600 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 601 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 602 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 603 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 604 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 605 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 606 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 607 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 608 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 609 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 610 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 611 FPE_FLTSUB, /* 40 - STK */ 612 FPE_FLTSUB, /* 41 - INV | STK */ 613 FPE_FLTUND, /* 42 - DNML | STK */ 614 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 615 FPE_FLTDIV, /* 44 - DZ | STK */ 616 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 617 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 618 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 619 FPE_FLTOVF, /* 48 - OFL | STK */ 620 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 621 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 622 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 623 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 624 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 625 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 626 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 627 FPE_FLTUND, /* 50 - UFL | STK */ 628 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 629 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 630 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 631 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 632 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 633 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 634 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 635 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 636 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 637 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 638 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 639 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 640 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 641 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 642 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 643 FPE_FLTRES, /* 60 - IMP | STK */ 644 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 645 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 646 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 647 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 648 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 649 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 650 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 651 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 652 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 653 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 654 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 655 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 656 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 657 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 658 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 659 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 660 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 661 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 662 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 663 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 664 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 665 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 666 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 667 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 668 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 669 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 670 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 671 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 672 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 673 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 674 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 675 }; 676 677 /* 678 * Read the FP status and control words, then generate si_code value 679 * for SIGFPE. The error code chosen will be one of the 680 * FPE_... macros. It will be sent as the second argument to old 681 * BSD-style signal handlers and as "siginfo_t->si_code" (second 682 * argument) to SA_SIGINFO signal handlers. 683 * 684 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 685 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 686 * usermode code which understands the FPU hardware enough to enable 687 * the exceptions, can also handle clearing the exception state in the 688 * handler. The only consequence of not clearing the exception is the 689 * rethrow of the SIGFPE on return from the signal handler and 690 * reexecution of the corresponding instruction. 691 * 692 * For XMM traps, the exceptions were never cleared. 693 */ 694 int 695 fputrap_x87(void) 696 { 697 struct savefpu *pcb_save; 698 u_short control, status; 699 700 critical_enter(); 701 702 /* 703 * Interrupt handling (for another interrupt) may have pushed the 704 * state to memory. Fetch the relevant parts of the state from 705 * wherever they are. 706 */ 707 if (PCPU_GET(fpcurthread) != curthread) { 708 pcb_save = curpcb->pcb_save; 709 control = pcb_save->sv_env.en_cw; 710 status = pcb_save->sv_env.en_sw; 711 } else { 712 fnstcw(&control); 713 fnstsw(&status); 714 } 715 716 critical_exit(); 717 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 718 } 719 720 int 721 fputrap_sse(void) 722 { 723 u_int mxcsr; 724 725 critical_enter(); 726 if (PCPU_GET(fpcurthread) != curthread) 727 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr; 728 else 729 stmxcsr(&mxcsr); 730 critical_exit(); 731 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 732 } 733 734 static void 735 restore_fpu_curthread(struct thread *td) 736 { 737 struct pcb *pcb; 738 739 /* 740 * Record new context early in case frstor causes a trap. 741 */ 742 PCPU_SET(fpcurthread, td); 743 744 stop_emulating(); 745 fpu_clean_state(); 746 pcb = td->td_pcb; 747 748 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) { 749 /* 750 * This is the first time this thread has used the FPU or 751 * the PCB doesn't contain a clean FPU state. Explicitly 752 * load an initial state. 753 * 754 * We prefer to restore the state from the actual save 755 * area in PCB instead of directly loading from 756 * fpu_initialstate, to ignite the XSAVEOPT 757 * tracking engine. 758 */ 759 bcopy(fpu_initialstate, pcb->pcb_save, 760 cpu_max_ext_state_size); 761 fpurestore(pcb->pcb_save); 762 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__) 763 fldcw(pcb->pcb_initial_fpucw); 764 if (PCB_USER_FPU(pcb)) 765 set_pcb_flags(pcb, PCB_FPUINITDONE | 766 PCB_USERFPUINITDONE); 767 else 768 set_pcb_flags(pcb, PCB_FPUINITDONE); 769 } else 770 fpurestore(pcb->pcb_save); 771 } 772 773 /* 774 * Device Not Available (DNA, #NM) exception handler. 775 * 776 * It would be better to switch FP context here (if curthread != 777 * fpcurthread) and not necessarily for every context switch, but it 778 * is too hard to access foreign pcb's. 779 */ 780 void 781 fpudna(void) 782 { 783 struct thread *td; 784 785 td = curthread; 786 /* 787 * This handler is entered with interrupts enabled, so context 788 * switches may occur before critical_enter() is executed. If 789 * a context switch occurs, then when we regain control, our 790 * state will have been completely restored. The CPU may 791 * change underneath us, but the only part of our context that 792 * lives in the CPU is CR0.TS and that will be "restored" by 793 * setting it on the new CPU. 794 */ 795 critical_enter(); 796 797 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0, 798 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)")); 799 if (__predict_false(PCPU_GET(fpcurthread) == td)) { 800 /* 801 * Some virtual machines seems to set %cr0.TS at 802 * arbitrary moments. Silently clear the TS bit 803 * regardless of the eager/lazy FPU context switch 804 * mode. 805 */ 806 stop_emulating(); 807 } else { 808 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) { 809 panic( 810 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n", 811 PCPU_GET(fpcurthread), 812 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid); 813 } 814 restore_fpu_curthread(td); 815 } 816 critical_exit(); 817 } 818 819 void fpu_activate_sw(struct thread *td); /* Called from the context switch */ 820 void 821 fpu_activate_sw(struct thread *td) 822 { 823 824 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) { 825 PCPU_SET(fpcurthread, NULL); 826 start_emulating(); 827 } else if (PCPU_GET(fpcurthread) != td) { 828 restore_fpu_curthread(td); 829 } 830 } 831 832 void 833 fpudrop(void) 834 { 835 struct thread *td; 836 837 td = PCPU_GET(fpcurthread); 838 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 839 CRITICAL_ASSERT(td); 840 PCPU_SET(fpcurthread, NULL); 841 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE); 842 start_emulating(); 843 } 844 845 /* 846 * Get the user state of the FPU into pcb->pcb_user_save without 847 * dropping ownership (if possible). It returns the FPU ownership 848 * status. 849 */ 850 int 851 fpugetregs(struct thread *td) 852 { 853 struct pcb *pcb; 854 uint64_t *xstate_bv, bit; 855 char *sa; 856 int max_ext_n, i, owned; 857 858 pcb = td->td_pcb; 859 critical_enter(); 860 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) { 861 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb), 862 cpu_max_ext_state_size); 863 get_pcb_user_save_pcb(pcb)->sv_env.en_cw = 864 pcb->pcb_initial_fpucw; 865 fpuuserinited(td); 866 critical_exit(); 867 return (_MC_FPOWNED_PCB); 868 } 869 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 870 fpusave(get_pcb_user_save_pcb(pcb)); 871 owned = _MC_FPOWNED_FPU; 872 } else { 873 owned = _MC_FPOWNED_PCB; 874 } 875 if (use_xsave) { 876 /* 877 * Handle partially saved state. 878 */ 879 sa = (char *)get_pcb_user_save_pcb(pcb); 880 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) + 881 offsetof(struct xstate_hdr, xstate_bv)); 882 max_ext_n = flsl(xsave_mask); 883 for (i = 0; i < max_ext_n; i++) { 884 bit = 1ULL << i; 885 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 886 continue; 887 bcopy((char *)fpu_initialstate + 888 xsave_area_desc[i].offset, 889 sa + xsave_area_desc[i].offset, 890 xsave_area_desc[i].size); 891 *xstate_bv |= bit; 892 } 893 } 894 critical_exit(); 895 return (owned); 896 } 897 898 void 899 fpuuserinited(struct thread *td) 900 { 901 struct pcb *pcb; 902 903 CRITICAL_ASSERT(td); 904 pcb = td->td_pcb; 905 if (PCB_USER_FPU(pcb)) 906 set_pcb_flags(pcb, 907 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 908 else 909 set_pcb_flags(pcb, PCB_FPUINITDONE); 910 } 911 912 int 913 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 914 { 915 struct xstate_hdr *hdr, *ehdr; 916 size_t len, max_len; 917 uint64_t bv; 918 919 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 920 if (xfpustate == NULL) 921 return (0); 922 if (!use_xsave) 923 return (EOPNOTSUPP); 924 925 len = xfpustate_size; 926 if (len < sizeof(struct xstate_hdr)) 927 return (EINVAL); 928 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 929 if (len > max_len) 930 return (EINVAL); 931 932 ehdr = (struct xstate_hdr *)xfpustate; 933 bv = ehdr->xstate_bv; 934 935 /* 936 * Avoid #gp. 937 */ 938 if (bv & ~xsave_mask) 939 return (EINVAL); 940 941 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 942 943 hdr->xstate_bv = bv; 944 bcopy(xfpustate + sizeof(struct xstate_hdr), 945 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 946 947 return (0); 948 } 949 950 /* 951 * Set the state of the FPU. 952 */ 953 int 954 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate, 955 size_t xfpustate_size) 956 { 957 struct pcb *pcb; 958 int error; 959 960 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask; 961 pcb = td->td_pcb; 962 error = 0; 963 critical_enter(); 964 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 965 error = fpusetxstate(td, xfpustate, xfpustate_size); 966 if (error == 0) { 967 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 968 fpurestore(get_pcb_user_save_td(td)); 969 set_pcb_flags(pcb, PCB_FPUINITDONE | 970 PCB_USERFPUINITDONE); 971 } 972 } else { 973 error = fpusetxstate(td, xfpustate, xfpustate_size); 974 if (error == 0) { 975 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 976 fpuuserinited(td); 977 } 978 } 979 critical_exit(); 980 return (error); 981 } 982 983 /* 984 * On AuthenticAMD processors, the fxrstor instruction does not restore 985 * the x87's stored last instruction pointer, last data pointer, and last 986 * opcode values, except in the rare case in which the exception summary 987 * (ES) bit in the x87 status word is set to 1. 988 * 989 * In order to avoid leaking this information across processes, we clean 990 * these values by performing a dummy load before executing fxrstor(). 991 */ 992 static void 993 fpu_clean_state(void) 994 { 995 static float dummy_variable = 0.0; 996 u_short status; 997 998 /* 999 * Clear the ES bit in the x87 status word if it is currently 1000 * set, in order to avoid causing a fault in the upcoming load. 1001 */ 1002 fnstsw(&status); 1003 if (status & 0x80) 1004 fnclex(); 1005 1006 /* 1007 * Load the dummy variable into the x87 stack. This mangles 1008 * the x87 stack, but we don't care since we're about to call 1009 * fxrstor() anyway. 1010 */ 1011 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1012 } 1013 1014 /* 1015 * This really sucks. We want the acpi version only, but it requires 1016 * the isa_if.h file in order to get the definitions. 1017 */ 1018 #include "opt_isa.h" 1019 #ifdef DEV_ISA 1020 #include <isa/isavar.h> 1021 /* 1022 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1023 */ 1024 static struct isa_pnp_id fpupnp_ids[] = { 1025 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1026 { 0 } 1027 }; 1028 1029 static int 1030 fpupnp_probe(device_t dev) 1031 { 1032 int result; 1033 1034 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids); 1035 if (result <= 0) 1036 device_quiet(dev); 1037 return (result); 1038 } 1039 1040 static int 1041 fpupnp_attach(device_t dev) 1042 { 1043 1044 return (0); 1045 } 1046 1047 static device_method_t fpupnp_methods[] = { 1048 /* Device interface */ 1049 DEVMETHOD(device_probe, fpupnp_probe), 1050 DEVMETHOD(device_attach, fpupnp_attach), 1051 DEVMETHOD(device_detach, bus_generic_detach), 1052 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1053 DEVMETHOD(device_suspend, bus_generic_suspend), 1054 DEVMETHOD(device_resume, bus_generic_resume), 1055 { 0, 0 } 1056 }; 1057 1058 static driver_t fpupnp_driver = { 1059 "fpupnp", 1060 fpupnp_methods, 1061 1, /* no softc */ 1062 }; 1063 1064 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, 0, 0); 1065 ISA_PNP_INFO(fpupnp_ids); 1066 #endif /* DEV_ISA */ 1067 1068 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1069 "Kernel contexts for FPU state"); 1070 1071 #define FPU_KERN_CTX_FPUINITDONE 0x01 1072 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */ 1073 #define FPU_KERN_CTX_INUSE 0x04 1074 1075 struct fpu_kern_ctx { 1076 struct savefpu *prev; 1077 uint32_t flags; 1078 char hwstate1[]; 1079 }; 1080 1081 static inline size_t __pure2 1082 fpu_kern_alloc_sz(u_int max_est) 1083 { 1084 return (sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + max_est); 1085 } 1086 1087 static inline int __pure2 1088 fpu_kern_malloc_flags(u_int fpflags) 1089 { 1090 return (((fpflags & FPU_KERN_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 1091 } 1092 1093 struct fpu_kern_ctx * 1094 fpu_kern_alloc_ctx_domain(int domain, u_int flags) 1095 { 1096 return (malloc_domainset(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1097 M_FPUKERN_CTX, DOMAINSET_PREF(domain), 1098 fpu_kern_malloc_flags(flags))); 1099 } 1100 1101 struct fpu_kern_ctx * 1102 fpu_kern_alloc_ctx(u_int flags) 1103 { 1104 return (malloc(fpu_kern_alloc_sz(cpu_max_ext_state_size), 1105 M_FPUKERN_CTX, fpu_kern_malloc_flags(flags))); 1106 } 1107 1108 void 1109 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1110 { 1111 1112 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1113 /* XXXKIB clear the memory ? */ 1114 free(ctx, M_FPUKERN_CTX); 1115 } 1116 1117 static struct savefpu * 1118 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1119 { 1120 vm_offset_t p; 1121 1122 p = (vm_offset_t)&ctx->hwstate1; 1123 p = roundup2(p, XSAVE_AREA_ALIGN); 1124 return ((struct savefpu *)p); 1125 } 1126 1127 void 1128 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1129 { 1130 struct pcb *pcb; 1131 1132 pcb = td->td_pcb; 1133 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL, 1134 ("ctx is required when !FPU_KERN_NOCTX")); 1135 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0, 1136 ("using inuse ctx")); 1137 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0, 1138 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state")); 1139 1140 if ((flags & FPU_KERN_NOCTX) != 0) { 1141 critical_enter(); 1142 stop_emulating(); 1143 if (curthread == PCPU_GET(fpcurthread)) { 1144 fpusave(curpcb->pcb_save); 1145 PCPU_SET(fpcurthread, NULL); 1146 } else { 1147 KASSERT(PCPU_GET(fpcurthread) == NULL, 1148 ("invalid fpcurthread")); 1149 } 1150 1151 /* 1152 * This breaks XSAVEOPT tracker, but 1153 * PCB_FPUNOSAVE state is supposed to never need to 1154 * save FPU context at all. 1155 */ 1156 fpurestore(fpu_initialstate); 1157 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE | 1158 PCB_FPUINITDONE); 1159 return; 1160 } 1161 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1162 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1163 return; 1164 } 1165 critical_enter(); 1166 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1167 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1168 ctx->flags = FPU_KERN_CTX_INUSE; 1169 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0) 1170 ctx->flags |= FPU_KERN_CTX_FPUINITDONE; 1171 fpuexit(td); 1172 ctx->prev = pcb->pcb_save; 1173 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1174 set_pcb_flags(pcb, PCB_KERNFPU); 1175 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1176 critical_exit(); 1177 } 1178 1179 int 1180 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1181 { 1182 struct pcb *pcb; 1183 1184 pcb = td->td_pcb; 1185 1186 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) { 1187 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX")); 1188 KASSERT(PCPU_GET(fpcurthread) == NULL, 1189 ("non-NULL fpcurthread for PCB_FPUNOSAVE")); 1190 CRITICAL_ASSERT(td); 1191 1192 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE); 1193 start_emulating(); 1194 } else { 1195 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1196 ("leaving not inuse ctx")); 1197 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1198 1199 if (is_fpu_kern_thread(0) && 1200 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1201 return (0); 1202 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0, 1203 ("dummy ctx")); 1204 critical_enter(); 1205 if (curthread == PCPU_GET(fpcurthread)) 1206 fpudrop(); 1207 pcb->pcb_save = ctx->prev; 1208 } 1209 1210 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1211 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) { 1212 set_pcb_flags(pcb, PCB_FPUINITDONE); 1213 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1214 clear_pcb_flags(pcb, PCB_KERNFPU); 1215 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0) 1216 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU); 1217 } else { 1218 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0) 1219 set_pcb_flags(pcb, PCB_FPUINITDONE); 1220 else 1221 clear_pcb_flags(pcb, PCB_FPUINITDONE); 1222 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1223 } 1224 critical_exit(); 1225 return (0); 1226 } 1227 1228 int 1229 fpu_kern_thread(u_int flags) 1230 { 1231 1232 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1233 ("Only kthread may use fpu_kern_thread")); 1234 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1235 ("mangled pcb_save")); 1236 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1237 1238 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR); 1239 return (0); 1240 } 1241 1242 int 1243 is_fpu_kern_thread(u_int flags) 1244 { 1245 1246 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1247 return (0); 1248 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0); 1249 } 1250 1251 /* 1252 * FPU save area alloc/free/init utility routines 1253 */ 1254 struct savefpu * 1255 fpu_save_area_alloc(void) 1256 { 1257 1258 return (uma_zalloc(fpu_save_area_zone, M_WAITOK)); 1259 } 1260 1261 void 1262 fpu_save_area_free(struct savefpu *fsa) 1263 { 1264 1265 uma_zfree(fpu_save_area_zone, fsa); 1266 } 1267 1268 void 1269 fpu_save_area_reset(struct savefpu *fsa) 1270 { 1271 1272 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size); 1273 } 1274