1.\" 2.\" Copyright (c) 2019 Intel Corporation 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.Dd April 21, 2020 26.Dt HWPSTATE_INTEL 4 27.Os 28.Sh NAME 29.Nm hwpstate_intel 30.Nd Intel Speed Shift Technology driver 31.Sh SYNOPSIS 32To compile this driver into your kernel 33place the following line in your kernel 34configuration file: 35.Bd -ragged -offset indent 36.Cd "device cpufreq" 37.Ed 38.Sh DESCRIPTION 39The 40.Nm 41driver provides support for hardware-controlled performance states on Intel 42platforms, also known as Intel Speed Shift Technology. 43.Sh LOADER TUNABLES 44.Bl -tag -width indent 45.It Va hint.hwpstate_intel.0.disabled 46Can be used to disable 47.Nm , 48allowing other compatible drivers to manage performance states, like 49.Xr est 4 . 50Defaults to 51.Dv Qq 0 52(enabled). 53.It Va machdep.hwpstate_pkg_ctrl 54Selects between package-level control (the default) and per-core control. 55.Dv Qq 1 56selects package-level control and 57.Dv Qq 0 58selects core-level control. 59.El 60.Sh SYSCTL VARIABLES 61The following 62.Xr sysctl 8 63values are available 64.Bl -tag -width indent 65.It Va dev.hwpstate_intel.%d.%desc 66Describes the attached driver 67.It dev.hwpstate_intel.0.%desc: Intel Speed Shift 68.It Va dev.hwpstate_intel.%d.%driver 69Driver in use, always hwpstate_intel. 70.It dev.hwpstate_intel.0.%driver: hwpstate_intel 71.It Va dev.hwpstate_intel.%d.%parent 72The CPU that is exposing these frequencies. 73For example 74.Va cpu0 . 75.It dev.hwpstate_intel.0.%parent: cpu0 76.It Va dev.hwpstate_intel.%d.epp 77Energy/Performance Preference. 78Valid values range from 0 to 100. 79Setting this field conveys a hint to the hardware regarding a preference towards 80performance (at value 0), energy efficiency (at value 100), or somewhere in 81between. 82.It dev.hwpstate_intel.0.epp: 0 83.El 84.Sh COMPATIBILITY 85.Nm 86is only found on supported Intel CPUs. 87.Sh SEE ALSO 88.Xr cpufreq 4 89.Rs 90.%T "Intel 64 and IA-32 Architectures Software Developer Manuals" 91.%U "http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" 92.Re 93.Sh AUTHORS 94This manual page was written by 95.An D Scott Phillips Aq Mt scottph@FreeBSD.org . 96