xref: /freebsd/lib/libpmc/pmu-events/arch/x86/nehalemep/pipeline.json (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c) 
1[
2    {
3        "BriefDescription": "Cycles the divider is busy",
4        "Counter": "0,1,2,3",
5        "EventCode": "0x14",
6        "EventName": "ARITH.CYCLES_DIV_BUSY",
7        "SampleAfterValue": "2000000",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Divide Operations executed",
12        "Counter": "0,1,2,3",
13        "CounterMask": "1",
14        "EdgeDetect": "1",
15        "EventCode": "0x14",
16        "EventName": "ARITH.DIV",
17        "Invert": "1",
18        "SampleAfterValue": "2000000",
19        "UMask": "0x1"
20    },
21    {
22        "BriefDescription": "Multiply operations executed",
23        "Counter": "0,1,2,3",
24        "EventCode": "0x14",
25        "EventName": "ARITH.MUL",
26        "SampleAfterValue": "2000000",
27        "UMask": "0x2"
28    },
29    {
30        "BriefDescription": "BACLEAR asserted with bad target address",
31        "Counter": "0,1,2,3",
32        "EventCode": "0xE6",
33        "EventName": "BACLEAR.BAD_TARGET",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x2"
36    },
37    {
38        "BriefDescription": "BACLEAR asserted, regardless of cause",
39        "Counter": "0,1,2,3",
40        "EventCode": "0xE6",
41        "EventName": "BACLEAR.CLEAR",
42        "SampleAfterValue": "2000000",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Instruction queue forced BACLEAR",
47        "Counter": "0,1,2,3",
48        "EventCode": "0xA7",
49        "EventName": "BACLEAR_FORCE_IQ",
50        "SampleAfterValue": "2000000",
51        "UMask": "0x1"
52    },
53    {
54        "BriefDescription": "Early Branch Prediciton Unit clears",
55        "Counter": "0,1,2,3",
56        "EventCode": "0xE8",
57        "EventName": "BPU_CLEARS.EARLY",
58        "SampleAfterValue": "2000000",
59        "UMask": "0x1"
60    },
61    {
62        "BriefDescription": "Late Branch Prediction Unit clears",
63        "Counter": "0,1,2,3",
64        "EventCode": "0xE8",
65        "EventName": "BPU_CLEARS.LATE",
66        "SampleAfterValue": "2000000",
67        "UMask": "0x2"
68    },
69    {
70        "BriefDescription": "Branch prediction unit missed call or return",
71        "Counter": "0,1,2,3",
72        "EventCode": "0xE5",
73        "EventName": "BPU_MISSED_CALL_RET",
74        "SampleAfterValue": "2000000",
75        "UMask": "0x1"
76    },
77    {
78        "BriefDescription": "Branch instructions decoded",
79        "Counter": "0,1,2,3",
80        "EventCode": "0xE0",
81        "EventName": "BR_INST_DECODED",
82        "SampleAfterValue": "2000000",
83        "UMask": "0x1"
84    },
85    {
86        "BriefDescription": "Branch instructions executed",
87        "Counter": "0,1,2,3",
88        "EventCode": "0x88",
89        "EventName": "BR_INST_EXEC.ANY",
90        "SampleAfterValue": "200000",
91        "UMask": "0x7f"
92    },
93    {
94        "BriefDescription": "Conditional branch instructions executed",
95        "Counter": "0,1,2,3",
96        "EventCode": "0x88",
97        "EventName": "BR_INST_EXEC.COND",
98        "SampleAfterValue": "200000",
99        "UMask": "0x1"
100    },
101    {
102        "BriefDescription": "Unconditional branches executed",
103        "Counter": "0,1,2,3",
104        "EventCode": "0x88",
105        "EventName": "BR_INST_EXEC.DIRECT",
106        "SampleAfterValue": "200000",
107        "UMask": "0x2"
108    },
109    {
110        "BriefDescription": "Unconditional call branches executed",
111        "Counter": "0,1,2,3",
112        "EventCode": "0x88",
113        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
114        "SampleAfterValue": "20000",
115        "UMask": "0x10"
116    },
117    {
118        "BriefDescription": "Indirect call branches executed",
119        "Counter": "0,1,2,3",
120        "EventCode": "0x88",
121        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
122        "SampleAfterValue": "20000",
123        "UMask": "0x20"
124    },
125    {
126        "BriefDescription": "Indirect non call branches executed",
127        "Counter": "0,1,2,3",
128        "EventCode": "0x88",
129        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
130        "SampleAfterValue": "20000",
131        "UMask": "0x4"
132    },
133    {
134        "BriefDescription": "Call branches executed",
135        "Counter": "0,1,2,3",
136        "EventCode": "0x88",
137        "EventName": "BR_INST_EXEC.NEAR_CALLS",
138        "SampleAfterValue": "20000",
139        "UMask": "0x30"
140    },
141    {
142        "BriefDescription": "All non call branches executed",
143        "Counter": "0,1,2,3",
144        "EventCode": "0x88",
145        "EventName": "BR_INST_EXEC.NON_CALLS",
146        "SampleAfterValue": "200000",
147        "UMask": "0x7"
148    },
149    {
150        "BriefDescription": "Indirect return branches executed",
151        "Counter": "0,1,2,3",
152        "EventCode": "0x88",
153        "EventName": "BR_INST_EXEC.RETURN_NEAR",
154        "SampleAfterValue": "20000",
155        "UMask": "0x8"
156    },
157    {
158        "BriefDescription": "Taken branches executed",
159        "Counter": "0,1,2,3",
160        "EventCode": "0x88",
161        "EventName": "BR_INST_EXEC.TAKEN",
162        "SampleAfterValue": "200000",
163        "UMask": "0x40"
164    },
165    {
166        "BriefDescription": "Retired branch instructions (Precise Event)",
167        "Counter": "0,1,2,3",
168        "EventCode": "0xC4",
169        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
170        "PEBS": "1",
171        "SampleAfterValue": "200000",
172        "UMask": "0x4"
173    },
174    {
175        "BriefDescription": "Retired conditional branch instructions (Precise Event)",
176        "Counter": "0,1,2,3",
177        "EventCode": "0xC4",
178        "EventName": "BR_INST_RETIRED.CONDITIONAL",
179        "PEBS": "1",
180        "SampleAfterValue": "200000",
181        "UMask": "0x1"
182    },
183    {
184        "BriefDescription": "Retired near call instructions (Precise Event)",
185        "Counter": "0,1,2,3",
186        "EventCode": "0xC4",
187        "EventName": "BR_INST_RETIRED.NEAR_CALL",
188        "PEBS": "1",
189        "SampleAfterValue": "20000",
190        "UMask": "0x2"
191    },
192    {
193        "BriefDescription": "Mispredicted branches executed",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x89",
196        "EventName": "BR_MISP_EXEC.ANY",
197        "SampleAfterValue": "20000",
198        "UMask": "0x7f"
199    },
200    {
201        "BriefDescription": "Mispredicted conditional branches executed",
202        "Counter": "0,1,2,3",
203        "EventCode": "0x89",
204        "EventName": "BR_MISP_EXEC.COND",
205        "SampleAfterValue": "20000",
206        "UMask": "0x1"
207    },
208    {
209        "BriefDescription": "Mispredicted unconditional branches executed",
210        "Counter": "0,1,2,3",
211        "EventCode": "0x89",
212        "EventName": "BR_MISP_EXEC.DIRECT",
213        "SampleAfterValue": "20000",
214        "UMask": "0x2"
215    },
216    {
217        "BriefDescription": "Mispredicted non call branches executed",
218        "Counter": "0,1,2,3",
219        "EventCode": "0x89",
220        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
221        "SampleAfterValue": "2000",
222        "UMask": "0x10"
223    },
224    {
225        "BriefDescription": "Mispredicted indirect call branches executed",
226        "Counter": "0,1,2,3",
227        "EventCode": "0x89",
228        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
229        "SampleAfterValue": "2000",
230        "UMask": "0x20"
231    },
232    {
233        "BriefDescription": "Mispredicted indirect non call branches executed",
234        "Counter": "0,1,2,3",
235        "EventCode": "0x89",
236        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
237        "SampleAfterValue": "2000",
238        "UMask": "0x4"
239    },
240    {
241        "BriefDescription": "Mispredicted call branches executed",
242        "Counter": "0,1,2,3",
243        "EventCode": "0x89",
244        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
245        "SampleAfterValue": "2000",
246        "UMask": "0x30"
247    },
248    {
249        "BriefDescription": "Mispredicted non call branches executed",
250        "Counter": "0,1,2,3",
251        "EventCode": "0x89",
252        "EventName": "BR_MISP_EXEC.NON_CALLS",
253        "SampleAfterValue": "20000",
254        "UMask": "0x7"
255    },
256    {
257        "BriefDescription": "Mispredicted return branches executed",
258        "Counter": "0,1,2,3",
259        "EventCode": "0x89",
260        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
261        "SampleAfterValue": "2000",
262        "UMask": "0x8"
263    },
264    {
265        "BriefDescription": "Mispredicted taken branches executed",
266        "Counter": "0,1,2,3",
267        "EventCode": "0x89",
268        "EventName": "BR_MISP_EXEC.TAKEN",
269        "SampleAfterValue": "20000",
270        "UMask": "0x40"
271    },
272    {
273        "BriefDescription": "Mispredicted near retired calls (Precise Event)",
274        "Counter": "0,1,2,3",
275        "EventCode": "0xC5",
276        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
277        "PEBS": "1",
278        "SampleAfterValue": "2000",
279        "UMask": "0x2"
280    },
281    {
282        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
283        "Counter": "Fixed counter 3",
284        "EventCode": "0x0",
285        "EventName": "CPU_CLK_UNHALTED.REF",
286        "SampleAfterValue": "2000000",
287        "UMask": "0x0"
288    },
289    {
290        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
291        "Counter": "0,1,2,3",
292        "EventCode": "0x3C",
293        "EventName": "CPU_CLK_UNHALTED.REF_P",
294        "SampleAfterValue": "100000",
295        "UMask": "0x1"
296    },
297    {
298        "BriefDescription": "Cycles when thread is not halted (fixed counter)",
299        "Counter": "Fixed counter 2",
300        "EventCode": "0x0",
301        "EventName": "CPU_CLK_UNHALTED.THREAD",
302        "SampleAfterValue": "2000000",
303        "UMask": "0x0"
304    },
305    {
306        "BriefDescription": "Cycles when thread is not halted (programmable counter)",
307        "Counter": "0,1,2,3",
308        "EventCode": "0x3C",
309        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
310        "SampleAfterValue": "2000000",
311        "UMask": "0x0"
312    },
313    {
314        "BriefDescription": "Total CPU cycles",
315        "Counter": "0,1,2,3",
316        "CounterMask": "2",
317        "EventCode": "0x3C",
318        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
319        "Invert": "1",
320        "SampleAfterValue": "2000000",
321        "UMask": "0x0"
322    },
323    {
324        "BriefDescription": "Any Instruction Length Decoder stall cycles",
325        "Counter": "0,1,2,3",
326        "EventCode": "0x87",
327        "EventName": "ILD_STALL.ANY",
328        "SampleAfterValue": "2000000",
329        "UMask": "0xf"
330    },
331    {
332        "BriefDescription": "Instruction Queue full stall cycles",
333        "Counter": "0,1,2,3",
334        "EventCode": "0x87",
335        "EventName": "ILD_STALL.IQ_FULL",
336        "SampleAfterValue": "2000000",
337        "UMask": "0x4"
338    },
339    {
340        "BriefDescription": "Length Change Prefix stall cycles",
341        "Counter": "0,1,2,3",
342        "EventCode": "0x87",
343        "EventName": "ILD_STALL.LCP",
344        "SampleAfterValue": "2000000",
345        "UMask": "0x1"
346    },
347    {
348        "BriefDescription": "Stall cycles due to BPU MRU bypass",
349        "Counter": "0,1,2,3",
350        "EventCode": "0x87",
351        "EventName": "ILD_STALL.MRU",
352        "SampleAfterValue": "2000000",
353        "UMask": "0x2"
354    },
355    {
356        "BriefDescription": "Regen stall cycles",
357        "Counter": "0,1,2,3",
358        "EventCode": "0x87",
359        "EventName": "ILD_STALL.REGEN",
360        "SampleAfterValue": "2000000",
361        "UMask": "0x8"
362    },
363    {
364        "BriefDescription": "Instructions that must be decoded by decoder 0",
365        "Counter": "0,1,2,3",
366        "EventCode": "0x18",
367        "EventName": "INST_DECODED.DEC0",
368        "SampleAfterValue": "2000000",
369        "UMask": "0x1"
370    },
371    {
372        "BriefDescription": "Instructions written to instruction queue.",
373        "Counter": "0,1,2,3",
374        "EventCode": "0x17",
375        "EventName": "INST_QUEUE_WRITES",
376        "SampleAfterValue": "2000000",
377        "UMask": "0x1"
378    },
379    {
380        "BriefDescription": "Cycles instructions are written to the instruction queue",
381        "Counter": "0,1,2,3",
382        "EventCode": "0x1E",
383        "EventName": "INST_QUEUE_WRITE_CYCLES",
384        "SampleAfterValue": "2000000",
385        "UMask": "0x1"
386    },
387    {
388        "BriefDescription": "Instructions retired (fixed counter)",
389        "Counter": "Fixed counter 1",
390        "EventCode": "0x0",
391        "EventName": "INST_RETIRED.ANY",
392        "SampleAfterValue": "2000000",
393        "UMask": "0x0"
394    },
395    {
396        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
397        "Counter": "0,1,2,3",
398        "EventCode": "0xC0",
399        "EventName": "INST_RETIRED.ANY_P",
400        "PEBS": "1",
401        "SampleAfterValue": "2000000",
402        "UMask": "0x1"
403    },
404    {
405        "BriefDescription": "Retired MMX instructions (Precise Event)",
406        "Counter": "0,1,2,3",
407        "EventCode": "0xC0",
408        "EventName": "INST_RETIRED.MMX",
409        "PEBS": "1",
410        "SampleAfterValue": "2000000",
411        "UMask": "0x4"
412    },
413    {
414        "BriefDescription": "Total cycles (Precise Event)",
415        "Counter": "0,1,2,3",
416        "CounterMask": "16",
417        "EventCode": "0xC0",
418        "EventName": "INST_RETIRED.TOTAL_CYCLES",
419        "Invert": "1",
420        "PEBS": "1",
421        "SampleAfterValue": "2000000",
422        "UMask": "0x1"
423    },
424    {
425        "BriefDescription": "Total cycles (Precise Event)",
426        "Counter": "0,1,2,3",
427        "CounterMask": "16",
428        "EventCode": "0xC0",
429        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
430        "Invert": "1",
431        "PEBS": "2",
432        "SampleAfterValue": "2000000",
433        "UMask": "0x1"
434    },
435    {
436        "BriefDescription": "Retired floating-point operations (Precise Event)",
437        "Counter": "0,1,2,3",
438        "EventCode": "0xC0",
439        "EventName": "INST_RETIRED.X87",
440        "PEBS": "1",
441        "SampleAfterValue": "2000000",
442        "UMask": "0x2"
443    },
444    {
445        "BriefDescription": "Load operations conflicting with software prefetches",
446        "Counter": "0,1",
447        "EventCode": "0x4C",
448        "EventName": "LOAD_HIT_PRE",
449        "SampleAfterValue": "200000",
450        "UMask": "0x1"
451    },
452    {
453        "BriefDescription": "Cycles when uops were delivered by the LSD",
454        "Counter": "0,1,2,3",
455        "CounterMask": "1",
456        "EventCode": "0xA8",
457        "EventName": "LSD.ACTIVE",
458        "SampleAfterValue": "2000000",
459        "UMask": "0x1"
460    },
461    {
462        "BriefDescription": "Cycles no uops were delivered by the LSD",
463        "Counter": "0,1,2,3",
464        "CounterMask": "1",
465        "EventCode": "0xA8",
466        "EventName": "LSD.INACTIVE",
467        "Invert": "1",
468        "SampleAfterValue": "2000000",
469        "UMask": "0x1"
470    },
471    {
472        "BriefDescription": "Loops that can't stream from the instruction queue",
473        "Counter": "0,1,2,3",
474        "EventCode": "0x20",
475        "EventName": "LSD_OVERFLOW",
476        "SampleAfterValue": "2000000",
477        "UMask": "0x1"
478    },
479    {
480        "BriefDescription": "Cycles machine clear asserted",
481        "Counter": "0,1,2,3",
482        "EventCode": "0xC3",
483        "EventName": "MACHINE_CLEARS.CYCLES",
484        "SampleAfterValue": "20000",
485        "UMask": "0x1"
486    },
487    {
488        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
489        "Counter": "0,1,2,3",
490        "EventCode": "0xC3",
491        "EventName": "MACHINE_CLEARS.MEM_ORDER",
492        "SampleAfterValue": "20000",
493        "UMask": "0x2"
494    },
495    {
496        "BriefDescription": "Self-Modifying Code detected",
497        "Counter": "0,1,2,3",
498        "EventCode": "0xC3",
499        "EventName": "MACHINE_CLEARS.SMC",
500        "SampleAfterValue": "20000",
501        "UMask": "0x4"
502    },
503    {
504        "BriefDescription": "All RAT stall cycles",
505        "Counter": "0,1,2,3",
506        "EventCode": "0xD2",
507        "EventName": "RAT_STALLS.ANY",
508        "SampleAfterValue": "2000000",
509        "UMask": "0xf"
510    },
511    {
512        "BriefDescription": "Flag stall cycles",
513        "Counter": "0,1,2,3",
514        "EventCode": "0xD2",
515        "EventName": "RAT_STALLS.FLAGS",
516        "SampleAfterValue": "2000000",
517        "UMask": "0x1"
518    },
519    {
520        "BriefDescription": "Partial register stall cycles",
521        "Counter": "0,1,2,3",
522        "EventCode": "0xD2",
523        "EventName": "RAT_STALLS.REGISTERS",
524        "SampleAfterValue": "2000000",
525        "UMask": "0x2"
526    },
527    {
528        "BriefDescription": "ROB read port stalls cycles",
529        "Counter": "0,1,2,3",
530        "EventCode": "0xD2",
531        "EventName": "RAT_STALLS.ROB_READ_PORT",
532        "SampleAfterValue": "2000000",
533        "UMask": "0x4"
534    },
535    {
536        "BriefDescription": "Scoreboard stall cycles",
537        "Counter": "0,1,2,3",
538        "EventCode": "0xD2",
539        "EventName": "RAT_STALLS.SCOREBOARD",
540        "SampleAfterValue": "2000000",
541        "UMask": "0x8"
542    },
543    {
544        "BriefDescription": "Resource related stall cycles",
545        "Counter": "0,1,2,3",
546        "EventCode": "0xA2",
547        "EventName": "RESOURCE_STALLS.ANY",
548        "SampleAfterValue": "2000000",
549        "UMask": "0x1"
550    },
551    {
552        "BriefDescription": "FPU control word write stall cycles",
553        "Counter": "0,1,2,3",
554        "EventCode": "0xA2",
555        "EventName": "RESOURCE_STALLS.FPCW",
556        "SampleAfterValue": "2000000",
557        "UMask": "0x20"
558    },
559    {
560        "BriefDescription": "Load buffer stall cycles",
561        "Counter": "0,1,2,3",
562        "EventCode": "0xA2",
563        "EventName": "RESOURCE_STALLS.LOAD",
564        "SampleAfterValue": "2000000",
565        "UMask": "0x2"
566    },
567    {
568        "BriefDescription": "MXCSR rename stall cycles",
569        "Counter": "0,1,2,3",
570        "EventCode": "0xA2",
571        "EventName": "RESOURCE_STALLS.MXCSR",
572        "SampleAfterValue": "2000000",
573        "UMask": "0x40"
574    },
575    {
576        "BriefDescription": "Other Resource related stall cycles",
577        "Counter": "0,1,2,3",
578        "EventCode": "0xA2",
579        "EventName": "RESOURCE_STALLS.OTHER",
580        "SampleAfterValue": "2000000",
581        "UMask": "0x80"
582    },
583    {
584        "BriefDescription": "ROB full stall cycles",
585        "Counter": "0,1,2,3",
586        "EventCode": "0xA2",
587        "EventName": "RESOURCE_STALLS.ROB_FULL",
588        "SampleAfterValue": "2000000",
589        "UMask": "0x10"
590    },
591    {
592        "BriefDescription": "Reservation Station full stall cycles",
593        "Counter": "0,1,2,3",
594        "EventCode": "0xA2",
595        "EventName": "RESOURCE_STALLS.RS_FULL",
596        "SampleAfterValue": "2000000",
597        "UMask": "0x4"
598    },
599    {
600        "BriefDescription": "Store buffer stall cycles",
601        "Counter": "0,1,2,3",
602        "EventCode": "0xA2",
603        "EventName": "RESOURCE_STALLS.STORE",
604        "SampleAfterValue": "2000000",
605        "UMask": "0x8"
606    },
607    {
608        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
609        "Counter": "0,1,2,3",
610        "EventCode": "0xC7",
611        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
612        "PEBS": "1",
613        "SampleAfterValue": "200000",
614        "UMask": "0x4"
615    },
616    {
617        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
618        "Counter": "0,1,2,3",
619        "EventCode": "0xC7",
620        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
621        "PEBS": "1",
622        "SampleAfterValue": "200000",
623        "UMask": "0x1"
624    },
625    {
626        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
627        "Counter": "0,1,2,3",
628        "EventCode": "0xC7",
629        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
630        "PEBS": "1",
631        "SampleAfterValue": "200000",
632        "UMask": "0x8"
633    },
634    {
635        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
636        "Counter": "0,1,2,3",
637        "EventCode": "0xC7",
638        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
639        "PEBS": "1",
640        "SampleAfterValue": "200000",
641        "UMask": "0x2"
642    },
643    {
644        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
645        "Counter": "0,1,2,3",
646        "EventCode": "0xC7",
647        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
648        "PEBS": "1",
649        "SampleAfterValue": "200000",
650        "UMask": "0x10"
651    },
652    {
653        "BriefDescription": "Stack pointer instructions decoded",
654        "Counter": "0,1,2,3",
655        "EventCode": "0xD1",
656        "EventName": "UOPS_DECODED.ESP_FOLDING",
657        "SampleAfterValue": "2000000",
658        "UMask": "0x4"
659    },
660    {
661        "BriefDescription": "Stack pointer sync operations",
662        "Counter": "0,1,2,3",
663        "EventCode": "0xD1",
664        "EventName": "UOPS_DECODED.ESP_SYNC",
665        "SampleAfterValue": "2000000",
666        "UMask": "0x8"
667    },
668    {
669        "BriefDescription": "Uops decoded by Microcode Sequencer",
670        "Counter": "0,1,2,3",
671        "CounterMask": "1",
672        "EventCode": "0xD1",
673        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
674        "SampleAfterValue": "2000000",
675        "UMask": "0x2"
676    },
677    {
678        "BriefDescription": "Cycles no Uops are decoded",
679        "Counter": "0,1,2,3",
680        "CounterMask": "1",
681        "EventCode": "0xD1",
682        "EventName": "UOPS_DECODED.STALL_CYCLES",
683        "Invert": "1",
684        "SampleAfterValue": "2000000",
685        "UMask": "0x1"
686    },
687    {
688        "AnyThread": "1",
689        "BriefDescription": "Cycles Uops executed on any port (core count)",
690        "Counter": "0,1,2,3",
691        "CounterMask": "1",
692        "EventCode": "0xB1",
693        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
694        "SampleAfterValue": "2000000",
695        "UMask": "0x3f"
696    },
697    {
698        "AnyThread": "1",
699        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
700        "Counter": "0,1,2,3",
701        "CounterMask": "1",
702        "EventCode": "0xB1",
703        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
704        "SampleAfterValue": "2000000",
705        "UMask": "0x1f"
706    },
707    {
708        "AnyThread": "1",
709        "BriefDescription": "Uops executed on any port (core count)",
710        "Counter": "0,1,2,3",
711        "CounterMask": "1",
712        "EdgeDetect": "1",
713        "EventCode": "0xB1",
714        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
715        "Invert": "1",
716        "SampleAfterValue": "2000000",
717        "UMask": "0x3f"
718    },
719    {
720        "AnyThread": "1",
721        "BriefDescription": "Uops executed on ports 0-4 (core count)",
722        "Counter": "0,1,2,3",
723        "CounterMask": "1",
724        "EdgeDetect": "1",
725        "EventCode": "0xB1",
726        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
727        "Invert": "1",
728        "SampleAfterValue": "2000000",
729        "UMask": "0x1f"
730    },
731    {
732        "AnyThread": "1",
733        "BriefDescription": "Cycles no Uops issued on any port (core count)",
734        "Counter": "0,1,2,3",
735        "CounterMask": "1",
736        "EventCode": "0xB1",
737        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
738        "Invert": "1",
739        "SampleAfterValue": "2000000",
740        "UMask": "0x3f"
741    },
742    {
743        "AnyThread": "1",
744        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
745        "Counter": "0,1,2,3",
746        "CounterMask": "1",
747        "EventCode": "0xB1",
748        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
749        "Invert": "1",
750        "SampleAfterValue": "2000000",
751        "UMask": "0x1f"
752    },
753    {
754        "BriefDescription": "Uops executed on port 0",
755        "Counter": "0,1,2,3",
756        "EventCode": "0xB1",
757        "EventName": "UOPS_EXECUTED.PORT0",
758        "SampleAfterValue": "2000000",
759        "UMask": "0x1"
760    },
761    {
762        "BriefDescription": "Uops issued on ports 0, 1 or 5",
763        "Counter": "0,1,2,3",
764        "EventCode": "0xB1",
765        "EventName": "UOPS_EXECUTED.PORT015",
766        "SampleAfterValue": "2000000",
767        "UMask": "0x40"
768    },
769    {
770        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
771        "Counter": "0,1,2,3",
772        "CounterMask": "1",
773        "EventCode": "0xB1",
774        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
775        "Invert": "1",
776        "SampleAfterValue": "2000000",
777        "UMask": "0x40"
778    },
779    {
780        "BriefDescription": "Uops executed on port 1",
781        "Counter": "0,1,2,3",
782        "EventCode": "0xB1",
783        "EventName": "UOPS_EXECUTED.PORT1",
784        "SampleAfterValue": "2000000",
785        "UMask": "0x2"
786    },
787    {
788        "AnyThread": "1",
789        "BriefDescription": "Uops issued on ports 2, 3 or 4",
790        "Counter": "0,1,2,3",
791        "EventCode": "0xB1",
792        "EventName": "UOPS_EXECUTED.PORT234_CORE",
793        "SampleAfterValue": "2000000",
794        "UMask": "0x80"
795    },
796    {
797        "AnyThread": "1",
798        "BriefDescription": "Uops executed on port 2 (core count)",
799        "Counter": "0,1,2,3",
800        "EventCode": "0xB1",
801        "EventName": "UOPS_EXECUTED.PORT2_CORE",
802        "SampleAfterValue": "2000000",
803        "UMask": "0x4"
804    },
805    {
806        "AnyThread": "1",
807        "BriefDescription": "Uops executed on port 3 (core count)",
808        "Counter": "0,1,2,3",
809        "EventCode": "0xB1",
810        "EventName": "UOPS_EXECUTED.PORT3_CORE",
811        "SampleAfterValue": "2000000",
812        "UMask": "0x8"
813    },
814    {
815        "AnyThread": "1",
816        "BriefDescription": "Uops executed on port 4 (core count)",
817        "Counter": "0,1,2,3",
818        "EventCode": "0xB1",
819        "EventName": "UOPS_EXECUTED.PORT4_CORE",
820        "SampleAfterValue": "2000000",
821        "UMask": "0x10"
822    },
823    {
824        "BriefDescription": "Uops executed on port 5",
825        "Counter": "0,1,2,3",
826        "EventCode": "0xB1",
827        "EventName": "UOPS_EXECUTED.PORT5",
828        "SampleAfterValue": "2000000",
829        "UMask": "0x20"
830    },
831    {
832        "BriefDescription": "Uops issued",
833        "Counter": "0,1,2,3",
834        "EventCode": "0xE",
835        "EventName": "UOPS_ISSUED.ANY",
836        "SampleAfterValue": "2000000",
837        "UMask": "0x1"
838    },
839    {
840        "AnyThread": "1",
841        "BriefDescription": "Cycles no Uops were issued on any thread",
842        "Counter": "0,1,2,3",
843        "CounterMask": "1",
844        "EventCode": "0xE",
845        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
846        "Invert": "1",
847        "SampleAfterValue": "2000000",
848        "UMask": "0x1"
849    },
850    {
851        "AnyThread": "1",
852        "BriefDescription": "Cycles Uops were issued on either thread",
853        "Counter": "0,1,2,3",
854        "CounterMask": "1",
855        "EventCode": "0xE",
856        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
857        "SampleAfterValue": "2000000",
858        "UMask": "0x1"
859    },
860    {
861        "BriefDescription": "Fused Uops issued",
862        "Counter": "0,1,2,3",
863        "EventCode": "0xE",
864        "EventName": "UOPS_ISSUED.FUSED",
865        "SampleAfterValue": "2000000",
866        "UMask": "0x2"
867    },
868    {
869        "BriefDescription": "Cycles no Uops were issued",
870        "Counter": "0,1,2,3",
871        "CounterMask": "1",
872        "EventCode": "0xE",
873        "EventName": "UOPS_ISSUED.STALL_CYCLES",
874        "Invert": "1",
875        "SampleAfterValue": "2000000",
876        "UMask": "0x1"
877    },
878    {
879        "BriefDescription": "Cycles Uops are being retired",
880        "Counter": "0,1,2,3",
881        "CounterMask": "1",
882        "EventCode": "0xC2",
883        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
884        "PEBS": "1",
885        "SampleAfterValue": "2000000",
886        "UMask": "0x1"
887    },
888    {
889        "BriefDescription": "Uops retired (Precise Event)",
890        "Counter": "0,1,2,3",
891        "EventCode": "0xC2",
892        "EventName": "UOPS_RETIRED.ANY",
893        "PEBS": "1",
894        "SampleAfterValue": "2000000",
895        "UMask": "0x1"
896    },
897    {
898        "BriefDescription": "Macro-fused Uops retired (Precise Event)",
899        "Counter": "0,1,2,3",
900        "EventCode": "0xC2",
901        "EventName": "UOPS_RETIRED.MACRO_FUSED",
902        "PEBS": "1",
903        "SampleAfterValue": "2000000",
904        "UMask": "0x4"
905    },
906    {
907        "BriefDescription": "Retirement slots used (Precise Event)",
908        "Counter": "0,1,2,3",
909        "EventCode": "0xC2",
910        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
911        "PEBS": "1",
912        "SampleAfterValue": "2000000",
913        "UMask": "0x2"
914    },
915    {
916        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
917        "Counter": "0,1,2,3",
918        "CounterMask": "1",
919        "EventCode": "0xC2",
920        "EventName": "UOPS_RETIRED.STALL_CYCLES",
921        "Invert": "1",
922        "PEBS": "1",
923        "SampleAfterValue": "2000000",
924        "UMask": "0x1"
925    },
926    {
927        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
928        "Counter": "0,1,2,3",
929        "CounterMask": "16",
930        "EventCode": "0xC2",
931        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
932        "Invert": "1",
933        "PEBS": "1",
934        "SampleAfterValue": "2000000",
935        "UMask": "0x1"
936    },
937    {
938        "BriefDescription": "Uop unfusions due to FP exceptions",
939        "Counter": "0,1,2,3",
940        "EventCode": "0xDB",
941        "EventName": "UOP_UNFUSION",
942        "SampleAfterValue": "2000000",
943        "UMask": "0x1"
944    }
945]
946