1[ 2 { 3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x5C", 7 "EventName": "CPL_CYCLES.RING0", 8 "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EdgeDetect": "1", 18 "EventCode": "0x5C", 19 "EventName": "CPL_CYCLES.RING0_TRANS", 20 "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 21 "SampleAfterValue": "100007", 22 "UMask": "0x1" 23 }, 24 { 25 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 26 "Counter": "0,1,2,3", 27 "CounterHTOff": "0,1,2,3,4,5,6,7", 28 "EventCode": "0x5C", 29 "EventName": "CPL_CYCLES.RING123", 30 "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 31 "SampleAfterValue": "2000003", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 36 "Counter": "0,1,2,3", 37 "CounterHTOff": "0,1,2,3,4,5,6,7", 38 "EventCode": "0x63", 39 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40 "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 41 "SampleAfterValue": "2000003", 42 "UMask": "0x1" 43 } 44]