xref: /freebsd/lib/libpmc/pmu-events/arch/x86/alderlake/other.json (revision 18054d0220cfc8df9c9568c437bd6fbb59d53c3c)
1*18054d02SAlexander Motin[
2*18054d02SAlexander Motin    {
3*18054d02SAlexander Motin        "BriefDescription": "Counts demand data reads that have any type of response.",
4*18054d02SAlexander Motin        "Counter": "0,1,2,3",
5*18054d02SAlexander Motin        "EventCode": "0xB7",
6*18054d02SAlexander Motin        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
7*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
8*18054d02SAlexander Motin        "MSRValue": "0x10001",
9*18054d02SAlexander Motin        "SampleAfterValue": "100003",
10*18054d02SAlexander Motin        "UMask": "0x1",
11*18054d02SAlexander Motin        "Unit": "cpu_atom"
12*18054d02SAlexander Motin    },
13*18054d02SAlexander Motin    {
14*18054d02SAlexander Motin        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
15*18054d02SAlexander Motin        "Counter": "0,1,2,3",
16*18054d02SAlexander Motin        "EventCode": "0xB7",
17*18054d02SAlexander Motin        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
18*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
19*18054d02SAlexander Motin        "MSRValue": "0x10002",
20*18054d02SAlexander Motin        "SampleAfterValue": "100003",
21*18054d02SAlexander Motin        "UMask": "0x1",
22*18054d02SAlexander Motin        "Unit": "cpu_atom"
23*18054d02SAlexander Motin    },
24*18054d02SAlexander Motin    {
25*18054d02SAlexander Motin        "BriefDescription": "Counts streaming stores that have any type of response.",
26*18054d02SAlexander Motin        "Counter": "0,1,2,3",
27*18054d02SAlexander Motin        "EventCode": "0xB7",
28*18054d02SAlexander Motin        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
29*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
30*18054d02SAlexander Motin        "MSRValue": "0x10800",
31*18054d02SAlexander Motin        "SampleAfterValue": "100003",
32*18054d02SAlexander Motin        "UMask": "0x1",
33*18054d02SAlexander Motin        "Unit": "cpu_atom"
34*18054d02SAlexander Motin    },
35*18054d02SAlexander Motin    {
36*18054d02SAlexander Motin        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
37*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
38*18054d02SAlexander Motin        "Counter": "0,1,2,3,4,5,6,7",
39*18054d02SAlexander Motin        "EventCode": "0xc1",
40*18054d02SAlexander Motin        "EventName": "ASSISTS.ANY",
41*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3,4,5,6,7",
42*18054d02SAlexander Motin        "SampleAfterValue": "100003",
43*18054d02SAlexander Motin        "UMask": "0x1f",
44*18054d02SAlexander Motin        "Unit": "cpu_core"
45*18054d02SAlexander Motin    },
46*18054d02SAlexander Motin    {
47*18054d02SAlexander Motin        "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",
48*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
49*18054d02SAlexander Motin        "Counter": "0,1,2,3,4,5,6,7",
50*18054d02SAlexander Motin        "EventCode": "0xc1",
51*18054d02SAlexander Motin        "EventName": "ASSISTS.HARDWARE",
52*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3,4,5,6,7",
53*18054d02SAlexander Motin        "SampleAfterValue": "100003",
54*18054d02SAlexander Motin        "UMask": "0x4",
55*18054d02SAlexander Motin        "Unit": "cpu_core"
56*18054d02SAlexander Motin    },
57*18054d02SAlexander Motin    {
58*18054d02SAlexander Motin        "BriefDescription": "TBD",
59*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
60*18054d02SAlexander Motin        "Counter": "0,1,2,3,4,5,6,7",
61*18054d02SAlexander Motin        "EventCode": "0xc1",
62*18054d02SAlexander Motin        "EventName": "ASSISTS.PAGE_FAULT",
63*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3,4,5,6,7",
64*18054d02SAlexander Motin        "SampleAfterValue": "1000003",
65*18054d02SAlexander Motin        "UMask": "0x8",
66*18054d02SAlexander Motin        "Unit": "cpu_core"
67*18054d02SAlexander Motin    },
68*18054d02SAlexander Motin    {
69*18054d02SAlexander Motin        "BriefDescription": "TBD",
70*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
71*18054d02SAlexander Motin        "Counter": "0,1,2,3",
72*18054d02SAlexander Motin        "EventCode": "0x28",
73*18054d02SAlexander Motin        "EventName": "CORE_POWER.LICENSE_1",
74*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3",
75*18054d02SAlexander Motin        "SampleAfterValue": "200003",
76*18054d02SAlexander Motin        "UMask": "0x2",
77*18054d02SAlexander Motin        "Unit": "cpu_core"
78*18054d02SAlexander Motin    },
79*18054d02SAlexander Motin    {
80*18054d02SAlexander Motin        "BriefDescription": "TBD",
81*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
82*18054d02SAlexander Motin        "Counter": "0,1,2,3",
83*18054d02SAlexander Motin        "EventCode": "0x28",
84*18054d02SAlexander Motin        "EventName": "CORE_POWER.LICENSE_2",
85*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3",
86*18054d02SAlexander Motin        "SampleAfterValue": "200003",
87*18054d02SAlexander Motin        "UMask": "0x4",
88*18054d02SAlexander Motin        "Unit": "cpu_core"
89*18054d02SAlexander Motin    },
90*18054d02SAlexander Motin    {
91*18054d02SAlexander Motin        "BriefDescription": "TBD",
92*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
93*18054d02SAlexander Motin        "Counter": "0,1,2,3",
94*18054d02SAlexander Motin        "EventCode": "0x28",
95*18054d02SAlexander Motin        "EventName": "CORE_POWER.LICENSE_3",
96*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3",
97*18054d02SAlexander Motin        "SampleAfterValue": "200003",
98*18054d02SAlexander Motin        "UMask": "0x8",
99*18054d02SAlexander Motin        "Unit": "cpu_core"
100*18054d02SAlexander Motin    },
101*18054d02SAlexander Motin    {
102*18054d02SAlexander Motin        "BriefDescription": "Counts demand data reads that have any type of response.",
103*18054d02SAlexander Motin        "Counter": "0,1,2,3",
104*18054d02SAlexander Motin        "EventCode": "0x2A,0x2B",
105*18054d02SAlexander Motin        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
106*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
107*18054d02SAlexander Motin        "MSRValue": "0x10001",
108*18054d02SAlexander Motin        "SampleAfterValue": "100003",
109*18054d02SAlexander Motin        "UMask": "0x1",
110*18054d02SAlexander Motin        "Unit": "cpu_core"
111*18054d02SAlexander Motin    },
112*18054d02SAlexander Motin    {
113*18054d02SAlexander Motin        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
114*18054d02SAlexander Motin        "Counter": "0,1,2,3",
115*18054d02SAlexander Motin        "EventCode": "0x2A,0x2B",
116*18054d02SAlexander Motin        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
117*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
118*18054d02SAlexander Motin        "MSRValue": "0x10002",
119*18054d02SAlexander Motin        "SampleAfterValue": "100003",
120*18054d02SAlexander Motin        "UMask": "0x1",
121*18054d02SAlexander Motin        "Unit": "cpu_core"
122*18054d02SAlexander Motin    },
123*18054d02SAlexander Motin    {
124*18054d02SAlexander Motin        "BriefDescription": "Counts streaming stores that have any type of response.",
125*18054d02SAlexander Motin        "Counter": "0,1,2,3",
126*18054d02SAlexander Motin        "EventCode": "0x2A,0x2B",
127*18054d02SAlexander Motin        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
128*18054d02SAlexander Motin        "MSRIndex": "0x1a6,0x1a7",
129*18054d02SAlexander Motin        "MSRValue": "0x10800",
130*18054d02SAlexander Motin        "SampleAfterValue": "100003",
131*18054d02SAlexander Motin        "UMask": "0x1",
132*18054d02SAlexander Motin        "Unit": "cpu_core"
133*18054d02SAlexander Motin    },
134*18054d02SAlexander Motin    {
135*18054d02SAlexander Motin        "BriefDescription": "TBD",
136*18054d02SAlexander Motin        "CollectPEBSRecord": "2",
137*18054d02SAlexander Motin        "Counter": "0,1,2,3",
138*18054d02SAlexander Motin        "CounterMask": "1",
139*18054d02SAlexander Motin        "EventCode": "0x2d",
140*18054d02SAlexander Motin        "EventName": "XQ.FULL_CYCLES",
141*18054d02SAlexander Motin        "PEBScounters": "0,1,2,3",
142*18054d02SAlexander Motin        "SampleAfterValue": "1000003",
143*18054d02SAlexander Motin        "UMask": "0x1",
144*18054d02SAlexander Motin        "Unit": "cpu_core"
145*18054d02SAlexander Motin    }
146*18054d02SAlexander Motin]