xref: /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json (revision 9d97138e2d138bcd03dc28f45e78b13c536bed84) 
1[
2    {
3        "ArchStdEvent": "L1I_CACHE_REFILL"
4    },
5    {
6        "ArchStdEvent": "L1I_TLB_REFILL"
7    },
8    {
9        "ArchStdEvent": "L1D_CACHE_REFILL"
10    },
11    {
12        "ArchStdEvent": "L1D_CACHE"
13    },
14    {
15        "ArchStdEvent": "L1D_TLB_REFILL"
16    },
17    {
18        "ArchStdEvent": "L1I_CACHE"
19    },
20    {
21        "ArchStdEvent": "L1D_CACHE_WB"
22    },
23    {
24        "ArchStdEvent": "L2D_CACHE"
25    },
26    {
27        "ArchStdEvent": "L2D_CACHE_REFILL"
28    },
29    {
30        "ArchStdEvent": "L2D_CACHE_WB"
31    },
32    {
33        "ArchStdEvent": "L1D_CACHE_RD"
34    },
35    {
36        "ArchStdEvent": "L1D_CACHE_WR"
37    },
38    {
39        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
40    },
41    {
42        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
43    },
44    {
45        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
46    },
47    {
48        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
49    },
50    {
51        "ArchStdEvent": "L1D_CACHE_INVAL"
52    },
53    {
54        "ArchStdEvent": "L1D_TLB_REFILL_RD"
55    },
56    {
57        "ArchStdEvent": "L1D_TLB_REFILL_WR"
58    },
59    {
60        "ArchStdEvent": "L2D_CACHE_RD"
61    },
62    {
63        "ArchStdEvent": "L2D_CACHE_WR"
64    },
65    {
66        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
67    },
68    {
69        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
70    },
71    {
72        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
73    },
74    {
75        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
76    },
77    {
78        "ArchStdEvent": "L2D_CACHE_INVAL"
79    }
80]
81