1.\" Copyright (c) 2010 Fabien Thomas. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd February 25, 2012 25.Dt PMC.WESTMERE 3 26.Os 27.Sh NAME 28.Nm pmc.westmere 29.Nd measurement events for 30.Tn Intel 31.Tn Westmere 32family CPUs 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn Intel 39.Tn "Westmere" 40CPUs contain PMCs conforming to version 2 of the 41.Tn Intel 42performance measurement architecture. 43These CPUs may contain up to three classes of PMCs: 44.Bl -tag -width "Li PMC_CLASS_IAP" 45.It Li PMC_CLASS_IAF 46Fixed-function counters that count only one hardware event per counter. 47.It Li PMC_CLASS_IAP 48Programmable counters that may be configured to count one of a defined 49set of hardware events. 50.El 51.Pp 52The number of PMCs available in each class and their widths need to be 53determined at run time by calling 54.Xr pmc_cpuinfo 3 . 55.Pp 56Intel Westmere PMCs are documented in 57.Rs 58.%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual" 59.%T "Volume 3B: System Programming Guide, Part 2" 60.%N "Order Number: 253669-033US" 61.%D December 2009 62.%Q "Intel Corporation" 63.Re 64.Ss WESTMERE FIXED FUNCTION PMCS 65These PMCs and their supported events are documented in 66.Xr pmc.iaf 3 . 67.Ss WESTMERE PROGRAMMABLE PMCS 68The programmable PMCs support the following capabilities: 69.Bl -column "PMC_CAP_INTERRUPT" "Support" 70.It Em Capability Ta Em Support 71.It PMC_CAP_CASCADE Ta \&No 72.It PMC_CAP_EDGE Ta Yes 73.It PMC_CAP_INTERRUPT Ta Yes 74.It PMC_CAP_INVERT Ta Yes 75.It PMC_CAP_READ Ta Yes 76.It PMC_CAP_PRECISE Ta \&No 77.It PMC_CAP_SYSTEM Ta Yes 78.It PMC_CAP_TAGGING Ta \&No 79.It PMC_CAP_THRESHOLD Ta Yes 80.It PMC_CAP_USER Ta Yes 81.It PMC_CAP_WRITE Ta Yes 82.El 83.Ss Event Qualifiers 84Event specifiers for these PMCs support the following common 85qualifiers: 86.Bl -tag -width indent 87.It Li rsp= Ns Ar value 88Configure the Off-core Response bits. 89.Bl -tag -width indent 90.It Li DMND_DATA_RD 91Counts the number of demand and DCU prefetch data reads of full 92and partial cachelines as well as demand data page table entry 93cacheline reads. 94Does not count L2 data read prefetches or 95instruction fetches. 96.It Li DMND_RFO 97Counts the number of demand and DCU prefetch reads for ownership 98(RFO) requests generated by a write to data cacheline. 99Does not count L2 RFO. 100.It Li DMND_IFETCH 101Counts the number of demand and DCU prefetch instruction cacheline 102reads. 103Does not count L2 code read prefetches. 104WB 105Counts the number of writeback (modified to exclusive) transactions. 106.It Li PF_DATA_RD 107Counts the number of data cacheline reads generated by L2 prefetchers. 108.It Li PF_RFO 109Counts the number of RFO requests generated by L2 prefetchers. 110.It Li PF_IFETCH 111Counts the number of code reads generated by L2 prefetchers. 112.It Li OTHER 113Counts one of the following transaction types, including L3 invalidate, 114I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, 115lock, unlock, split lock. 116.It Li UNCORE_HIT 117L3 Hit: local or remote home requests that hit L3 cache in the uncore 118with no coherency actions required (snooping). 119.It Li OTHER_CORE_HIT_SNP 120L3 Hit: local or remote home requests that hit L3 cache in the uncore 121and was serviced by another core with a cross core snoop where no modified 122copies were found (clean). 123.It Li OTHER_CORE_HITM 124L3 Hit: local or remote home requests that hit L3 cache in the uncore 125and was serviced by another core with a cross core snoop where modified 126copies were found (HITM). 127.It Li REMOTE_CACHE_FWD 128L3 Miss: local homed requests that missed the L3 cache and was serviced 129by forwarded data following a cross package snoop where no modified 130copies found. (Remote home requests are not counted) 131.It Li REMOTE_DRAM 132L3 Miss: remote home requests that missed the L3 cache and were serviced 133by remote DRAM. 134.It Li LOCAL_DRAM 135L3 Miss: local home requests that missed the L3 cache and were serviced 136by local DRAM. 137.It Li NON_DRAM 138Non-DRAM requests that were serviced by IOH. 139.El 140.It Li cmask= Ns Ar value 141Configure the PMC to increment only if the number of configured 142events measured in a cycle is greater than or equal to 143.Ar value . 144.It Li edge 145Configure the PMC to count the number of de-asserted to asserted 146transitions of the conditions expressed by the other qualifiers. 147If specified, the counter will increment only once whenever a 148condition becomes true, irrespective of the number of clocks during 149which the condition remains true. 150.It Li inv 151Invert the sense of comparison when the 152.Dq Li cmask 153qualifier is present, making the counter increment when the number of 154events per cycle is less than the value specified by the 155.Dq Li cmask 156qualifier. 157.It Li os 158Configure the PMC to count events happening at processor privilege 159level 0. 160.It Li usr 161Configure the PMC to count events occurring at privilege levels 1, 2 162or 3. 163.El 164.Pp 165If neither of the 166.Dq Li os 167or 168.Dq Li usr 169qualifiers are specified, the default is to enable both. 170.Ss Event Specifiers (Programmable PMCs) 171Westmere programmable PMCs support the following events: 172.Bl -tag -width indent 173.It Li LOAD_BLOCK.OVERLAP_STORE 174.Pq Event 03H , Umask 02H 175Loads that partially overlap an earlier store 176.It Li SB_DRAIN.ANY 177.Pq Event 04H , Umask 07H 178All Store buffer stall cycles 179.It Li MISALIGN_MEMORY.STORE 180.Pq Event 05H , Umask 02H 181All store referenced with misaligned address 182.It Li STORE_BLOCKS.AT_RET 183.Pq Event 06H , Umask 04H 184Counts number of loads delayed with at-Retirement block code. 185The following 186loads need to be executed at retirement and wait for all senior stores on 187the same thread to be drained: load splitting across 4K boundary (page 188split), load accessing uncacheable (UC or USWC) memory, load lock, and load 189with page table in UC or USWC memory region. 190.It Li STORE_BLOCKS.L1D_BLOCK 191.Pq Event 06H , Umask 08H 192Cacheable loads delayed with L1D block code 193.It Li PARTIAL_ADDRESS_ALIAS 194.Pq Event 07H , Umask 01H 195Counts false dependency due to partial address aliasing 196.It Li DTLB_LOAD_MISSES.ANY 197.Pq Event 08H , Umask 01H 198Counts all load misses that cause a page walk 199.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 200.Pq Event 08H , Umask 02H 201Counts number of completed page walks due to load miss in the STLB. 202.It Li DTLB_LOAD_MISSES.WALK_CYCLES 203.Pq Event 08H , Umask 04H 204Cycles PMH is busy with a page walk due to a load miss in the STLB. 205.It Li DTLB_LOAD_MISSES.STLB_HIT 206.Pq Event 08H , Umask 10H 207Number of cache load STLB hits 208.It Li DTLB_LOAD_MISSES.PDE_MISS 209.Pq Event 08H , Umask 20H 210Number of DTLB cache load misses where the low part of the linear to 211physical address translation was missed. 212.It Li MEM_INST_RETIRED.LOADS 213.Pq Event 0BH , Umask 01H 214Counts the number of instructions with an architecturally-visible store 215retired on the architected path. 216In conjunction with ld_lat facility 217.It Li MEM_INST_RETIRED.STORES 218.Pq Event 0BH , Umask 02H 219Counts the number of instructions with an architecturally-visible store 220retired on the architected path. 221In conjunction with ld_lat facility 222.It Li MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD 223.Pq Event 0BH , Umask 10H 224Counts the number of instructions exceeding the latency specified with 225ld_lat facility. 226In conjunction with ld_lat facility 227.It Li MEM_STORE_RETIRED.DTLB_MISS 228.Pq Event 0CH , Umask 01H 229The event counts the number of retired stores that missed the DTLB. 230The DTLB miss is not counted if the store operation causes a fault. 231Does not counter prefetches. 232Counts both primary and secondary misses to the TLB 233.It Li UOPS_ISSUED.ANY 234.Pq Event 0EH , Umask 01H 235Counts the number of Uops issued by the Register Allocation Table to the 236Reservation Station, i.e. the UOPs issued from the front end to the back 237end. 238.It Li UOPS_ISSUED.STALLED_CYCLES 239.Pq Event 0EH , Umask 01H 240Counts the number of cycles no Uops issued by the Register Allocation Table 241to the Reservation Station, i.e. the UOPs issued from the front end to the 242back end. 243set invert=1, cmask = 1 244.It Li UOPS_ISSUED.FUSED 245.Pq Event 0EH , Umask 02H 246Counts the number of fused Uops that were issued from the Register 247Allocation Table to the Reservation Station. 248.It Li MEM_UNCORE_RETIRED.LOCAL_HITM 249.Pq Event 0FH , Umask 02H 250Load instructions retired that HIT modified data in sibling core (Precise 251Event) 252.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT 253.Pq Event 0FH , Umask 08H 254Load instructions retired local dram and remote cache HIT data sources 255(Precise Event) 256.It Li MEM_UNCORE_RETIRED.LOCAL_DRAM 257.Pq Event 0FH , Umask 10H 258Load instructions retired with a data source of local DRAM or locally homed 259remote cache HITM (Precise Event) 260.It Li MEM_UNCORE_RETIRED.REMOTE_DRAM 261.Pq Event 0FH , Umask 20H 262Load instructions retired remote DRAM and remote home-remote cache HITM 263(Precise Event) 264.It Li MEM_UNCORE_RETIRED.UNCACHEABLE 265.Pq Event 0FH , Umask 80H 266Load instructions retired I/O (Precise Event) 267.It Li FP_COMP_OPS_EXE.X87 268.Pq Event 10H , Umask 01H 269Counts the number of FP Computational Uops Executed. 270The number of FADD, 271FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer 272DIVs, and IDIVs. 273This event does not distinguish an FADD used in the middle 274of a transcendental flow from a separate FADD instruction. 275.It Li FP_COMP_OPS_EXE.MMX 276.Pq Event 10H , Umask 02H 277Counts number of MMX Uops executed. 278.It Li FP_COMP_OPS_EXE.SSE_FP 279.Pq Event 10H , Umask 04H 280Counts number of SSE and SSE2 FP uops executed. 281.It Li FP_COMP_OPS_EXE.SSE2_INTEGER 282.Pq Event 10H , Umask 08H 283Counts number of SSE2 integer uops executed. 284.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED 285.Pq Event 10H , Umask 10H 286Counts number of SSE FP packed uops executed. 287.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR 288.Pq Event 10H , Umask 20H 289Counts number of SSE FP scalar uops executed. 290.It Li FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION 291.Pq Event 10H , Umask 40H 292Counts number of SSE* FP single precision uops executed. 293.It Li FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION 294.Pq Event 10H , Umask 80H 295Counts number of SSE* FP double precision uops executed. 296.It Li SIMD_INT_128.PACKED_MPY 297.Pq Event 12H , Umask 01H 298Counts number of 128 bit SIMD integer multiply operations. 299.It Li SIMD_INT_128.PACKED_SHIFT 300.Pq Event 12H , Umask 02H 301Counts number of 128 bit SIMD integer shift operations. 302.It Li SIMD_INT_128.PACK 303.Pq Event 12H , Umask 04H 304Counts number of 128 bit SIMD integer pack operations. 305.It Li SIMD_INT_128.UNPACK 306.Pq Event 12H , Umask 08H 307Counts number of 128 bit SIMD integer unpack operations. 308.It Li SIMD_INT_128.PACKED_LOGICAL 309.Pq Event 12H , Umask 10H 310Counts number of 128 bit SIMD integer logical operations. 311.It Li SIMD_INT_128.PACKED_ARITH 312.Pq Event 12H , Umask 20H 313Counts number of 128 bit SIMD integer arithmetic operations. 314.It Li SIMD_INT_128.SHUFFLE_MOVE 315.Pq Event 12H , Umask 40H 316Counts number of 128 bit SIMD integer shuffle and move operations. 317.It Li LOAD_DISPATCH.RS 318.Pq Event 13H , Umask 01H 319Counts number of loads dispatched from the Reservation Station that bypass 320the Memory Order Buffer. 321.It Li LOAD_DISPATCH.RS_DELAYED 322.Pq Event 13H , Umask 02H 323Counts the number of delayed RS dispatches at the stage latch. 324If an RS dispatch can not bypass to LB, it has another chance to dispatch 325from the one-cycle delayed staging latch before it is written into the LB. 326.It Li LOAD_DISPATCH.MOB 327.Pq Event 13H , Umask 04H 328Counts the number of loads dispatched from the Reservation Station to the 329Memory Order Buffer. 330.It Li LOAD_DISPATCH.ANY 331.Pq Event 13H , Umask 07H 332Counts all loads dispatched from the Reservation Station. 333.It Li ARITH.CYCLES_DIV_BUSY 334.Pq Event 14H , Umask 01H 335Counts the number of cycles the divider is busy executing divide or square 336root operations. 337The divide can be integer, X87 or Streaming SIMD Extensions (SSE). 338The square root operation can be either X87 or SSE. 339Set 'edge =1, invert=1, cmask=1' to count the number of divides. 340Count may be incorrect When SMT is on 341.It Li ARITH.MUL 342.Pq Event 14H , Umask 02H 343Counts the number of multiply operations executed. 344This includes integer as 345well as floating point multiply operations but excludes DPPS mul and MPSAD. 346Count may be incorrect When SMT is on 347.It Li INST_QUEUE_WRITES 348.Pq Event 17H , Umask 01H 349Counts the number of instructions written into the instruction queue every 350cycle. 351.It Li INST_DECODED.DEC0 352.Pq Event 18H , Umask 01H 353Counts number of instructions that require decoder 0 to be decoded. 354Usually, this means that the instruction maps to more than 1 uop 355.It Li TWO_UOP_INSTS_DECODED 356.Pq Event 19H , Umask 01H 357An instruction that generates two uops was decoded 358.It Li INST_QUEUE_WRITE_CYCLES 359.Pq Event 1EH , Umask 01H 360This event counts the number of cycles during which instructions are written 361to the instruction queue. 362Dividing this counter by the number of 363instructions written to the instruction queue (INST_QUEUE_WRITES) yields the 364average number of instructions decoded each cycle. 365If this number is less 366than four and the pipe stalls, this indicates that the decoder is failing to 367decode enough instructions per cycle to sustain the 4-wide pipeline. 368If SSE* instructions that are 6 bytes or longer arrive one after another, 369then front end throughput may limit execution speed. 370In such case, 371.It Li LSD_OVERFLOW 372.Pq Event 20H , Umask 01H 373Number of loops that can not stream from the instruction queue. 374.It Li L2_RQSTS.LD_HIT 375.Pq Event 24H , Umask 01H 376Counts number of loads that hit the L2 cache. 377L2 loads include both L1D demand misses as well as L1D prefetches. 378L2 loads can be rejected for various reasons. 379Only non rejected loads are counted. 380.It Li L2_RQSTS.LD_MISS 381.Pq Event 24H , Umask 02H 382Counts the number of loads that miss the L2 cache. 383L2 loads include both L1D demand misses as well as L1D prefetches. 384.It Li L2_RQSTS.LOADS 385.Pq Event 24H , Umask 03H 386Counts all L2 load requests. 387L2 loads include both L1D demand misses as well as L1D prefetches. 388.It Li L2_RQSTS.RFO_HIT 389.Pq Event 24H , Umask 04H 390Counts the number of store RFO requests that hit the L2 cache. 391L2 RFO requests include both L1D demand RFO misses as well as L1D RFO 392prefetches. 393Count includes WC memory requests, where the data is not fetched but the 394permission to write the line is required. 395.It Li L2_RQSTS.RFO_MISS 396.Pq Event 24H , Umask 08H 397Counts the number of store RFO requests that miss the L2 cache. 398L2 RFO requests include both L1D demand RFO misses as well as L1D RFO 399prefetches. 400.It Li L2_RQSTS.RFOS 401.Pq Event 24H , Umask 0CH 402Counts all L2 store RFO requests. 403L2 RFO requests include both L1D demand 404RFO misses as well as L1D RFO prefetches. 405.It Li L2_RQSTS.IFETCH_HIT 406.Pq Event 24H , Umask 10H 407Counts number of instruction fetches that hit the L2 cache. 408L2 instruction fetches include both L1I demand misses as well as L1I 409instruction prefetches. 410.It Li L2_RQSTS.IFETCH_MISS 411.Pq Event 24H , Umask 20H 412Counts number of instruction fetches that miss the L2 cache. 413L2 instruction fetches include both L1I demand misses as well as L1I 414instruction prefetches. 415.It Li L2_RQSTS.IFETCHES 416.Pq Event 24H , Umask 30H 417Counts all instruction fetches. 418L2 instruction fetches include both L1I 419demand misses as well as L1I instruction prefetches. 420.It Li L2_RQSTS.PREFETCH_HIT 421.Pq Event 24H , Umask 40H 422Counts L2 prefetch hits for both code and data. 423.It Li L2_RQSTS.PREFETCH_MISS 424.Pq Event 24H , Umask 80H 425Counts L2 prefetch misses for both code and data. 426.It Li L2_RQSTS.PREFETCHES 427.Pq Event 24H , Umask C0H 428Counts all L2 prefetches for both code and data. 429.It Li L2_RQSTS.MISS 430.Pq Event 24H , Umask AAH 431Counts all L2 misses for both code and data. 432.It Li L2_RQSTS.REFERENCES 433.Pq Event 24H , Umask FFH 434Counts all L2 requests for both code and data. 435.It Li L2_DATA_RQSTS.DEMAND.I_STATE 436.Pq Event 26H , Umask 01H 437Counts number of L2 data demand loads where the cache line to be loaded is 438in the I (invalid) state, i.e. a cache miss. 439L2 demand loads are both L1D demand misses and L1D prefetches. 440.It Li L2_DATA_RQSTS.DEMAND.S_STATE 441.Pq Event 26H , Umask 02H 442Counts number of L2 data demand loads where the cache line to be loaded is 443in the S (shared) state. 444L2 demand loads are both L1D demand misses and L1D 445prefetches. 446.It Li L2_DATA_RQSTS.DEMAND.E_STATE 447.Pq Event 26H , Umask 04H 448Counts number of L2 data demand loads where the cache line to be loaded is 449in the E (exclusive) state. 450L2 demand loads are both L1D demand misses and 451L1D prefetches. 452.It Li L2_DATA_RQSTS.DEMAND.M_STATE 453.Pq Event 26H , Umask 08H 454Counts number of L2 data demand loads where the cache line to be loaded is 455in the M (modified) state. 456L2 demand loads are both L1D demand misses and 457L1D prefetches. 458.It Li L2_DATA_RQSTS.DEMAND.MESI 459.Pq Event 26H , Umask 0FH 460Counts all L2 data demand requests. 461L2 demand loads are both L1D demand 462misses and L1D prefetches. 463.It Li L2_DATA_RQSTS.PREFETCH.I_STATE 464.Pq Event 26H , Umask 10H 465Counts number of L2 prefetch data loads where the cache line to be loaded is 466in the I (invalid) state, i.e. a cache miss. 467.It Li L2_DATA_RQSTS.PREFETCH.S_STATE 468.Pq Event 26H , Umask 20H 469Counts number of L2 prefetch data loads where the cache line to be loaded is 470in the S (shared) state. 471A prefetch RFO will miss on an S state line, while 472a prefetch read will hit on an S state line. 473.It Li L2_DATA_RQSTS.PREFETCH.E_STATE 474.Pq Event 26H , Umask 40H 475Counts number of L2 prefetch data loads where the cache line to be loaded is 476in the E (exclusive) state. 477.It Li L2_DATA_RQSTS.PREFETCH.M_STATE 478.Pq Event 26H , Umask 80H 479Counts number of L2 prefetch data loads where the cache line to be loaded is 480in the M (modified) state. 481.It Li L2_DATA_RQSTS.PREFETCH.MESI 482.Pq Event 26H , Umask F0H 483Counts all L2 prefetch requests. 484.It Li L2_DATA_RQSTS.ANY 485.Pq Event 26H , Umask FFH 486Counts all L2 data requests. 487.It Li L2_WRITE.RFO.I_STATE 488.Pq Event 27H , Umask 01H 489Counts number of L2 demand store RFO requests where the cache line to be 490loaded is in the I (invalid) state, i.e, a cache miss. 491The L1D prefetcher 492does not issue a RFO prefetch. 493This is a demand RFO request 494.It Li L2_WRITE.RFO.S_STATE 495.Pq Event 27H , Umask 02H 496Counts number of L2 store RFO requests where the cache line to be loaded is 497in the S (shared) state. 498The L1D prefetcher does not issue a RFO prefetch. 499This is a demand RFO request. 500.It Li L2_WRITE.RFO.M_STATE 501.Pq Event 27H , Umask 08H 502Counts number of L2 store RFO requests where the cache line to be loaded is 503in the M (modified) state. 504The L1D prefetcher does not issue a RFO prefetch. 505This is a demand RFO request. 506.It Li L2_WRITE.RFO.HIT 507.Pq Event 27H , Umask 0EH 508Counts number of L2 store RFO requests where the cache line to be loaded is 509in either the S, E or M states. 510The L1D prefetcher does not issue a RFO 511prefetch. 512This is a demand RFO request 513.It Li L2_WRITE.RFO.MESI 514.Pq Event 27H , Umask 0FH 515Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO 516prefetch. 517This is a demand RFO request. 518.It Li L2_WRITE.LOCK.I_STATE 519.Pq Event 27H , Umask 10H 520Counts number of L2 demand lock RFO requests where the cache line to be 521loaded is in the I (invalid) state, i.e. a cache miss. 522.It Li L2_WRITE.LOCK.S_STATE 523.Pq Event 27H , Umask 20H 524Counts number of L2 lock RFO requests where the cache line to be loaded is 525in the S (shared) state. 526.It Li L2_WRITE.LOCK.E_STATE 527.Pq Event 27H , Umask 40H 528Counts number of L2 demand lock RFO requests where the cache line to be 529loaded is in the E (exclusive) state. 530.It Li L2_WRITE.LOCK.M_STATE 531.Pq Event 27H , Umask 80H 532Counts number of L2 demand lock RFO requests where the cache line to be 533loaded is in the M (modified) state. 534.It Li L2_WRITE.LOCK.HIT 535.Pq Event 27H , Umask E0H 536Counts number of L2 demand lock RFO requests where the cache line to be 537loaded is in either the S, E, or M state. 538.It Li L2_WRITE.LOCK.MESI 539.Pq Event 27H , Umask F0H 540Counts all L2 demand lock RFO requests. 541.It Li L1D_WB_L2.I_STATE 542.Pq Event 28H , Umask 01H 543Counts number of L1 writebacks to the L2 where the cache line to be written 544is in the I (invalid) state, i.e. a cache miss. 545.It Li L1D_WB_L2.S_STATE 546.Pq Event 28H , Umask 02H 547Counts number of L1 writebacks to the L2 where the cache line to be written 548is in the S state. 549.It Li L1D_WB_L2.E_STATE 550.Pq Event 28H , Umask 04H 551Counts number of L1 writebacks to the L2 where the cache line to be written 552is in the E (exclusive) state. 553.It Li L1D_WB_L2.M_STATE 554.Pq Event 28H , Umask 08H 555Counts number of L1 writebacks to the L2 where the cache line to be written 556is in the M (modified) state. 557.It Li L1D_WB_L2.MESI 558.Pq Event 28H , Umask 0FH 559Counts all L1 writebacks to the L2. 560.It Li L3_LAT_CACHE.REFERENCE 561.Pq Event 2EH , Umask 02H 562Counts uncore Last Level Cache references. 563Because cache hierarchy, cache 564sizes and other implementation-specific characteristics; value comparison to 565estimate performance differences is not recommended. 566See Table A-1. 567.It Li L3_LAT_CACHE.MISS 568.Pq Event 2EH , Umask 01H 569Counts uncore Last Level Cache misses. 570Because cache hierarchy, cache sizes 571and other implementation-specific characteristics; value comparison to 572estimate performance differences is not recommended. 573See Table A-1. 574.It Li CPU_CLK_UNHALTED.THREAD_P 575.Pq Event 3CH , Umask 00H 576Counts the number of thread cycles while the thread is not in a halt state. 577The thread enters the halt state when it is running the HLT instruction. 578The core frequency may change from time to time due to power or thermal 579throttling. 580see Table A-1 581.It Li CPU_CLK_UNHALTED.REF_P 582.Pq Event 3CH , Umask 01H 583Increments at the frequency of TSC when not halted. 584see Table A-1 585.It Li DTLB_MISSES.ANY 586.Pq Event 49H , Umask 01H 587Counts the number of misses in the STLB which causes a page walk. 588.It Li DTLB_MISSES.WALK_COMPLETED 589.Pq Event 49H , Umask 02H 590Counts number of misses in the STLB which resulted in a completed page walk. 591.It Li DTLB_MISSES.WALK_CYCLES 592.Pq Event 49H , Umask 04H 593Counts cycles of page walk due to misses in the STLB. 594.It Li DTLB_MISSES.STLB_HIT 595.Pq Event 49H , Umask 10H 596Counts the number of DTLB first level misses that hit in the second level 597TLB. 598This event is only relevant if the core contains multiple DTLB levels. 599.It Li DTLB_MISSES.LARGE_WALK_COMPLETED 600.Pq Event 49H , Umask 80H 601Counts number of completed large page walks due to misses in the STLB. 602.It Li LOAD_HIT_PRE 603.Pq Event 4CH , Umask 01H 604Counts load operations sent to the L1 data cache while a previous SSE 605prefetch instruction to the same cache line has started prefetching but has 606not yet finished. 607.It Li L1D_PREFETCH.REQUESTS 608.Pq Event 4EH , Umask 01H 609Counts number of hardware prefetch requests dispatched out of the prefetch 610FIFO. 611.It Li L1D_PREFETCH.MISS 612.Pq Event 4EH , Umask 02H 613Counts number of hardware prefetch requests that miss the L1D. 614There are two 615prefetchers in the L1D. 616A streamer, which predicts lines sequentially after 617this one should be fetched, and the IP prefetcher that remembers access 618patterns for the current instruction. 619The streamer prefetcher stops on an 620L1D hit, while the IP prefetcher does not. 621.It Li L1D_PREFETCH.TRIGGERS 622.Pq Event 4EH , Umask 04H 623Counts number of prefetch requests triggered by the Finite State Machine and 624pushed into the prefetch FIFO. 625Some of the prefetch requests are dropped due 626to overwrites or competition between the IP index prefetcher and streamer 627prefetcher. 628The prefetch FIFO contains 4 entries. 629.It Li EPT.WALK_CYCLES 630.Pq Event 4FH , Umask 10H 631Counts Extended Page walk cycles. 632.It Li L1D.REPL 633.Pq Event 51H , Umask 01H 634Counts the number of lines brought into the L1 data cache. 635Counter 0, 1 only. 636.It Li L1D.M_REPL 637.Pq Event 51H , Umask 02H 638Counts the number of modified lines brought into the L1 data cache. 639Counter 0, 1 only. 640.It Li L1D.M_EVICT 641.Pq Event 51H , Umask 04H 642Counts the number of modified lines evicted from the L1 data cache due to 643replacement. 644Counter 0, 1 only. 645.It Li L1D.M_SNOOP_EVICT 646.Pq Event 51H , Umask 08H 647Counts the number of modified lines evicted from the L1 data cache due to 648snoop HITM intervention. 649Counter 0, 1 only 650.It Li L1D_CACHE_PREFETCH_LOCK_FB_HIT 651.Pq Event 52H , Umask 01H 652Counts the number of cacheable load lock speculated instructions accepted 653into the fill buffer. 654.It Li L1D_CACHE_LOCK_FB_HIT 655.Pq Event 53H , Umask 01H 656Counts the number of cacheable load lock speculated or retired instructions 657accepted into the fill buffer. 658.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA 659.Pq Event 60H , Umask 01H 660Counts weighted cycles of offcore demand data read requests. 661Does not include L2 prefetch requests. 662Counter 0. 663.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE 664.Pq Event 60H , Umask 02H 665Counts weighted cycles of offcore demand code read requests. 666Does not include L2 prefetch requests. 667Counter 0. 668.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO 669.Pq Event 60H , Umask 04H 670Counts weighted cycles of offcore demand RFO requests. 671Does not include L2 prefetch requests. 672Counter 0. 673.It Li OFFCORE_REQUESTS_OUTSTANDING.ANY.READ 674.Pq Event 60H , Umask 08H 675Counts weighted cycles of offcore read requests of any kind. 676Include L2 prefetch requests. 677Counter 0. 678.It Li CACHE_LOCK_CYCLES.L1D_L2 679.Pq Event 63H , Umask 01H 680Cycle count during which the L1D and L2 are locked. 681A lock is asserted when 682there is a locked memory access, due to uncacheable memory, a locked 683operation that spans two cache lines, or a page walk from an uncacheable 684page table. 685Counter 0, 1 only. 686L1D and L2 locks have a very high performance penalty and 687it is highly recommended to avoid such accesses. 688.It Li CACHE_LOCK_CYCLES.L1D 689.Pq Event 63H , Umask 02H 690Counts the number of cycles that cacheline in the L1 data cache unit is 691locked. 692Counter 0, 1 only. 693.It Li IO_TRANSACTIONS 694.Pq Event 6CH , Umask 01H 695Counts the number of completed I/O transactions. 696.It Li L1I.HITS 697.Pq Event 80H , Umask 01H 698Counts all instruction fetches that hit the L1 instruction cache. 699.It Li L1I.MISSES 700.Pq Event 80H , Umask 02H 701Counts all instruction fetches that miss the L1I cache. 702This includes 703instruction cache misses, streaming buffer misses, victim cache misses and 704uncacheable fetches. 705An instruction fetch miss is counted only once and not 706once for every cycle it is outstanding. 707.It Li L1I.READS 708.Pq Event 80H , Umask 03H 709Counts all instruction fetches, including uncacheable fetches that bypass 710the L1I. 711.It Li L1I.CYCLES_STALLED 712.Pq Event 80H , Umask 04H 713Cycle counts for which an instruction fetch stalls due to a L1I cache miss, 714ITLB miss or ITLB fault. 715.It Li LARGE_ITLB.HIT 716.Pq Event 82H , Umask 01H 717Counts number of large ITLB hits. 718.It Li ITLB_MISSES.ANY 719.Pq Event 85H , Umask 01H 720Counts the number of misses in all levels of the ITLB which causes a page 721walk. 722.It Li ITLB_MISSES.WALK_COMPLETED 723.Pq Event 85H , Umask 02H 724Counts number of misses in all levels of the ITLB which resulted in a 725completed page walk. 726.It Li ITLB_MISSES.WALK_CYCLES 727.Pq Event 85H , Umask 04H 728Counts ITLB miss page walk cycles. 729.It Li ITLB_MISSES.LARGE_WALK_COMPLETED 730.Pq Event 85H , Umask 80H 731Counts number of completed large page walks due to misses in the STLB. 732.It Li ILD_STALL.LCP 733.Pq Event 87H , Umask 01H 734Cycles Instruction Length Decoder stalls due to length changing prefixes: 73566, 67 or REX.W (for EM64T) instructions which change the length of the 736decoded instruction. 737.It Li ILD_STALL.MRU 738.Pq Event 87H , Umask 02H 739Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) 740Most Recently Used (MRU) bypass. 741.It Li ILD_STALL.IQ_FULL 742.Pq Event 87H , Umask 04H 743Stall cycles due to a full instruction queue. 744.It Li ILD_STALL.REGEN 745.Pq Event 87H , Umask 08H 746Counts the number of regen stalls. 747.It Li ILD_STALL.ANY 748.Pq Event 87H , Umask 0FH 749Counts any cycles the Instruction Length Decoder is stalled. 750.It Li BR_INST_EXEC.COND 751.Pq Event 88H , Umask 01H 752Counts the number of conditional near branch instructions executed, but not 753necessarily retired. 754.It Li BR_INST_EXEC.DIRECT 755.Pq Event 88H , Umask 02H 756Counts all unconditional near branch instructions excluding calls and 757indirect branches. 758.It Li BR_INST_EXEC.INDIRECT_NON_CALL 759.Pq Event 88H , Umask 04H 760Counts the number of executed indirect near branch instructions that are not 761calls. 762.It Li BR_INST_EXEC.NON_CALLS 763.Pq Event 88H , Umask 07H 764Counts all non call near branch instructions executed, but not necessarily 765retired. 766.It Li BR_INST_EXEC.RETURN_NEAR 767.Pq Event 88H , Umask 08H 768Counts indirect near branches that have a return mnemonic. 769.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 770.Pq Event 88H , Umask 10H 771Counts unconditional near call branch instructions, excluding non call 772branch, executed. 773.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 774.Pq Event 88H , Umask 20H 775Counts indirect near calls, including both register and memory indirect, 776executed. 777.It Li BR_INST_EXEC.NEAR_CALLS 778.Pq Event 88H , Umask 30H 779Counts all near call branches executed, but not necessarily retired. 780.It Li BR_INST_EXEC.TAKEN 781.Pq Event 88H , Umask 40H 782Counts taken near branches executed, but not necessarily retired. 783.It Li BR_INST_EXEC.ANY 784.Pq Event 88H , Umask 7FH 785Counts all near executed branches (not necessarily retired). 786This includes only instructions and not micro-op branches. 787Frequent branching is not necessarily a major performance issue. 788However frequent branch mispredictions may be a problem. 789.It Li BR_MISP_EXEC.COND 790.Pq Event 89H , Umask 01H 791Counts the number of mispredicted conditional near branch instructions 792executed, but not necessarily retired. 793.It Li BR_MISP_EXEC.DIRECT 794.Pq Event 89H , Umask 02H 795Counts mispredicted macro unconditional near branch instructions, excluding 796calls and indirect branches (should always be 0). 797.It Li BR_MISP_EXEC.INDIRECT_NON_CALL 798.Pq Event 89H , Umask 04H 799Counts the number of executed mispredicted indirect near branch instructions 800that are not calls. 801.It Li BR_MISP_EXEC.NON_CALLS 802.Pq Event 89H , Umask 07H 803Counts mispredicted non call near branches executed, but not necessarily 804retired. 805.It Li BR_MISP_EXEC.RETURN_NEAR 806.Pq Event 89H , Umask 08H 807Counts mispredicted indirect branches that have a rear return mnemonic. 808.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 809.Pq Event 89H , Umask 10H 810Counts mispredicted non-indirect near calls executed, (should always be 0). 811.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 812.Pq Event 89H , Umask 20H 813Counts mispredicted indirect near calls executed, including both register 814and memory indirect. 815.It Li BR_MISP_EXEC.NEAR_CALLS 816.Pq Event 89H , Umask 30H 817Counts all mispredicted near call branches executed, but not necessarily 818retired. 819.It Li BR_MISP_EXEC.TAKEN 820.Pq Event 89H , Umask 40H 821Counts executed mispredicted near branches that are taken, but not 822necessarily retired. 823.It Li BR_MISP_EXEC.ANY 824.Pq Event 89H , Umask 7FH 825Counts the number of mispredicted near branch instructions that were 826executed, but not necessarily retired. 827.It Li RESOURCE_STALLS.ANY 828.Pq Event A2H , Umask 01H 829Counts the number of Allocator resource related stalls. 830Includes register renaming buffer entries, memory buffer entries. 831In addition to resource related stalls, this event counts some other events. 832Includes stalls arising 833during branch misprediction recovery, such as if retirement of the 834mispredicted branch is delayed and stalls arising while store buffer is 835draining from synchronizing operations. 836Does not include stalls due to SuperQ (off core) queue full, too many cache 837misses, etc. 838.It Li RESOURCE_STALLS.LOAD 839.Pq Event A2H , Umask 02H 840Counts the cycles of stall due to lack of load buffer for load operation. 841.It Li RESOURCE_STALLS.RS_FULL 842.Pq Event A2H , Umask 04H 843This event counts the number of cycles when the number of instructions in 844the pipeline waiting for execution reaches the limit the processor can 845handle. 846A high count of this event indicates that there are long latency 847operations in the pipe (possibly load and store operations that miss the L2 848cache, or instructions dependent upon instructions further down the pipeline 849that have yet to retire. 850When RS is full, new instructions can not enter the reservation station and 851start execution. 852.It Li RESOURCE_STALLS.STORE 853.Pq Event A2H , Umask 08H 854This event counts the number of cycles that a resource related stall will 855occur due to the number of store instructions reaching the limit of the 856pipeline, (i.e. all store buffers are used). 857The stall ends when a store 858instruction commits its data to the cache or memory. 859.It Li RESOURCE_STALLS.ROB_FULL 860.Pq Event A2H , Umask 10H 861Counts the cycles of stall due to re- order buffer full. 862.It Li RESOURCE_STALLS.FPCW 863.Pq Event A2H , Umask 20H 864Counts the number of cycles while execution was stalled due to writing the 865floating-point unit (FPU) control word. 866.It Li RESOURCE_STALLS.MXCSR 867.Pq Event A2H , Umask 40H 868Stalls due to the MXCSR register rename occurring to close to a previous 869MXCSR rename. 870The MXCSR provides control and status for the MMX registers. 871.It Li RESOURCE_STALLS.OTHER 872.Pq Event A2H , Umask 80H 873Counts the number of cycles while execution was stalled due to other 874resource issues. 875.It Li MACRO_INSTS.FUSIONS_DECODED 876.Pq Event A6H , Umask 01H 877Counts the number of instructions decoded that are macro-fused but not 878necessarily executed or retired. 879.It Li BACLEAR_FORCE_IQ 880.Pq Event A7H , Umask 01H 881Counts number of times a BACLEAR was forced by the Instruction Queue. 882The IQ is also responsible for providing conditional branch prediction 883direction based on a static scheme and dynamic data provided by the L2 884Branch Prediction Unit. 885If the conditional branch target is not found in the Target 886Array and the IQ predicts that the branch is taken, then the IQ will force 887the Branch Address Calculator to issue a BACLEAR. 888Each BACLEAR asserted by 889the BAC generates approximately an 8 cycle bubble in the instruction fetch 890pipeline. 891.It Li LSD.UOPS 892.Pq Event A8H , Umask 01H 893Counts the number of micro-ops delivered by loop stream detector 894Use cmask=1 and invert to count cycles 895.It Li ITLB_FLUSH 896.Pq Event AEH , Umask 01H 897Counts the number of ITLB flushes 898.It Li OFFCORE_REQUESTS.DEMAND.READ_DATA 899.Pq Event B0H , Umask 01H 900Counts number of offcore demand data read requests. 901Does not count L2 prefetch requests. 902.It Li OFFCORE_REQUESTS.DEMAND.READ_CODE 903.Pq Event B0H , Umask 02H 904Counts number of offcore demand code read requests. 905Does not count L2 prefetch requests. 906.It Li OFFCORE_REQUESTS.DEMAND.RFO 907.Pq Event B0H , Umask 04H 908Counts number of offcore demand RFO requests. 909Does not count L2 prefetch requests. 910.It Li OFFCORE_REQUESTS.ANY.READ 911.Pq Event B0H , Umask 08H 912Counts number of offcore read requests. 913Includes L2 prefetch requests. 914.It Li OFFCORE_REQUESTS.ANY.RFO 915.Pq Event 80H , Umask 10H 916Counts number of offcore RFO requests. 917Includes L2 prefetch requests. 918.It Li OFFCORE_REQUESTS.L1D_WRITEBACK 919.Pq Event B0H , Umask 40H 920Counts number of L1D writebacks to the uncore. 921.It Li OFFCORE_REQUESTS.ANY 922.Pq Event B0H , Umask 80H 923Counts all offcore requests. 924.It Li UOPS_EXECUTED.PORT0 925.Pq Event B1H , Umask 01H 926Counts number of Uops executed that were issued on port 0. 927Port 0 handles integer arithmetic, SIMD and FP add Uops. 928.It Li UOPS_EXECUTED.PORT1 929.Pq Event B1H , Umask 02H 930Counts number of Uops executed that were issued on port 1. 931Port 1 handles integer arithmetic, SIMD, integer shift, FP multiply and 932FP divide Uops. 933.It Li UOPS_EXECUTED.PORT2_CORE 934.Pq Event B1H , Umask 04H 935Counts number of Uops executed that were issued on port 2. 936Port 2 handles the load Uops. 937This is a core count only and can not be collected per 938thread. 939.It Li UOPS_EXECUTED.PORT3_CORE 940.Pq Event B1H , Umask 08H 941Counts number of Uops executed that were issued on port 3. 942Port 3 handles store Uops. 943This is a core count only and can not be collected per thread. 944.It Li UOPS_EXECUTED.PORT4_CORE 945.Pq Event B1H , Umask 10H 946Counts number of Uops executed that where issued on port 4. 947Port 4 handles the value to be stored for the store Uops issued on port 3. 948This is a core count only and can not be collected per thread. 949.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 950.Pq Event B1H , Umask 1FH 951Counts number of cycles there are one or more uops being executed and were 952issued on ports 0-4. 953This is a core count only and can not be collected per thread. 954.It Li UOPS_EXECUTED.PORT5 955.Pq Event B1H , Umask 20H 956Counts number of Uops executed that where issued on port 5. 957.It Li UOPS_EXECUTED.CORE_ACTIVE_CYCLES 958.Pq Event B1H , Umask 3FH 959Counts number of cycles there are one or more uops being executed on any 960ports. 961This is a core count only and can not be collected per thread. 962.It Li UOPS_EXECUTED.PORT015 963.Pq Event B1H , Umask 40H 964Counts number of Uops executed that where issued on port 0, 1, or 5. 965Use cmask=1, invert=1 to count stall cycles. 966.It Li UOPS_EXECUTED.PORT234 967.Pq Event B1H , Umask 80H 968Counts number of Uops executed that where issued on port 2, 3, or 4. 969.It Li OFFCORE_REQUESTS_SQ_FULL 970.Pq Event B2H , Umask 01H 971Counts number of cycles the SQ is full to handle off-core requests. 972.It Li SNOOPQ_REQUESTS_OUTSTANDING.DATA 973.Pq Event B3H , Umask 01H 974Counts weighted cycles of snoopq requests for data. 975Counter 0 only 976Use cmask=1 to count cycles not empty. 977.It Li SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE 978.Pq Event B3H , Umask 02H 979Counts weighted cycles of snoopq invalidate requests. 980Counter 0 only. 981Use cmask=1 to count cycles not empty. 982.It Li SNOOPQ_REQUESTS_OUTSTANDING.CODE 983.Pq Event B3H , Umask 04H 984Counts weighted cycles of snoopq requests for code. 985Counter 0 only. 986Use cmask=1 to count cycles not empty. 987.It Li SNOOPQ_REQUESTS.CODE 988.Pq Event B4H , Umask 01H 989Counts the number of snoop code requests. 990.It Li SNOOPQ_REQUESTS.DATA 991.Pq Event B4H , Umask 02H 992Counts the number of snoop data requests. 993.It Li SNOOPQ_REQUESTS.INVALIDATE 994.Pq Event B4H , Umask 04H 995Counts the number of snoop invalidate requests 996.It Li OFF_CORE_RESPONSE_0 997.Pq Event B7H , Umask 01H 998see Section 30.6.1.3, Off-core Response Performance Monitoring in the 999Processor Core. 1000Requires programming MSR 01A6H. 1001.It Li SNOOP_RESPONSE.HIT 1002.Pq Event B8H , Umask 01H 1003Counts HIT snoop response sent by this thread in response to a snoop 1004request. 1005.It Li SNOOP_RESPONSE.HITE 1006.Pq Event B8H , Umask 02H 1007Counts HIT E snoop response sent by this thread in response to a snoop 1008request. 1009.It Li SNOOP_RESPONSE.HITM 1010.Pq Event B8H , Umask 04H 1011Counts HIT M snoop response sent by this thread in response to a snoop 1012request. 1013.It Li OFF_CORE_RESPONSE_1 1014.Pq Event BBH , Umask 01H 1015see Section 30.6.1.3, Off-core Response Performance Monitoring in the 1016Processor Core. 1017Use MSR 01A7H. 1018.It Li INST_RETIRED.ANY_P 1019.Pq Event C0H , Umask 01H 1020See Table A-1 1021Notes: INST_RETIRED.ANY is counted by a designated fixed counter. 1022INST_RETIRED.ANY_P is counted by a programmable counter and is an 1023architectural performance event. 1024Event is supported if CPUID.A.EBX[1] = 0. 1025Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not 1026count as retired instructions. 1027.It Li INST_RETIRED.X87 1028.Pq Event C0H , Umask 02H 1029Counts the number of floating point computational operations retired 1030floating point computational operations executed by the assist handler and 1031sub-operations of complex floating point instructions like transcendental 1032instructions. 1033.It Li INST_RETIRED.MMX 1034.Pq Event C0H , Umask 04H 1035Counts the number of retired: MMX instructions. 1036.It Li UOPS_RETIRED.ANY 1037.Pq Event C2H , Umask 01H 1038Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, 1039others=1; maximum count of 8 per cycle). 1040Most instructions are composed of one or two micro-ops. 1041Some instructions are decoded into longer sequences 1042such as repeat instructions, floating point transcendental instructions, and 1043assists. 1044Use cmask=1 and invert to count active cycles or stalled cycles 1045.It Li UOPS_RETIRED.RETIRE_SLOTS 1046.Pq Event C2H , Umask 02H 1047Counts the number of retirement slots used each cycle 1048.It Li UOPS_RETIRED.MACRO_FUSED 1049.Pq Event C2H , Umask 04H 1050Counts number of macro-fused uops retired. 1051.It Li MACHINE_CLEARS.CYCLES 1052.Pq Event C3H , Umask 01H 1053Counts the cycles machine clear is asserted. 1054.It Li MACHINE_CLEARS.MEM_ORDER 1055.Pq Event C3H , Umask 02H 1056Counts the number of machine clears due to memory order conflicts. 1057.It Li MACHINE_CLEARS.SMC 1058.Pq Event C3H , Umask 04H 1059Counts the number of times that a program writes to a code section. 1060Self-modifying code causes a sever penalty in all Intel 64 and IA-32 1061processors. 1062The modified cache line is written back to the L2 and L3caches. 1063.It Li BR_INST_RETIRED.ANY_P 1064.Pq Event C4H , Umask 00H 1065See Table A-1. 1066.It Li BR_INST_RETIRED.CONDITIONAL 1067.Pq Event C4H , Umask 01H 1068Counts the number of conditional branch instructions retired. 1069.It Li BR_INST_RETIRED.NEAR_CALL 1070.Pq Event C4H , Umask 02H 1071Counts the number of direct & indirect near unconditional calls retired. 1072.It Li BR_INST_RETIRED.ALL_BRANCHES 1073.Pq Event C4H , Umask 04H 1074Counts the number of branch instructions retired. 1075.It Li BR_MISP_RETIRED.ANY_P 1076.Pq Event C5H , Umask 00H 1077See Table A-1. 1078.It Li BR_MISP_RETIRED.CONDITIONAL 1079.Pq Event C5H , Umask 01H 1080Counts mispredicted conditional retired calls. 1081.It Li BR_MISP_RETIRED.NEAR_CALL 1082.Pq Event C5H , Umask 02H 1083Counts mispredicted direct & indirect near unconditional retired calls. 1084.It Li BR_MISP_RETIRED.ALL_BRANCHES 1085.Pq Event C5H , Umask 04H 1086Counts all mispredicted retired calls. 1087.It Li SSEX_UOPS_RETIRED.PACKED_SINGLE 1088.Pq Event C7H , Umask 01H 1089Counts SIMD packed single-precision floating point Uops retired. 1090.It Li SSEX_UOPS_RETIRED.SCALAR_SINGLE 1091.Pq Event C7H , Umask 02H 1092Counts SIMD calar single-precision floating point Uops retired. 1093.It Li SSEX_UOPS_RETIRED.PACKED_DOUBLE 1094.Pq Event C7H , Umask 04H 1095Counts SIMD packed double- precision floating point Uops retired. 1096.It Li SSEX_UOPS_RETIRED.SCALAR_DOUBLE 1097.Pq Event C7H , Umask 08H 1098Counts SIMD scalar double-precision floating point Uops retired. 1099.It Li SSEX_UOPS_RETIRED.VECTOR_INTEGER 1100.Pq Event C7H , Umask 10H 1101Counts 128-bit SIMD vector integer Uops retired. 1102.It Li ITLB_MISS_RETIRED 1103.Pq Event C8H , Umask 20H 1104Counts the number of retired instructions that missed the ITLB when the 1105instruction was fetched. 1106.It Li MEM_LOAD_RETIRED.L1D_HIT 1107.Pq Event CBH , Umask 01H 1108Counts number of retired loads that hit the L1 data cache. 1109.It Li MEM_LOAD_RETIRED.L2_HIT 1110.Pq Event CBH , Umask 02H 1111Counts number of retired loads that hit the L2 data cache. 1112.It Li MEM_LOAD_RETIRED.L3_UNSHARED_HIT 1113.Pq Event CBH , Umask 04H 1114Counts number of retired loads that hit their own, unshared lines in the L3 1115cache. 1116.It Li MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM 1117.Pq Event CBH , Umask 08H 1118Counts number of retired loads that hit in a sibling core's L2 (on die 1119core). 1120Since the L3 is inclusive of all cores on the package, this is an L3 hit. 1121This counts both clean or modified hits. 1122.It Li MEM_LOAD_RETIRED.L3_MISS 1123.Pq Event CBH , Umask 10H 1124Counts number of retired loads that miss the L3 cache. 1125The load was satisfied by a remote socket, local memory or an IOH. 1126.It Li MEM_LOAD_RETIRED.HIT_LFB 1127.Pq Event CBH , Umask 40H 1128Counts number of retired loads that miss the L1D and the address is located 1129in an allocated line fill buffer and will soon be committed to cache. 1130This is counting secondary L1D misses. 1131.It Li MEM_LOAD_RETIRED.DTLB_MISS 1132.Pq Event CBH , Umask 80H 1133Counts the number of retired loads that missed the DTLB. 1134The DTLB miss is not counted if the load operation causes a fault. 1135This event counts loads from cacheable memory only. 1136The event does not count loads by software prefetches. 1137Counts both primary and secondary misses to the TLB. 1138.It Li FP_MMX_TRANS.TO_FP 1139.Pq Event CCH , Umask 01H 1140Counts the first floating-point instruction following any MMX instruction. 1141You can use this event to estimate the penalties for the transitions between 1142floating-point and MMX technology states. 1143.It Li FP_MMX_TRANS.TO_MMX 1144.Pq Event CCH , Umask 02H 1145Counts the first MMX instruction following a floating-point instruction. 1146You can use this event to estimate the penalties for the transitions between 1147floating-point and MMX technology states. 1148.It Li FP_MMX_TRANS.ANY 1149.Pq Event CCH , Umask 03H 1150Counts all transitions from floating point to MMX instructions and from MMX 1151instructions to floating point instructions. 1152You can use this event to estimate the penalties for the transitions between 1153floating-point and MMX technology states. 1154.It Li MACRO_INSTS.DECODED 1155.Pq Event D0H , Umask 01H 1156Counts the number of instructions decoded, (but not necessarily executed or 1157retired). 1158.It Li UOPS_DECODED.STALL_CYCLES 1159.Pq Event D1H , Umask 01H 1160Counts the cycles of decoder stalls. 1161.It Li UOPS_DECODED.MS 1162.Pq Event D1H , Umask 02H 1163Counts the number of Uops decoded by the Microcode Sequencer, MS. 1164The MS delivers uops when the instruction is more than 4 uops long or a 1165microcode assist is occurring. 1166.It Li UOPS_DECODED.ESP_FOLDING 1167.Pq Event D1H , Umask 04H 1168Counts number of stack pointer (ESP) instructions decoded: push , pop , call 1169, ret, etc. 1170ESP instructions do not generate a Uop to increment or decrement ESP. 1171Instead, they update an ESP_Offset register that keeps track of the 1172delta to the current value of the ESP register. 1173.It Li UOPS_DECODED.ESP_SYNC 1174.Pq Event D1H , Umask 08H 1175Counts number of stack pointer (ESP) sync operations where an ESP 1176instruction is corrected by adding the ESP offset register to the current 1177value of the ESP register. 1178.It Li RAT_STALLS.FLAGS 1179.Pq Event D2H , Umask 01H 1180Counts the number of cycles during which execution stalled due to several 1181reasons, one of which is a partial flag register stall. 1182A partial register 1183stall may occur when two conditions are met: 1) an instruction modifies 1184some, but not all, of the flags in the flag register and 2) the next 1185instruction, which depends on flags, depends on flags that were not modified 1186by this instruction. 1187.It Li RAT_STALLS.REGISTERS 1188.Pq Event D2H , Umask 02H 1189This event counts the number of cycles instruction execution latency became 1190longer than the defined latency because the instruction used a register that 1191was partially written by previous instruction. 1192.It Li RAT_STALLS.ROB_READ_PORT 1193.Pq Event D2H , Umask 04H 1194Counts the number of cycles when ROB read port stalls occurred, which did 1195not allow new micro-ops to enter the out-of-order pipeline. 1196Note that, at 1197this stage in the pipeline, additional stalls may occur at the same cycle 1198and prevent the stalled micro-ops from entering the pipe. 1199In such a case, 1200micro-ops retry entering the execution pipe in the next cycle and the 1201ROB-read port stall is counted again. 1202.It Li RAT_STALLS.SCOREBOARD 1203.Pq Event D2H , Umask 08H 1204Counts the cycles where we stall due to microarchitecturally required 1205serialization. 1206Microcode scoreboarding stalls. 1207.It Li RAT_STALLS.ANY 1208.Pq Event D2H , Umask 0FH 1209Counts all Register Allocation Table stall cycles due to: Cycles when ROB 1210read port stalls occurred, which did not allow new micro-ops to enter the 1211execution pipe. 1212Cycles when partial register stalls occurred Cycles when 1213flag stalls occurred Cycles floating-point unit (FPU) status word stalls 1214occurred. 1215To count each of these conditions separately use the events: 1216RAT_STALLS.ROB_READ_PORT, RAT_STALLS.PARTIAL, RAT_STALLS.FLAGS, and 1217RAT_STALLS.FPSW. 1218.It Li SEG_RENAME_STALLS 1219.Pq Event D4H , Umask 01H 1220Counts the number of stall cycles due to the lack of renaming resources for 1221the ES, DS, FS, and GS segment registers. 1222If a segment is renamed but not 1223retired and a second update to the same segment occurs, a stall occurs in 1224the front- end of the pipeline until the renamed segment retires. 1225.It Li ES_REG_RENAMES 1226.Pq Event D5H , Umask 01H 1227Counts the number of times the ES segment register is renamed. 1228.It Li UOP_UNFUSION 1229.Pq Event DBH , Umask 01H 1230Counts unfusion events due to floating point exception to a fused uop. 1231.It Li BR_INST_DECODED 1232.Pq Event E0H , Umask 01H 1233Counts the number of branch instructions decoded. 1234.It Li BPU_MISSED_CALL_RET 1235.Pq Event E5H , Umask 01H 1236Counts number of times the Branch Prediction Unit missed predicting a call 1237or return branch. 1238.It Li BACLEAR.CLEAR 1239.Pq Event E6H , Umask 01H 1240Counts the number of times the front end is resteered, mainly when the 1241Branch Prediction Unit cannot provide a correct prediction and this is 1242corrected by the Branch Address Calculator at the front end. 1243This can occur 1244if the code has many branches such that they cannot be consumed by the BPU. 1245Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble 1246in the instruction fetch pipeline. 1247The effect on total execution time depends on the surrounding code. 1248.It Li BACLEAR.BAD_TARGET 1249.Pq Event E6H , Umask 02H 1250Counts number of Branch Address Calculator clears (BACLEAR) asserted due to 1251conditional branch instructions in which there was a target hit but the 1252direction was wrong. 1253Each BACLEAR asserted by the BAC generates 1254approximately an 8 cycle bubble in the instruction fetch pipeline. 1255.It Li BPU_CLEARS.EARLY 1256.Pq Event E8H , Umask 01H 1257Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken 1258branch after incorrectly assuming that it was not taken. 1259The BPU clear leads to 2 cycle bubble in the Front End. 1260.It Li BPU_CLEARS.LATE 1261.Pq Event E8H , Umask 02H 1262Counts late Branch Prediction Unit clears due to Most Recently Used 1263conflicts. 1264The PBU clear leads to a 3 cycle bubble in the Front End. 1265.It Li THREAD_ACTIVE 1266.Pq Event ECH , Umask 01H 1267Counts cycles threads are active. 1268.It Li L2_TRANSACTIONS.LOAD 1269.Pq Event F0H , Umask 01H 1270Counts L2 load operations due to HW prefetch or demand loads. 1271.It Li L2_TRANSACTIONS.RFO 1272.Pq Event F0H , Umask 02H 1273Counts L2 RFO operations due to HW prefetch or demand RFOs. 1274.It Li L2_TRANSACTIONS.IFETCH 1275.Pq Event F0H , Umask 04H 1276Counts L2 instruction fetch operations due to HW prefetch or demand ifetch. 1277.It Li L2_TRANSACTIONS.PREFETCH 1278.Pq Event F0H , Umask 08H 1279Counts L2 prefetch operations. 1280.It Li L2_TRANSACTIONS.L1D_WB 1281.Pq Event F0H , Umask 10H 1282Counts L1D writeback operations to the L2. 1283.It Li L2_TRANSACTIONS.FILL 1284.Pq Event F0H , Umask 20H 1285Counts L2 cache line fill operations due to load, RFO, L1D writeback or 1286prefetch. 1287.It Li L2_TRANSACTIONS.WB 1288.Pq Event F0H , Umask 40H 1289Counts L2 writeback operations to the L3. 1290.It Li L2_TRANSACTIONS.ANY 1291.Pq Event F0H , Umask 80H 1292Counts all L2 cache operations. 1293.It Li L2_LINES_IN.S_STATE 1294.Pq Event F1H , Umask 02H 1295Counts the number of cache lines allocated in the L2 cache in the S (shared) 1296state. 1297.It Li L2_LINES_IN.E_STATE 1298.Pq Event F1H , Umask 04H 1299Counts the number of cache lines allocated in the L2 cache in the E 1300(exclusive) state. 1301.It Li L2_LINES_IN.ANY 1302.Pq Event F1H , Umask 07H 1303Counts the number of cache lines allocated in the L2 cache. 1304.It Li L2_LINES_OUT.DEMAND_CLEAN 1305.Pq Event F2H , Umask 01H 1306Counts L2 clean cache lines evicted by a demand request. 1307.It Li L2_LINES_OUT.DEMAND_DIRTY 1308.Pq Event F2H , Umask 02H 1309Counts L2 dirty (modified) cache lines evicted by a demand request. 1310.It Li L2_LINES_OUT.PREFETCH_CLEAN 1311.Pq Event F2H , Umask 04H 1312Counts L2 clean cache line evicted by a prefetch request. 1313.It Li L2_LINES_OUT.PREFETCH_DIRTY 1314.Pq Event F2H , Umask 08H 1315Counts L2 modified cache line evicted by a prefetch request. 1316.It Li L2_LINES_OUT.ANY 1317.Pq Event F2H , Umask 0FH 1318Counts all L2 cache lines evicted for any reason. 1319.It Li SQ_MISC.LRU_HINTS 1320.Pq Event F4H , Umask 04H 1321Counts number of Super Queue LRU hints sent to L3. 1322.It Li SQ_MISC.SPLIT_LOCK 1323.Pq Event F4H , Umask 10H 1324Counts the number of SQ lock splits across a cache line. 1325.It Li SQ_FULL_STALL_CYCLES 1326.Pq Event F6H , Umask 01H 1327Counts cycles the Super Queue is full. 1328Neither of the threads on this core will be able to access the uncore. 1329.It Li FP_ASSIST.ALL 1330.Pq Event F7H , Umask 01H 1331Counts the number of floating point operations executed that required 1332micro-code assist intervention. 1333Assists are required in the following cases: 1334SSE instructions, (Denormal input when the DAZ flag is off or Underflow 1335result when the FTZ flag is off): x87 instructions, (NaN or denormal are 1336loaded to a register or used as input from memory, Division by 0 or 1337Underflow output). 1338.It Li FP_ASSIST.OUTPUT 1339.Pq Event F7H , Umask 02H 1340Counts number of floating point micro-code assist when the output value 1341(destination register) is invalid. 1342.It Li FP_ASSIST.INPUT 1343.Pq Event F7H , Umask 04H 1344Counts number of floating point micro-code assist when the input value (one 1345of the source operands to an FP instruction) is invalid. 1346.It Li SIMD_INT_64.PACKED_MPY 1347.Pq Event FDH , Umask 01H 1348Counts number of SID integer 64 bit packed multiply operations. 1349.It Li SIMD_INT_64.PACKED_SHIFT 1350.Pq Event FDH , Umask 02H 1351Counts number of SID integer 64 bit packed shift operations. 1352.It Li SIMD_INT_64.PACK 1353.Pq Event FDH , Umask 04H 1354Counts number of SID integer 64 bit pack operations. 1355.It Li SIMD_INT_64.UNPACK 1356.Pq Event FDH , Umask 08H 1357Counts number of SID integer 64 bit unpack operations. 1358.It Li SIMD_INT_64.PACKED_LOGICAL 1359.Pq Event FDH , Umask 10H 1360Counts number of SID integer 64 bit logical operations. 1361.It Li SIMD_INT_64.PACKED_ARITH 1362.Pq Event FDH , Umask 20H 1363Counts number of SID integer 64 bit arithmetic operations. 1364.It Li SIMD_INT_64.SHUFFLE_MOVE 1365.Pq Event FDH , Umask 40H 1366Counts number of SID integer 64 bit shift or move operations. 1367.El 1368.Sh SEE ALSO 1369.Xr pmc 3 , 1370.Xr pmc.amd 3 , 1371.Xr pmc.atom 3 , 1372.Xr pmc.core 3 , 1373.Xr pmc.corei7 3 , 1374.Xr pmc.corei7uc 3 , 1375.Xr pmc.iaf 3 , 1376.Xr pmc.soft 3 , 1377.Xr pmc.tsc 3 , 1378.Xr pmc.ucf 3 , 1379.Xr pmc.westmereuc 3 , 1380.Xr pmc_cpuinfo 3 , 1381.Xr pmclog 3 , 1382.Xr hwpmc 4 1383.Sh HISTORY 1384The 1385.Nm pmc 1386library first appeared in 1387.Fx 6.0 . 1388.Sh AUTHORS 1389The 1390.Lb libpmc 1391library was written by 1392.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1393