1.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions 6.\" are met: 7.\" 1. Redistributions of source code must retain the above copyright 8.\" notice, this list of conditions and the following disclaimer. 9.\" 2. Redistributions in binary form must reproduce the above copyright 10.\" notice, this list of conditions and the following disclaimer in the 11.\" documentation and/or other materials provided with the distribution. 12.\" 13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23.\" SUCH DAMAGE. 24.\" 25.\" $FreeBSD$ 26.\" 27.Dd January 25, 2013 28.Dt PMC.IVYBRIDGEXEON 3 29.Os 30.Sh NAME 31.Nm pmc.ivybridgexeon 32.Nd measurement events for 33.Tn Intel 34.Tn Ivy Bridge Xeon 35family CPUs 36.Sh LIBRARY 37.Lb libpmc 38.Sh SYNOPSIS 39.In pmc.h 40.Sh DESCRIPTION 41.Tn Intel 42.Tn "Ivy Bridge Xeon" 43CPUs contain PMCs conforming to version 2 of the 44.Tn Intel 45performance measurement architecture. 46These CPUs may contain up to three classes of PMCs: 47.Bl -tag -width "Li PMC_CLASS_IAP" 48.It Li PMC_CLASS_IAF 49Fixed-function counters that count only one hardware event per counter. 50.It Li PMC_CLASS_IAP 51Programmable counters that may be configured to count one of a defined 52set of hardware events. 53.El 54.Pp 55The number of PMCs available in each class and their widths need to be 56determined at run time by calling 57.Xr pmc_cpuinfo 3 . 58.Pp 59Intel Ivy Bridge Xeon PMCs are documented in 60.Rs 61.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 62.%N "Order Number: 325462-045US" 63.%D January 2013 64.%Q "Intel Corporation" 65.Re 66.Ss IVYBRIDGE FIXED FUNCTION PMCS 67These PMCs and their supported events are documented in 68.Xr pmc.iaf 3 . 69.Ss IVYBRIDGE PROGRAMMABLE PMCS 70The programmable PMCs support the following capabilities: 71.Bl -column "PMC_CAP_INTERRUPT" "Support" 72.It Em Capability Ta Em Support 73.It PMC_CAP_CASCADE Ta \&No 74.It PMC_CAP_EDGE Ta Yes 75.It PMC_CAP_INTERRUPT Ta Yes 76.It PMC_CAP_INVERT Ta Yes 77.It PMC_CAP_READ Ta Yes 78.It PMC_CAP_PRECISE Ta \&No 79.It PMC_CAP_SYSTEM Ta Yes 80.It PMC_CAP_TAGGING Ta \&No 81.It PMC_CAP_THRESHOLD Ta Yes 82.It PMC_CAP_USER Ta Yes 83.It PMC_CAP_WRITE Ta Yes 84.El 85.Ss Event Qualifiers 86Event specifiers for these PMCs support the following common 87qualifiers: 88.Bl -tag -width indent 89.It Li rsp= Ns Ar value 90Configure the Off-core Response bits. 91.Bl -tag -width indent 92.It Li REQ_DMND_DATA_RD 93Counts the number of demand and DCU prefetch data reads of full and partial 94cachelines as well as demand data page table entry cacheline reads. 95Does not count L2 data read prefetches or instruction fetches. 96.It Li REQ_DMND_RFO 97Counts the number of demand and DCU prefetch reads for ownership (RFO) 98requests generated by a write to data cacheline. 99Does not count L2 RFO prefetches. 100.It Li REQ_DMND_IFETCH 101Counts the number of demand and DCU prefetch instruction cacheline reads. 102Does not count L2 code read prefetches. 103.It Li REQ_WB 104Counts the number of writeback (modified to exclusive) transactions. 105.It Li REQ_PF_DATA_RD 106Counts the number of data cacheline reads generated by L2 prefetchers. 107.It Li REQ_PF_RFO 108Counts the number of RFO requests generated by L2 prefetchers. 109.It Li REQ_PF_IFETCH 110Counts the number of code reads generated by L2 prefetchers. 111.It Li REQ_PF_LLC_DATA_RD 112L2 prefetcher to L3 for loads. 113.It Li REQ_PF_LLC_RFO 114RFO requests generated by L2 prefetcher 115.It Li REQ_PF_LLC_IFETCH 116L2 prefetcher to L3 for instruction fetches. 117.It Li REQ_BUS_LOCKS 118Bus lock and split lock requests. 119.It Li REQ_STRM_ST 120Streaming store requests. 121.It Li REQ_OTHER 122Any other request that crosses IDI, including I/O. 123.It Li RES_ANY 124Catch all value for any response types. 125.It Li RES_SUPPLIER_NO_SUPP 126No Supplier Information available. 127.It Li RES_SUPPLIER_LLC_HITM 128M-state initial lookup stat in L3. 129.It Li RES_SUPPLIER_LLC_HITE 130E-state. 131.It Li RES_SUPPLIER_LLC_HITS 132S-state. 133.It Li RES_SUPPLIER_LLC_HITF 134F-state. 135.It Li RES_SUPPLIER_LOCAL 136Local DRAM Controller. 137.It Li RES_SNOOP_SNP_NONE 138No details on snoop-related information. 139.It Li RES_SNOOP_SNP_NO_NEEDED 140No snoop was needed to satisfy the request. 141.It Li RES_SNOOP_SNP_MISS 142A snoop was needed and it missed all snooped caches: 143-For LLC Hit, ReslHitl was returned by all cores 144-For LLC Miss, Rspl was returned by all sockets and data was returned from 145DRAM. 146.It Li RES_SNOOP_HIT_NO_FWD 147A snoop was needed and it hits in at least one snooped cache. 148Hit denotes a cache-line was valid before snoop effect. 149This includes: 150-Snoop Hit w/ Invalidation (LLC Hit, RFO) 151-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 152-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 153In the LLC Miss case, data is returned from DRAM. 154.It Li RES_SNOOP_HIT_FWD 155A snoop was needed and data was forwarded from a remote socket. 156This includes: 157-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 158.It Li RES_SNOOP_HITM 159A snoop was needed and it HitM-ed in local or remote cache. 160HitM denotes a cache-line was in modified state before effect as a results of snoop. 161This includes: 162-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 163-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 164-Snoop MtoS (LLC Hit, IFetch/Data_RD). 165.It Li RES_NON_DRAM 166Target was non-DRAM system address. 167This includes MMIO transactions. 168.El 169.It Li cmask= Ns Ar value 170Configure the PMC to increment only if the number of configured 171events measured in a cycle is greater than or equal to 172.Ar value . 173.It Li edge 174Configure the PMC to count the number of de-asserted to asserted 175transitions of the conditions expressed by the other qualifiers. 176If specified, the counter will increment only once whenever a 177condition becomes true, irrespective of the number of clocks during 178which the condition remains true. 179.It Li inv 180Invert the sense of comparison when the 181.Dq Li cmask 182qualifier is present, making the counter increment when the number of 183events per cycle is less than the value specified by the 184.Dq Li cmask 185qualifier. 186.It Li os 187Configure the PMC to count events happening at processor privilege 188level 0. 189.It Li usr 190Configure the PMC to count events occurring at privilege levels 1, 2 191or 3. 192.El 193.Pp 194If neither of the 195.Dq Li os 196or 197.Dq Li usr 198qualifiers are specified, the default is to enable both. 199.Ss Event Specifiers (Programmable PMCs) 200Ivy Bridge programmable PMCs support the following events: 201.Bl -tag -width indent 202.It Li LD_BLOCKS.STORE_FORWARD 203.Pq Event 03H , Umask 02H 204loads blocked by overlapping with store buffer that cannot be forwarded . 205.It Li MISALIGN_MEM_REF.LOADS 206.Pq Event 05H , Umask 01H 207Speculative cache-line split load uops dispatched to L1D. 208.It Li MISALIGN_MEM_REF.STORES 209.Pq Event 05H , Umask 02H 210Speculative cache-line split Store- address uops dispatched to L1D. 211.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 212.Pq Event 07H , Umask 01H 213False dependencies in MOB due to partial compare on address. 214.It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK 215.Pq Event 08H , Umask 81H 216Misses in all TLB levels that cause a page walk of any page size from demand loads. 217.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED 218.Pq Event 08H , Umask 82H 219Misses in all TLB levels that caused page walk completed of any size by demand loads. 220.It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION 221.Pq Event 08H , Umask 84H 222Cycle PMH is busy with a walk due to demand loads. 223.It Li UOPS_ISSUED.ANY 224.Pq Event 0EH , Umask 01H 225Increments each cycle the # of Uops issued by the RAT to RS. 226Set Cmask = 1, Inv = 1to count stalled cycles. 227Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. 228.It Li UOPS_ISSUED.FLAGS_MERGE 229.Pq Event 0EH , Umask 10H 230Number of flags-merge uops allocated. 231Such uops adds delay. 232.It Li UOPS_ISSUED.SLOW_LEA 233.Pq Event 0EH , Umask 20H 234Number of slow LEA or similar uops allocated. 235Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. 236.It Li UOPS_ISSUED.SINGLE_MUL 237.Pq Event 0EH , Umask 40H 238Number of multiply packed/scalar single precision uops allocated. 239.It Li ARITH.FPU_DIV_ACTIVE 240.Pq Event 14H , Umask 01H 241Cycles that the divider is active, includes INT and FP. 242Set 'edge =1, cmask=1' to count the number of divides. 243.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 244.Pq Event 24H , Umask 01H 245Demand Data Read requests that hit L2 cache. 246.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 247.Pq Event 24H , Umask 03H 248Counts any demand and L1 HW prefetch data load requests to L2. 249.It Li L2_RQSTS.RFO_HITS 250.Pq Event 24H , Umask 04H 251Counts the number of store RFO requests that hit the L2 cache. 252.It Li L2_RQSTS.RFO_MISS 253.Pq Event 24H , Umask 08H 254Counts the number of store RFO requests that miss the L2 cache. 255.It Li L2_RQSTS.ALL_RFO 256.Pq Event 24H , Umask 0CH 257Counts all L2 store RFO requests. 258.It Li L2_RQSTS.CODE_RD_HIT 259.Pq Event 24H , Umask 10H 260Number of instruction fetches that hit the L2 cache. 261.It Li L2_RQSTS.CODE_RD_MISS 262.Pq Event 24H , Umask 20H 263Number of instruction fetches that missed the L2 cache. 264.It Li L2_RQSTS.ALL_CODE_RD 265.Pq Event 24H , Umask 30H 266Counts all L2 code requests. 267.It Li L2_RQSTS.PF_HIT 268.Pq Event 24H , Umask 40H 269Counts all L2 HW prefetcher requests that hit L2. 270.It Li L2_RQSTS.PF_MISS 271.Pq Event 24H , Umask 80H 272Counts all L2 HW prefetcher requests that missed L2. 273.It Li L2_RQSTS.ALL_PF 274.Pq Event 24H , Umask C0H 275Counts all L2 HW prefetcher requests. 276.It Li L2_STORE_LOCK_RQSTS.MISS 277.Pq Event 27H , Umask 01H 278RFOs that miss cache lines. 279.It Li L2_STORE_LOCK_RQSTS.HIT_M 280.Pq Event 27H , Umask 08H 281RFOs that hit cache lines in M state. 282.It Li L2_STORE_LOCK_RQSTS.ALL 283.Pq Event 27H , Umask 0FH 284RFOs that access cache lines in any state. 285.It Li L2_L1D_WB_RQSTS.MISS 286.Pq Event 28H , Umask 01H 287Not rejected writebacks that missed LLC. 288.It Li L2_L1D_WB_RQSTS.HIT_E 289.Pq Event 28H , Umask 04H 290Not rejected writebacks from L1D to L2 cache lines in E state. 291.It Li L2_L1D_WB_RQSTS.HIT_M 292.Pq Event 28H , Umask 08H 293Not rejected writebacks from L1D to L2 cache lines in M state. 294.It Li L2_L1D_WB_RQSTS.ALL 295.Pq Event 28H , Umask 0FH 296Not rejected writebacks from L1D to L2 cache lines in any state. 297.It Li LONGEST_LAT_CACHE.REFERENCE 298.Pq Event 2EH , Umask 4FH 299This event counts requests originating from the core that reference a cache 300line in the last level cache. 301.It Li LONGEST_LAT_CACHE.MISS 302.Pq Event 2EH , Umask 41H 303This event counts each cache miss condition for references to the last level 304cache. 305.It Li CPU_CLK_UNHALTED.THREAD_P 306.Pq Event 3CH , Umask 00H 307Counts the number of thread cycles while the thread is not in a halt state. 308The thread enters the halt state when it is running the HLT instruction. 309The core frequency may change from time to time due to power or thermal throttling. 310.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 311.Pq Event 3CH , Umask 01H 312Increments at the frequency of XCLK (100 MHz) when not halted. 313.It Li L1D_PEND_MISS.PENDING 314.Pq Event 48H , Umask 01H 315Increments the number of outstanding L1D misses every cycle. 316Set Cmaks = 1 and Edge =1 to count occurrences. 317Counter 2 only. 318Set Cmask = 1 to count cycles. 319.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 320.Pq Event 49H , Umask 01H 321Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). 322.It Li DTLB_STORE_MISSES.WALK_COMPLETED 323.Pq Event 49H , Umask 02H 324Miss in all TLB levels causes a page walk that completes of any page size 325(4K/2M/4M/1G). 326.It Li DTLB_STORE_MISSES.WALK_DURATION 327.Pq Event 49H , Umask 04H 328Cycles PMH is busy with this walk. 329.It Li DTLB_STORE_MISSES.STLB_HIT 330.Pq Event 49H , Umask 10H 331Store operations that miss the first TLB level but hit the second and do not 332cause page walks. 333.It Li LOAD_HIT_PRE.SW_PF 334.Pq Event 4CH , Umask 01H 335Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. 336.It Li LOAD_HIT_PRE.HW_PF 337.Pq Event 4CH , Umask 02H 338Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. 339.It Li L1D.REPLACEMENT 340.Pq Event 51H , Umask 01H 341Counts the number of lines brought into the L1 data cache. 342.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 343.Pq Event 58H , Umask 01H 344Number of integer Move Elimination candidate uops that were not eliminated. 345.It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED 346.Pq Event 58H , Umask 02H 347Number of SIMD Move Elimination candidate uops that were not eliminated. 348.It Li MOVE_ELIMINATION.INT_ELIMINATED 349.Pq Event 58H , Umask 04H 350Number of integer Move Elimination candidate uops that were eliminated. 351.It Li MOVE_ELIMINATION.SIMD_ELIMINATED 352.Pq Event 58H , Umask 08H 353Number of SIMD Move Elimination candidate uops that were eliminated. 354.It Li CPL_CYCLES.RING0 355.Pq Event 5CH , Umask 01H 356Unhalted core cycles when the thread is in ring 0. 357Use Edge to count transition. 358.It Li CPL_CYCLES.RING123 359.Pq Event 5CH , Umask 02H 360Unhalted core cycles when the thread is not in ring 0. 361.It Li RS_EVENTS.EMPTY_CYCLES 362.Pq Event 5EH , Umask 01H 363Cycles the RS is empty for the thread. 364.It Li DTLB_LOAD_MISSES.STLB_HIT 365.Pq Event 5FH , Umask 04H 366Counts load operations that missed 1st level DTLB but hit the 2nd level. 367.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 368.Pq Event 60H , Umask 01H 369Offcore outstanding Demand Data Read transactions in SQ to uncore. 370Set Cmask=1 to count cycles. 371.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD 372.Pq Event 60H , Umask 02H 373Offcore outstanding Demand Code Read transactions in SQ to uncore. 374Set Cmask=1 to count cycles. 375.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 376.Pq Event 60H , Umask 04H 377Offcore outstanding RFO store transactions in SQ to uncore. 378Set Cmask=1 to count cycles. 379.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 380.Pq Event 60H , Umask 08H 381Offcore outstanding cacheable data read transactions in SQ to uncore. 382Set Cmask=1 to count cycles. 383.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 384.Pq Event 63H , Umask 01H 385Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. 386.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 387.Pq Event 63H , Umask 02H 388Cycles in which the L1D is locked. 389.It Li IDQ.EMPTY 390.Pq Event 79H , Umask 02H 391Counts cycles the IDQ is empty. 392.It Li IDQ.MITE_UOPS 393.Pq Event 79H , Umask 04H 394Increment each cycle # of uops delivered to IDQ from MITE path. 395Can combine Umask 04H and 20H. 396Set Cmask = 1 to count cycles. 397.It Li IDQ.DSB_UOPS 398.Pq Event 79H , Umask 08H 399Increment each cycle. # of uops delivered to IDQ from DSB path. 400Can combine Umask 08H and 10H 401Set Cmask = 1 to count cycles. 402.It Li IDQ.MS_DSB_UOPS 403.Pq Event 79H , Umask 10H 404Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. 405Set Cmask = 1 to count cycles. 406Add Edge=1 to count # of delivery. 407Can combine Umask 04H, 08H. 408.It Li IDQ.MS_MITE_UOPS 409.Pq Event 79H , Umask 20H 410Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. 411Set Cmask = 1 to count cycles. 412Can combine Umask 04H, 08H. 413.It Li IDQ.MS_UOPS 414.Pq Event 79H , Umask 30H 415Increment each cycle # of uops delivered to IDQ from MS by either DSB or 416MITE. 417Set Cmask = 1 to count cycles. 418Can combine Umask 04H, 08H. 419.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 420.Pq Event 79H , Umask 18H 421Counts cycles DSB is delivered at least one uops. 422Set Cmask = 1. 423.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 424.Pq Event 79H , Umask 18H 425Counts cycles DSB is delivered four uops. 426Set Cmask = 4. 427.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 428.Pq Event 79H , Umask 24H 429Counts cycles MITE is delivered at least one uops. 430Set Cmask = 1. 431.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 432.Pq Event 79H , Umask 24H 433Counts cycles MITE is delivered four uops. 434Set Cmask = 4. 435.It Li IDQ.MITE_ALL_UOPS 436.Pq Event 79H , Umask 3CH 437# of uops delivered to IDQ from any path. 438.It Li ICACHE.MISSES 439.Pq Event 80H , Umask 02H 440Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. 441Includes UC accesses. 442.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 443.Pq Event 85H , Umask 01H 444Misses in all ITLB levels that cause page walks. 445.It Li ITLB_MISSES.WALK_COMPLETED 446.Pq Event 85H , Umask 02H 447Misses in all ITLB levels that cause completed page walks. 448.It Li ITLB_MISSES.WALK_DURATION 449.Pq Event 85H , Umask 04H 450Cycle PMH is busy with a walk. 451.It Li ITLB_MISSES.STLB_HIT 452.Pq Event 85H , Umask 10H 453Number of cache load STLB hits. 454No page walk. 455.It Li ILD_STALL.LCP 456.Pq Event 87H , Umask 01H 457Stalls caused by changing prefix length of the instruction. 458.It Li ILD_STALL.IQ_FULL 459.Pq Event 87H , Umask 04H 460Stall cycles due to IQ is full. 461.It Li BR_INST_EXEC.NONTAKEN_COND 462.Pq Event 88H , Umask 41H 463Count conditional near branch instructions that were executed (but not 464necessarily retired) and not taken. 465.It Li BR_INST_EXEC.TAKEN_COND 466.Pq Event 88H , Umask 81H 467Count conditional near branch instructions that were executed (but not 468necessarily retired) and taken. 469.It Li BR_INST_EXEC.DIRECT_JMP 470.Pq Event 88H , Umask 82H 471Count all unconditional near branch instructions excluding calls and 472indirect branches. 473.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 474.Pq Event 88H , Umask 84H 475Count executed indirect near branch instructions that are not calls nor 476returns. 477.It Li BR_INST_EXEC.RETURN_NEAR 478.Pq Event 88H , Umask 88H 479Count indirect near branches that have a return mnemonic. 480.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 481.Pq Event 88H , Umask 90H 482Count unconditional near call branch instructions, excluding non call 483branch, executed. 484.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 485.Pq Event 88H , Umask A0H 486Count indirect near calls, including both register and memory indirect, 487executed. 488.It Li BR_INST_EXEC.ALL_BRANCHES 489.Pq Event 88H , Umask FFH 490Counts all near executed branches (not necessarily retired). 491.It Li BR_MISP_EXEC.NONTAKEN_COND 492.Pq Event 89H , Umask 41H 493Count conditional near branch instructions mispredicted as nontaken. 494.It Li BR_MISP_EXEC.TAKEN_COND 495.Pq Event 89H , Umask 81H 496Count conditional near branch instructions mispredicted as taken. 497.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 498.Pq Event 89H , Umask 84H 499Count mispredicted indirect near branch instructions that are not calls 500nor returns. 501.It Li BR_MISP_EXEC.RETURN_NEAR 502.Pq Event 89H , Umask 88H 503Count mispredicted indirect near branches that have a return mnemonic. 504.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 505.Pq Event 89H , Umask 90H 506Count mispredicted unconditional near call branch instructions, excluding 507non call branch, executed. 508.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 509.Pq Event 89H , Umask A0H 510Count mispredicted indirect near calls, including both register and memory 511indirect, executed. 512.It Li BR_MISP_EXEC.ALL_BRANCHES 513.Pq Event 89H , Umask FFH 514Counts all mispredicted near executed branches (not necessarily retired). 515.It Li IDQ_UOPS_NOT_DELIVERED.CORE 516.Pq Event 9CH , Umask 01H 517Count number of non-delivered uops to RAT per thread. 518Use Cmask to qualify uop b/w. 519.It Li UOPS_DISPATCHED_PORT.PORT_0 520.Pq Event A1H , Umask 01H 521Cycles which a Uop is dispatched on port 0. 522.It Li UOPS_DISPATCHED_PORT.PORT_1 523.Pq Event A1H , Umask 02H 524Cycles which a Uop is dispatched on port 1. 525.It Li UOPS_DISPATCHED_PORT.PORT_2_LD 526.Pq Event A1H , Umask 04H 527Cycles which a load uop is dispatched on port 2. 528.It Li UOPS_DISPATCHED_PORT.PORT_2_STA 529.Pq Event A1H , Umask 08H 530Cycles which a store address uop is dispatched on port 2. 531.It Li UOPS_DISPATCHED_PORT.PORT_2 532.Pq Event A1H , Umask 0CH 533Cycles which a Uop is dispatched on port 2. 534.It Li UOPS_DISPATCHED_PORT.PORT_3_LD 535.Pq Event A1H , Umask 10H 536Cycles which a load uop is dispatched on port 3. 537.It Li UOPS_DISPATCHED_PORT.PORT_3_STA 538.Pq Event A1H , Umask 20H 539Cycles which a store address uop is dispatched on port 3. 540.It Li UOPS_DISPATCHED_PORT.PORT_3 541.Pq Event A1H , Umask 30H 542Cycles which a Uop is dispatched on port 3. 543.It Li UOPS_DISPATCHED_PORT.PORT_4 544.Pq Event A1H , Umask 40H 545Cycles which a Uop is dispatched on port 4. 546.It Li UOPS_DISPATCHED_PORT.PORT_5 547.Pq Event A1H , Umask 80H 548Cycles which a Uop is dispatched on port 5. 549.It Li RESOURCE_STALLS.ANY 550.Pq Event A2H , Umask 01H 551Cycles Allocation is stalled due to Resource Related reason. 552.It Li RESOURCE_STALLS.RS 553.Pq Event A2H , Umask 04H 554Cycles stalled due to no eligible RS entry available. 555.It Li RESOURCE_STALLS.SB 556.Pq Event A2H , Umask 08H 557Cycles stalled due to no store buffers available. (not including draining 558form sync). 559.It Li RESOURCE_STALLS.ROB 560.Pq Event A2H , Umask 10H 561Cycles stalled due to re-order buffer full. 562.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 563.Pq Event A3H , Umask 01H 564Cycles with pending L2 miss loads. 565Set AnyThread to count per core. 566.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 567.Pq Event A3H , Umask 02H 568Cycles with pending memory loads. 569Set AnyThread to count per core. 570.It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE 571.Pq Event A3H , Umask 04H 572Cycles of dispatch stalls. 573Set AnyThread to count per core. 574.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 575.Pq Event A3H , Umask 08H 576Cycles with pending L1 cache miss loads. 577Set AnyThread to count per core. 578.It Li DSB2MITE_SWITCHES.COUNT 579.Pq Event ABH , Umask 01H 580Number of DSB to MITE switches. 581.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES 582.Pq Event ABH , Umask 02H 583Cycles DSB to MITE switches caused delay. 584.It Li DSB_FILL.EXCEED_DSB_LINES 585.Pq Event ACH , Umask 08H 586DSB Fill encountered > 3 DSB lines. 587.It Li ITLB.ITLB_FLUSH 588.Pq Event AEH , Umask 01H 589Counts the number of ITLB flushes, includes 4k/2M/4M pages. 590.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 591.Pq Event B0H , Umask 01H 592Demand data read requests sent to uncore. 593.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 594.Pq Event B0H , Umask 02H 595Demand code read requests sent to uncore. 596.It Li OFFCORE_REQUESTS.DEMAND_RFO 597.Pq Event B0H , Umask 04H 598Demand RFO read requests sent to uncore, including regular RFOs, locks, 599ItoM. 600.It Li OFFCORE_REQUESTS.ALL_DATA_RD 601.Pq Event B0H , Umask 08H 602Data read requests sent to uncore (demand and prefetch). 603.It Li UOPS_EXECUTED.THREAD 604.Pq Event B1H , Umask 01H 605Counts total number of uops to be executed per-thread each cycle. 606Set Cmask = 1, INV =1 to count stall cycles. 607.It Li UOPS_EXECUTED.CORE 608.Pq Event B1H , Umask 02H 609Counts total number of uops to be executed per-core each cycle. 610Do not need to set ANY. 611.It Li OFF_CORE_RESPONSE_0 612.Pq Event B7H , Umask 01H 613Off-core Response Performance Monitoring. 614PMC0 only. 615Requires programming MSR 01A6H. 616.It Li OFF_CORE_RESPONSE_1 617.Pq Event BBH , Umask 01H 618Off-core Response Performance Monitoring. 619PMC3 only. 620Requires programming MSR 01A7H. 621.It Li TLB_FLUSH.DTLB_THREAD 622.Pq Event BDH , Umask 01H 623DTLB flush attempts of the thread- specific entries. 624.It Li TLB_FLUSH.STLB_ANY 625.Pq Event BDH , Umask 20H 626Count number of STLB flush attempts. 627.It Li INST_RETIRED.ANY_P 628.Pq Event C0H , Umask 00H 629Number of instructions at retirement. 630.It Li INST_RETIRED.ALL 631.Pq Event C0H , Umask 01H 632Precise instruction retired event with HW to reduce effect of PEBS shadow in 633IP distribution. 634PMC1 only. 635Must quiesce other PMCs. 636.It Li OTHER_ASSISTS.AVX_STORE 637.Pq Event C1H , Umask 08H 638Number of assists associated with 256-bit AVX store operations. 639.It Li OTHER_ASSISTS.AVX_TO_SSE 640.Pq Event C1H , Umask 10H 641Number of transitions from AVX- 256 to legacy SSE when penalty applicable. 642.It Li OTHER_ASSISTS.SSE_TO_AVX 643.Pq Event C1H , Umask 20H 644Number of transitions from SSE to AVX-256 when penalty applicable. 645.It Li UOPS_RETIRED.ALL 646.Pq Event C2H , Umask 01H 647Counts the number of micro-ops retired, Use cmask=1 and invert to count 648active cycles or stalled cycles. 649Supports PEBS, use Any=1 for core granular. 650.It Li UOPS_RETIRED.RETIRE_SLOTS 651.Pq Event C2H , Umask 02H 652Counts the number of retirement slots used each cycle. 653.It Li MACHINE_CLEARS.MEMORY_ORDERING 654.Pq Event C3H , Umask 02H 655Counts the number of machine clears due to memory order conflicts. 656.It Li MACHINE_CLEARS.SMC 657.Pq Event C3H , Umask 04H 658Number of self-modifying-code machine clears detected. 659.It Li MACHINE_CLEARS.MASKMOV 660.Pq Event C3H , Umask 20H 661Counts the number of executed AVX masked load operations that refer to an 662illegal address range with the mask bits set to 0. 663.It Li BR_INST_RETIRED.ALL_BRANCHES 664.Pq Event C4H , Umask 00H 665Branch instructions at retirement. 666.It Li BR_INST_RETIRED.CONDITIONAL 667.Pq Event C4H , Umask 01H 668Counts the number of conditional branch instructions retired. 669Supports PEBS. 670.It Li BR_INST_RETIRED.NEAR_CALL 671.Pq Event C4H , Umask 02H 672Direct and indirect near call instructions retired. 673.It Li BR_INST_RETIRED.ALL_BRANCHES 674.Pq Event C4H , Umask 04H 675Counts the number of branch instructions retired. 676.It Li BR_INST_RETIRED.NEAR_RETURN 677.Pq Event C4H , Umask 08H 678Counts the number of near return instructions retired. 679.It Li BR_INST_RETIRED.NOT_TAKEN 680.Pq Event C4H , Umask 10H 681Counts the number of not taken branch instructions retired. 682.It Li BR_INST_RETIRED.NEAR_TAKEN 683.Pq Event C4H , Umask 20H 684Number of near taken branches retired. 685.It Li BR_INST_RETIRED.FAR_BRANCH 686.Pq Event C4H , Umask 40H 687Number of far branches retired. 688.It Li BR_MISP_RETIRED.ALL_BRANCHES 689.Pq Event C5H , Umask 00H 690Mispredicted branch instructions at retirement. 691.It Li BR_MISP_RETIRED.CONDITIONAL 692.Pq Event C5H , Umask 01H 693Mispredicted conditional branch instructions retired. 694Supports PEBS. 695.It Li BR_MISP_RETIRED.NEAR_CALL 696.Pq Event C5H , Umask 02H 697Direct and indirect mispredicted near call instructions retired. 698.It Li BR_MISP_RETIRED.ALL_BRANCHES 699.Pq Event C5H , Umask 04H 700Mispredicted macro branch instructions retired. 701.It Li BR_MISP_RETIRED.NOT_TAKEN 702.Pq Event C5H , Umask 10H 703Mispredicted not taken branch instructions retired. 704.It Li BR_MISP_RETIRED.TAKEN 705.Pq Event C5H , Umask 20H 706Mispredicted taken branch instructions retired. 707.It Li FP_ASSIST.X87_OUTPUT 708.Pq Event CAH , Umask 02H 709Number of X87 FP assists due to Output values. 710.It Li FP_ASSIST.X87_INPUT 711.Pq Event CAH , Umask 04H 712Number of X87 FP assists due to input values. 713.It Li FP_ASSIST.SIMD_OUTPUT 714.Pq Event CAH , Umask 08H 715Number of SIMD FP assists due to Output values. 716.It Li FP_ASSIST.SIMD_INPUT 717.Pq Event CAH , Umask 10H 718Number of SIMD FP assists due to input values. 719.It Li FP_ASSIST.ANY 720.Pq Event CAH , Umask 1EH 721Cycles with any input/output SSE* or FP assists. 722.It Li ROB_MISC_EVENTS.LBR_INSERTS 723.Pq Event CCH , Umask 20H 724Count cases of saving new LBR records by hardware. 725.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 726.Pq Event CDH , Umask 01H 727Sample loads with specified latency threshold. 728PMC3 only. 729Specify threshold in MSR 0x3F6. 730.It Li MEM_TRANS_RETIRED.PRECISE_STORE 731.Pq Event CDH , Umask 02H 732Sample stores and collect precise store operation via PEBS record. 733PMC3 only. 734.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 735.Pq Event D0H , Umask 11H 736Count retired load uops that missed the STLB. 737.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 738.Pq Event D0H , Umask 12H 739Count retired store uops that missed the STLB. 740.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 741.Pq Event D0H , Umask 41H 742Count retired load uops that were split across a cache line. 743.It Li MEM_UOPS_RETIRED.SPLIT_STORES 744.Pq Event D0H , Umask 42H 745Count retired store uops that were split across a cache line. 746.It Li MEM_UOPS_RETIRED.ALL_LOADS 747.Pq Event D0H , Umask 81H 748Count all retired load uops. 749.It Li MEM_UOPS_RETIRED.ALL_STORES 750.Pq Event D0H , Umask 82H 751Count all retired store uops. 752.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 753.Pq Event D1H , Umask 01H 754Retired load uops with L1 cache hits as data sources. 755Supports PEBS. 756.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 757.Pq Event D1H , Umask 02H 758Retired load uops with L2 cache hits as data sources. 759.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 760.Pq Event D1H , Umask 04H 761Retired load uops whose data source was LLC hit with no snoop required. 762.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS 763.Pq Event D1H , Umask 20H 764Retired load uops whose data source is LLC miss. 765.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 766.Pq Event D1H , Umask 40H 767Retired load uops which data sources were load uops missed L1 but hit FB due 768to preceding miss to the same cache line with data not ready. 769.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 770.Pq Event D2H , Umask 01H 771Retired load uops which data sources were LLC hit and cross-core snoop 772missed in on-pkg core cache. 773Supports PEBS. 774.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 775.Pq Event D2H , Umask 02H 776Retired load uops which data sources were LLC and cross-core snoop hits in 777on-pkg core cache. 778Supports PEBS. 779.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 780.Pq Event D2H , Umask 04H 781Retired load uops which data sources were HitM responses from shared LLC. 782.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 783.Pq Event D2H , Umask 08H 784Retired load uops which data sources were hits in LLC without snoops 785required. 786.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 787.Pq Event D3H , Umask 01H 788Retired load uops which data sources missed LLC but serviced from local 789dram. 790Supports PEBS. 791.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM 792.Pq Event D3H , Umask 04H 793Retired load uops whose data source was remote DRAM. 794.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM 795.Pq Event D3H , Umask 10H 796Retired load uops whose data source was remote HITM. 797.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD 798.Pq Event D3H , Umask 20H 799Retired load uops whose data source was forwards from a remote cache. 800.It Li BACLEARS.ANY 801.Pq Event E6H , Umask 1FH 802Number of front end re-steers due to BPU misprediction. 803.It Li L2_TRANS.DEMAND_DATA_RD 804.Pq Event F0H , Umask 01H 805Demand Data Read requests that access L2 cache. 806.It Li L2_TRANS.RFO 807.Pq Event F0H , Umask 02H 808RFO requests that access L2 cache. 809.It Li L2_TRANS.CODE_RD 810.Pq Event F0H , Umask 04H 811L2 cache accesses when fetching instructions. 812.It Li L2_TRANS.ALL_PF 813.Pq Event F0H , Umask 08H 814Any MLC or LLC HW prefetch accessing L2, including rejects. 815.It Li L2_TRANS.L1D_WB 816.Pq Event F0H , Umask 10H 817L1D writebacks that access L2 cache. 818.It Li L2_TRANS.L2_FILL 819.Pq Event F0H , Umask 20H 820L2 fill requests that access L2 cache. 821.It Li L2_TRANS.L2_WB 822.Pq Event F0H , Umask 40H 823L2 writebacks that access L2 cache. 824.It Li L2_TRANS.ALL_REQUESTS 825.Pq Event F0H , Umask 80H 826Transactions accessing L2 pipe. 827.It Li L2_LINES_IN.I 828.Pq Event F1H , Umask 01H 829L2 cache lines in I state filling L2. 830Counting does not cover rejects. 831.It Li L2_LINES_IN.S 832.Pq Event F1H , Umask 02H 833L2 cache lines in S state filling L2. 834Counting does not cover rejects. 835.It Li L2_LINES_IN.E 836.Pq Event F1H , Umask 04H 837L2 cache lines in E state filling L2. 838Counting does not cover rejects. 839.It Li L2_LINES_IN.ALL 840.Pq Event F1H , Umask 07H 841L2 cache lines filling L2. 842Counting does not cover rejects. 843.It Li L2_LINES_OUT.DEMAND_CLEAN 844.Pq Event F2H , Umask 01H 845Clean L2 cache lines evicted by demand. 846.It Li L2_LINES_OUT.DEMAND_DIRTY 847.Pq Event F2H , Umask 02H 848Dirty L2 cache lines evicted by demand. 849.It Li L2_LINES_OUT.PF_CLEAN 850.Pq Event F2H , Umask 04H 851Clean L2 cache lines evicted by the MLC prefetcher. 852.It Li L2_LINES_OUT.PF_DIRTY 853.Pq Event F2H , Umask 08H 854Dirty L2 cache lines evicted by the MLC prefetcher. 855.It Li L2_LINES_OUT.DIRTY_ALL 856.Pq Event F2H , Umask 0AH 857Dirty L2 cache lines filling the L2. 858.El 859.Sh SEE ALSO 860.Xr pmc 3 , 861.Xr pmc.atom 3 , 862.Xr pmc.core 3 , 863.Xr pmc.corei7 3 , 864.Xr pmc.corei7uc 3 , 865.Xr pmc.iaf 3 , 866.Xr pmc.ivybridge 3 , 867.Xr pmc.k7 3 , 868.Xr pmc.k8 3 , 869.Xr pmc.sandybridge 3 , 870.Xr pmc.sandybridgeuc 3 , 871.Xr pmc.sandybridgexeon 3 , 872.Xr pmc.soft 3 , 873.Xr pmc.tsc 3 , 874.Xr pmc.ucf 3 , 875.Xr pmc.westmere 3 , 876.Xr pmc.westmereuc 3 , 877.Xr pmc_cpuinfo 3 , 878.Xr pmclog 3 , 879.Xr hwpmc 4 880.Sh HISTORY 881The 882.Nm pmc 883library first appeared in 884.Fx 6.0 . 885.Sh AUTHORS 886.An -nosplit 887The 888.Lb libpmc 889library was written by 890.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 891The support for the Ivy Bridge Xeon 892microarchitecture was written by 893.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com . 894