1.\" 2.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28.Dd November 21, 2014 29.Dt PMC.HASWELLXEON 3 30.Os 31.Sh NAME 32.Nm pmc.haswellxeon 33.Nd measurement events for 34.Tn Intel 35.Tn Haswell Xeon 36family CPUs 37.Sh LIBRARY 38.Lb libpmc 39.Sh SYNOPSIS 40.In pmc.h 41.Sh DESCRIPTION 42.Tn Intel 43.Tn "Haswell" 44CPUs contain PMCs conforming to version 2 of the 45.Tn Intel 46performance measurement architecture. 47These CPUs may contain up to two classes of PMCs: 48.Bl -tag -width "Li PMC_CLASS_IAP" 49.It Li PMC_CLASS_IAF 50Fixed-function counters that count only one hardware event per counter. 51.It Li PMC_CLASS_IAP 52Programmable counters that may be configured to count one of a defined 53set of hardware events. 54.El 55.Pp 56The number of PMCs available in each class and their widths need to be 57determined at run time by calling 58.Xr pmc_cpuinfo 3 . 59.Pp 60Intel Haswell Xeon PMCs are documented in 61.Rs 62.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" 63.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" 64.%N "Order Number: 325462-052US" 65.%D September 2014 66.%Q "Intel Corporation" 67.Re 68.Ss HASWELL FIXED FUNCTION PMCS 69These PMCs and their supported events are documented in 70.Xr pmc.iaf 3 . 71.Ss HASWELL PROGRAMMABLE PMCS 72The programmable PMCs support the following capabilities: 73.Bl -column "PMC_CAP_INTERRUPT" "Support" 74.It Em Capability Ta Em Support 75.It PMC_CAP_CASCADE Ta \&No 76.It PMC_CAP_EDGE Ta Yes 77.It PMC_CAP_INTERRUPT Ta Yes 78.It PMC_CAP_INVERT Ta Yes 79.It PMC_CAP_READ Ta Yes 80.It PMC_CAP_PRECISE Ta \&No 81.It PMC_CAP_SYSTEM Ta Yes 82.It PMC_CAP_TAGGING Ta \&No 83.It PMC_CAP_THRESHOLD Ta Yes 84.It PMC_CAP_USER Ta Yes 85.It PMC_CAP_WRITE Ta Yes 86.El 87.Ss Event Qualifiers 88Event specifiers for these PMCs support the following common 89qualifiers: 90.Bl -tag -width indent 91.It Li rsp= Ns Ar value 92Configure the Off-core Response bits. 93.Bl -tag -width indent 94.It Li DMND_DATA_RD 95Counts the number of demand and DCU prefetch data reads of full 96and partial cachelines as well as demand data page table entry 97cacheline reads. Does not count L2 data read prefetches or 98instruction fetches. 99.It Li REQ_DMND_RFO 100Counts the number of demand and DCU prefetch reads for ownership (RFO) 101requests generated by a write to data cacheline. Does not count L2 RFO 102prefetches. 103.It Li REQ_DMND_IFETCH 104Counts the number of demand and DCU prefetch instruction cacheline reads. 105Does not count L2 code read prefetches. 106.It Li REQ_WB 107Counts the number of writeback (modified to exclusive) transactions. 108.It Li REQ_PF_DATA_RD 109Counts the number of data cacheline reads generated by L2 prefetchers. 110.It Li REQ_PF_RFO 111Counts the number of RFO requests generated by L2 prefetchers. 112.It Li REQ_PF_IFETCH 113Counts the number of code reads generated by L2 prefetchers. 114.It Li REQ_PF_LLC_DATA_RD 115L2 prefetcher to L3 for loads. 116.It Li REQ_PF_LLC_RFO 117RFO requests generated by L2 prefetcher 118.It Li REQ_PF_LLC_IFETCH 119L2 prefetcher to L3 for instruction fetches. 120.It Li REQ_BUS_LOCKS 121Bus lock and split lock requests. 122.It Li REQ_STRM_ST 123Streaming store requests. 124.It Li REQ_OTHER 125Any other request that crosses IDI, including I/O. 126.It Li RES_ANY 127Catch all value for any response types. 128.It Li RES_SUPPLIER_NO_SUPP 129No Supplier Information available. 130.It Li RES_SUPPLIER_LLC_HITM 131M-state initial lookup stat in L3. 132.It Li RES_SUPPLIER_LLC_HITE 133E-state. 134.It Li RES_SUPPLIER_LLC_HITS 135S-state. 136.It Li RES_SUPPLIER_LLC_HITF 137F-state. 138.It Li RES_SUPPLIER_LOCAL 139Local DRAM Controller. 140.It Li RES_SNOOP_SNP_NONE 141No details on snoop-related information. 142.It Li RES_SNOOP_SNP_NO_NEEDED 143No snoop was needed to satisfy the request. 144.It Li RES_SNOOP_SNP_MISS 145A snoop was needed and it missed all snooped caches: 146-For LLC Hit, ReslHitl was returned by all cores 147-For LLC Miss, Rspl was returned by all sockets and data was returned from 148DRAM. 149.It Li RES_SNOOP_HIT_NO_FWD 150A snoop was needed and it hits in at least one snooped cache. Hit denotes a 151cache-line was valid before snoop effect. This includes: 152-Snoop Hit w/ Invalidation (LLC Hit, RFO) 153-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) 154-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) 155In the LLC Miss case, data is returned from DRAM. 156.It Li RES_SNOOP_HIT_FWD 157A snoop was needed and data was forwarded from a remote socket. 158This includes: 159-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). 160.It Li RES_SNOOP_HITM 161A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a 162cache-line was in modified state before effect as a results of snoop. This 163includes: 164-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) 165-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) 166-Snoop MtoS (LLC Hit, IFetch/Data_RD). 167.It Li RES_NON_DRAM 168Target was non-DRAM system address. This includes MMIO transactions. 169.El 170.It Li cmask= Ns Ar value 171Configure the PMC to increment only if the number of configured 172events measured in a cycle is greater than or equal to 173.Ar value . 174.It Li edge 175Configure the PMC to count the number of de-asserted to asserted 176transitions of the conditions expressed by the other qualifiers. 177If specified, the counter will increment only once whenever a 178condition becomes true, irrespective of the number of clocks during 179which the condition remains true. 180.It Li inv 181Invert the sense of comparison when the 182.Dq Li cmask 183qualifier is present, making the counter increment when the number of 184events per cycle is less than the value specified by the 185.Dq Li cmask 186qualifier. 187.It Li os 188Configure the PMC to count events happening at processor privilege 189level 0. 190.It Li usr 191Configure the PMC to count events occurring at privilege levels 1, 2 192or 3. 193.El 194.Pp 195If neither of the 196.Dq Li os 197or 198.Dq Li usr 199qualifiers are specified, the default is to enable both. 200.Ss Event Specifiers (Programmable PMCs) 201Haswell programmable PMCs support the following events: 202.Bl -tag -width indent 203.It Li LD_BLOCKS.STORE_FORWARD 204.Pq Event 03H , Umask 02H 205Loads blocked by overlapping with store buffer that 206cannot be forwarded. 207.It Li MISALIGN_MEM_REF.LOADS 208.Pq Event 05H , Umask 01H 209Speculative cache-line split load uops dispatched to 210L1D. 211.It Li MISALIGN_MEM_REF.STORES 212.Pq Event 05H , Umask 02H 213Speculative cache-line split Store-address uops 214dispatched to L1D. 215.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS 216.Pq Event 07H , Umask 01H 217False dependencies in MOB due to partial compare 218on address. 219.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK 220.Pq Event 08H , Umask 01H 221Misses in all TLB levels that cause a page walk of any 222page size. 223.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K 224.Pq Event 08H , Umask 02H 225Completed page walks due to demand load misses 226that caused 4K page walks in any TLB levels. 227.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K 228.Pq Event 08H , Umask 02H 229Completed page walks due to demand load misses 230that caused 2M/4M page walks in any TLB levels. 231.It Li DTLB_LOAD_MISSES.WALK_COMPLETED 232.Pq Event 08H , Umask 0EH 233Completed page walks in any TLB of any page size 234due to demand load misses 235.It Li DTLB_LOAD_MISSES.WALK_DURATION 236.Pq Event 08H , Umask 10H 237Cycle PMH is busy with a walk. 238.It Li DTLB_LOAD_MISSES.STLB_HIT_4K 239.Pq Event 08H , Umask 20H 240Load misses that missed DTLB but hit STLB (4K). 241.It Li DTLB_LOAD_MISSES.STLB_HIT_2M 242.Pq Event 08H , Umask 40H 243Load misses that missed DTLB but hit STLB (2M). 244.It Li DTLB_LOAD_MISSES.STLB_HIT 245.Pq Event 08H , Umask 60H 246Number of cache load STLB hits. No page walk. 247.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS 248.Pq Event 08H , Umask 80H 249DTLB demand load misses with low part of linear-to- 250physical address translation missed 251.It Li INT_MISC.RECOVERY_CYCLES 252.Pq Event 0DH , Umask 03H 253Cycles waiting to recover after Machine Clears 254except JEClear. Set Cmask= 1. 255.It Li UOPS_ISSUED.ANY 256.Pq Event 0EH , Umask 01H 257ncrements each cycle the # of Uops issued by the 258RAT to RS. 259Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles 260of this core. 261.It Li UOPS_ISSUED.FLAGS_MERGE 262.Pq Event 0EH , Umask 10H 263Number of flags-merge uops allocated. Such uops 264adds delay. 265.It Li UOPS_ISSUED.SLOW_LEA 266.Pq Event 0EH , Umask 20H 267Number of slow LEA or similar uops allocated. Such 268uop has 3 sources (e.g. 2 sources + immediate) 269regardless if as a result of LEA instruction or not. 270.It Li UOPS_ISSUED.SiNGLE_MUL 271.Pq Event 0EH , Umask 40H 272Number of multiply packed/scalar single precision 273uops allocated. 274.It Li L2_RQSTS.DEMAND_DATA_RD_MISS 275.Pq Event 24H , Umask 21H 276Demand Data Read requests that missed L2, no 277rejects. 278.It Li L2_RQSTS.DEMAND_DATA_RD_HIT 279.Pq Event 24H , Umask 41H 280Demand Data Read requests that hit L2 cache. 281.It Li L2_RQSTS.ALL_DEMAND_DATA_RD 282.Pq Event 24H , Umask E1H 283Counts any demand and L1 HW prefetch data load 284requests to L2. 285.It Li L2_RQSTS.RFO_HIT 286.Pq Event 24H , Umask 42H 287Counts the number of store RFO requests that hit 288the L2 cache. 289.It Li L2_RQSTS.RFO_MISS 290.Pq Event 24H , Umask 22H 291Counts the number of store RFO requests that miss 292the L2 cache. 293.It Li L2_RQSTS.ALL_RFO 294.Pq Event 24H , Umask E2H 295Counts all L2 store RFO requests. 296.It Li L2_RQSTS.CODE_RD_HIT 297.Pq Event 24H , Umask 44H 298Number of instruction fetches that hit the L2 cache. 299.It Li L2_RQSTS.CODE_RD_MISS 300.Pq Event 24H , Umask 24H 301Number of instruction fetches that missed the L2 302cache. 303.It Li L2_RQSTS.ALL_DEMAND_MISS 304.Pq Event 24H , Umask 27H 305Demand requests that miss L2 cache. 306.It Li L2_RQSTS.ALL_DEMAND_REFERENCES 307.Pq Event 24H , Umask E7H 308Demand requests to L2 cache. 309.It Li L2_RQSTS.ALL_CODE_RD 310.Pq Event 24H , Umask E4H 311Counts all L2 code requests. 312.It Li L2_RQSTS.L2_PF_HIT 313.Pq Event 24H , Umask 50H 314Counts all L2 HW prefetcher requests that hit L2. 315.It Li L2_RQSTS.L2_PF_MISS 316.Pq Event 24H , Umask 30H 317Counts all L2 HW prefetcher requests that missed 318L2. 319.It Li L2_RQSTS.ALL_PF 320.Pq Event 24H , Umask F8H 321Counts all L2 HW prefetcher requests. 322.It Li L2_RQSTS.MISS 323.Pq Event 24H , Umask 3FH 324All requests that missed L2. 325.It Li L2_RQSTS.REFERENCES 326.Pq Event 24H , Umask FFH 327All requests to L2 cache. 328.It Li L2_DEMAND_RQSTS.WB_HIT 329.Pq Event 27H , Umask 50H 330Not rejected writebacks that hit L2 cache 331.It Li LONGEST_LAT_CACHE.REFERENCE 332.Pq Event 2EH , Umask 4FH 333This event counts requests originating from the core 334that reference a cache line in the last level cache. 335.It Li LONGEST_LAT_CACHE.MISS 336.Pq Event 2EH , Umask 41H 337This event counts each cache miss condition for 338references to the last level cache. 339.It Li CPU_CLK_UNHALTED.THREAD_P 340.Pq Event 3CH , Umask 00H 341Counts the number of thread cycles while the thread 342is not in a halt state. The thread enters the halt state 343when it is running the HLT instruction. The core 344frequency may change from time to time due to 345power or thermal throttling. 346.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK 347.Pq Event 3CH , Umask 01H 348Increments at the frequency of XCLK (100 MHz) 349when not halted. 350.It Li L1D_PEND_MISS.PENDING 351.Pq Event 48H , Umask 01H 352Increments the number of outstanding L1D misses 353every cycle. Set Cmaks = 1 and Edge =1 to count 354occurrences. 355.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK 356.Pq Event 49H , Umask 01H 357Miss in all TLB levels causes an page walk of any 358page size (4K/2M/4M/1G). 359.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K 360.Pq Event 49H , Umask 02H 361Completed page walks due to store misses in one or 362more TLB levels of 4K page structure. 363.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M 364.Pq Event 49H , Umask 04H 365Completed page walks due to store misses in one or 366more TLB levels of 2M/4M page structure. 367.It Li DTLB_STORE_MISSES.WALK_COMPLETED 368.Pq Event 49H , Umask 0EH 369Completed page walks due to store miss in any TLB 370levels of any page size (4K/2M/4M/1G). 371.It Li DTLB_STORE_MISSES.WALK_DURATION 372.Pq Event 49H , Umask 10H 373Cycles PMH is busy with this walk. 374.It Li DTLB_STORE_MISSES.STLB_HIT_4K 375.Pq Event 49H , Umask 20H 376Store misses that missed DTLB but hit STLB (4K). 377.It Li DTLB_STORE_MISSES.STLB_HIT_2M 378.Pq Event 49H , Umask 40H 379Store misses that missed DTLB but hit STLB (2M). 380.It Li DTLB_STORE_MISSES.STLB_HIT 381.Pq Event 49H , Umask 60H 382Store operations that miss the first TLB level but hit 383the second and do not cause page walks. 384.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS 385.Pq Event 49H , Umask 80H 386DTLB store misses with low part of linear-to-physical 387address translation missed. 388.It Li LOAD_HIT_PRE.SW_PF 389.Pq Event 4CH , Umask 01H 390Non-SW-prefetch load dispatches that hit fill buffer 391allocated for S/W prefetch. 392.It Li LOAD_HIT_PRE.HW_PF 393.Pq Event 4CH , Umask 02H 394Non-SW-prefetch load dispatches that hit fill buffer 395allocated for H/W prefetch. 396.It Li L1D.REPLACEMENT 397.Pq Event 51H , Umask 01H 398Counts the number of lines brought into the L1 data 399cache. 400.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED 401.Pq Event 58H , Umask 04H 402Number of integer Move Elimination candidate uops 403that were not eliminated. 404.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED 405.Pq Event 58H , Umask 08H 406Number of SIMD Move Elimination candidate uops 407that were not eliminated. 408.It Li MOVE_ELIMINATION.INT_ELIMINATED 409.Pq Event 58H , Umask 01H 410Unhalted core cycles when the thread is in ring 0. 411.It Li MOVE_ELIMINATION.SMID_ELIMINATED 412.Pq Event 58H , Umask 02H 413Number of SIMD Move Elimination candidate uops 414that were eliminated. 415.It Li CPL_CYCLES.RING0 416.Pq Event 5CH , Umask 02H 417Unhalted core cycles when the thread is in ring 0. 418.It Li CPL_CYCLES.RING123 419.Pq Event 5CH , Umask 01H 420Unhalted core cycles when the thread is not in ring 0. 421.It Li RS_EVENTS.EMPTY_CYCLES 422.Pq Event 5EH , Umask 01H 423Cycles the RS is empty for the thread. 424.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD 425.Pq Event 60H , Umask 01H 426Offcore outstanding Demand Data Read transactions 427in SQ to uncore. Set Cmask=1 to count cycles. 428.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD 429.Pq Event 60H , Umask 02H 430Offcore outstanding Demand code Read transactions 431in SQ to uncore. Set Cmask=1 to count cycles. 432.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO 433.Pq Event 60H , Umask 04H 434Offcore outstanding RFO store transactions in SQ to 435uncore. Set Cmask=1 to count cycles. 436.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD 437.Pq Event 60H , Umask 08H 438Offcore outstanding cacheable data read 439transactions in SQ to uncore. Set Cmask=1 to count 440cycles. 441.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION 442.Pq Event 63H , Umask 01H 443Cycles in which the L1D and L2 are locked, due to a 444UC lock or split lock. 445.It Li LOCK_CYCLES.CACHE_LOCK_DURATION 446.Pq Event 63H , Umask 02H 447Cycles in which the L1D is locked. 448.It Li IDQ.EMPTY 449.Pq Event 79H , Umask 02H 450Counts cycles the IDQ is empty. 451.It Li IDQ.MITE_UOPS 452.Pq Event 79H , Umask 04H 453Increment each cycle # of uops delivered to IDQ from 454MITE path. 455Set Cmask = 1 to count cycles. 456.It Li IDQ.DSB_UOPS 457.Pq Event 79H , Umask 08H 458Increment each cycle. # of uops delivered to IDQ 459from DSB path. 460Set Cmask = 1 to count cycles. 461.It Li IDQ.MS_DSB_UOPS 462.Pq Event 79H , Umask 10H 463Increment each cycle # of uops delivered to IDQ 464when MS_busy by DSB. Set Cmask = 1 to count 465cycles. Add Edge=1 to count # of delivery. 466.It Li IDQ.MS_MITE_UOPS 467.Pq Event 79H , Umask 20H 468ncrement each cycle # of uops delivered to IDQ 469when MS_busy by MITE. Set Cmask = 1 to count 470cycles. 471.It Li IDQ.MS_UOPS 472.Pq Event 79H , Umask 30H 473Increment each cycle # of uops delivered to IDQ from 474MS by either DSB or MITE. Set Cmask = 1 to count 475cycles. 476.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS 477.Pq Event 79H , Umask 18H 478Counts cycles DSB is delivered at least one uops. Set 479Cmask = 1. 480.It Li IDQ.ALL_DSB_CYCLES_4_UOPS 481.Pq Event 79H , Umask 18H 482Counts cycles DSB is delivered four uops. Set Cmask 483=4. 484.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS 485.Pq Event 79H , Umask 24H 486Counts cycles MITE is delivered at least one uops. Set 487Cmask = 1. 488.It Li IDQ.ALL_MITE_CYCLES_4_UOPS 489.Pq Event 79H , Umask 24H 490Counts cycles MITE is delivered four uops. Set Cmask 491=4. 492.It Li IDQ.MITE_ALL_UOPS 493.Pq Event 79H , Umask 3CH 494# of uops delivered to IDQ from any path. 495.It Li ICACHE.MISSES 496.Pq Event 80H , Umask 02H 497Number of Instruction Cache, Streaming Buffer and 498Victim Cache Misses. Includes UC accesses. 499.It Li ITLB_MISSES.MISS_CAUSES_A_WALK 500.Pq Event 85H , Umask 01H 501Misses in ITLB that causes a page walk of any page 502size. 503.It Li ITLB_MISSES.WALK_COMPLETED_4K 504.Pq Event 85H , Umask 02H 505Completed page walks due to misses in ITLB 4K page 506entries. 507.It Li TLB_MISSES.WALK_COMPLETED_2M_4M 508.Pq Event 85H , Umask 04H 509Completed page walks due to misses in ITLB 2M/4M 510page entries. 511.It Li ITLB_MISSES.WALK_COMPLETED 512.Pq Event 85H , Umask 0EH 513Completed page walks in ITLB of any page size. 514.It Li ITLB_MISSES.WALK_DURATION 515.Pq Event 85H , Umask 10H 516Cycle PMH is busy with a walk. 517.It Li ITLB_MISSES.STLB_HIT_4K 518.Pq Event 85H , Umask 20H 519ITLB misses that hit STLB (4K). 520.It Li ITLB_MISSES.STLB_HIT_2M 521.Pq Event 85H , Umask 40H 522ITLB misses that hit STLB (2K). 523.It Li ITLB_MISSES.STLB_HIT 524.Pq Event 85H , Umask 60H 525TLB misses that hit STLB. No page walk. 526.It Li ILD_STALL.LCP 527.Pq Event 87H , Umask 01H 528Stalls caused by changing prefix length of the 529instruction. 530.It Li ILD_STALL.IQ_FULL 531.Pq Event 87H , Umask 04H 532Stall cycles due to IQ is full. 533.It Li BR_INST_EXEC.NONTAKEN_COND 534.Pq Event 88H , Umask 41H 535Count conditional near branch instructions that were executed (but not 536necessarily retired) and not taken. 537.It Li BR_INST_EXEC.TAKEN_COND 538.Pq Event 88H , Umask 81H 539Count conditional near branch instructions that were executed (but not 540necessarily retired) and taken. 541.It Li BR_INST_EXEC.DIRECT_JMP 542.Pq Event 88H , Umask 82H 543Count all unconditional near branch instructions excluding calls and 544indirect branches. 545.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET 546.Pq Event 88H , Umask 84H 547Count executed indirect near branch instructions that are not calls nor 548returns. 549.It Li BR_INST_EXEC.RETURN_NEAR 550.Pq Event 88H , Umask 88H 551Count indirect near branches that have a return mnemonic. 552.It Li BR_INST_EXEC.DIRECT_NEAR_CALL 553.Pq Event 88H , Umask 90H 554Count unconditional near call branch instructions, excluding non call 555branch, executed. 556.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL 557.Pq Event 88H , Umask A0H 558Count indirect near calls, including both register and memory indirect, 559executed. 560.It Li BR_INST_EXEC.ALL_BRANCHES 561.Pq Event 88H , Umask FFH 562Counts all near executed branches (not necessarily retired). 563.It Li BR_MISP_EXEC.NONTAKEN_COND 564.Pq Event 89H , Umask 41H 565Count conditional near branch instructions mispredicted as nontaken. 566.It Li BR_MISP_EXEC.TAKEN_COND 567.Pq Event 89H , Umask 81H 568Count conditional near branch instructions mispredicted as taken. 569.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET 570.Pq Event 89H , Umask 84H 571Count mispredicted indirect near branch instructions that are not calls 572nor returns. 573.It Li BR_MISP_EXEC.RETURN_NEAR 574.Pq Event 89H , Umask 88H 575Count mispredicted indirect near branches that have a return mnemonic. 576.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL 577.Pq Event 89H , Umask 90H 578Count mispredicted unconditional near call branch instructions, excluding 579non call branch, executed. 580.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL 581.Pq Event 89H , Umask A0H 582Count mispredicted indirect near calls, including both register and memory 583indirect, executed. 584.It Li BR_MISP_EXEC.ALL_BRANCHES 585.Pq Event 89H , Umask FFH 586Counts all mispredicted near executed branches (not necessarily retired). 587.It Li IDQ_UOPS_NOT_DELIVERED.CORE 588.Pq Event 9CH , Umask 01H 589Count number of non-delivered uops to RAT per 590thread. 591.It Li UOPS_EXECUTED_PORT.PORT_0 592.Pq Event A1H , Umask 01H 593Cycles which a Uop is dispatched on port 0 in this 594thread. 595.It Li UOPS_EXECUTED_PORT.PORT_1 596.Pq Event A1H , Umask 02H 597Cycles which a Uop is dispatched on port 1 in this 598thread. 599.It Li UOPS_EXECUTED_PORT.PORT_2 600.Pq Event A1H , Umask 04H 601Cycles which a Uop is dispatched on port 2 in this 602thread. 603.It Li UOPS_EXECUTED_PORT.PORT_3 604.Pq Event A1H , Umask 08H 605Cycles which a Uop is dispatched on port 3 in this 606thread. 607.It Li UOPS_EXECUTED_PORT.PORT_4 608.Pq Event A1H , Umask 10H 609Cycles which a Uop is dispatched on port 4 in this 610thread. 611.It Li UOPS_EXECUTED_PORT.PORT_5 612.Pq Event A1H , Umask 20H 613Cycles which a Uop is dispatched on port 5 in this 614thread. 615.It Li UOPS_EXECUTED_PORT.PORT_6 616.Pq Event A1H , Umask 40H 617Cycles which a Uop is dispatched on port 6 in this 618thread. 619.It Li UOPS_EXECUTED_PORT.PORT_7 620.Pq Event A1H , Umask 80H 621Cycles which a Uop is dispatched on port 7 in this 622thread. 623.It Li RESOURCE_STALLS.ANY 624.Pq Event A2H , Umask 01H 625Cycles Allocation is stalled due to Resource Related 626reason. 627.It Li RESOURCE_STALLS.RS 628.Pq Event A2H , Umask 04H 629Cycles stalled due to no eligible RS entry available. 630.It Li RESOURCE_STALLS.SB 631.Pq Event A2H , Umask 08H 632Cycles stalled due to no store buffers available (not 633including draining form sync). 634.It Li RESOURCE_STALLS.ROB 635.Pq Event A2H , Umask 10H 636Cycles stalled due to re-order buffer full. 637.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING 638.Pq Event A3H , Umask 01H 639Cycles with pending L2 miss loads. Set Cmask=2 to 640count cycle. 641.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING 642.Pq Event A3H , Umask 02H 643Cycles with pending memory loads. Set Cmask=2 to 644count cycle. 645.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING 646.Pq Event A3H , Umask 05H 647Number of loads missed L2. 648.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING 649.Pq Event A3H , Umask 08H 650Cycles with pending L1 cache miss loads. Set 651Cmask=8 to count cycle. 652.It Li ITLB.ITLB_FLUSH 653.Pq Event AEH , Umask 01H 654Counts the number of ITLB flushes, includes 6554k/2M/4M pages. 656.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD 657.Pq Event B0H , Umask 01H 658Demand data read requests sent to uncore. 659.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD 660.Pq Event B0H , Umask 02H 661Demand code read requests sent to uncore. 662.It Li OFFCORE_REQUESTS.DEMAND_RFO 663.Pq Event B0H , Umask 04H 664Demand RFO read requests sent to uncore, including 665regular RFOs, locks, ItoM. 666.It Li OFFCORE_REQUESTS.ALL_DATA_RD 667.Pq Event B0H , Umask 08H 668Data read requests sent to uncore (demand and 669prefetch). 670.It Li UOPS_EXECUTED.CORE 671.Pq Event B1H , Umask 02H 672Counts total number of uops to be executed per-core 673each cycle. 674.It Li OFF_CORE_RESPONSE_0 675.Pq Event B7H , Umask 01H 676Requires MSR 01A6H 677.It Li OFF_CORE_RESPONSE_1 678.Pq Event BBH , Umask 01H 679Requires MSR 01A7H 680.It Li PAGE_WALKER_LOADS.DTLB_L1 681.Pq Event BCH , Umask 11H 682Number of DTLB page walker loads that hit in the 683L1+FB. 684.It Li PAGE_WALKER_LOADS.ITLB_L1 685.Pq Event BCH , Umask 21H 686Number of ITLB page walker loads that hit in the 687L1+FB. 688.It Li PAGE_WALKER_LOADS.DTLB_L2 689.Pq Event BCH , Umask 12H 690Number of DTLB page walker loads that hit in the L2. 691.It Li PAGE_WALKER_LOADS.ITLB_L2 692.Pq Event BCH , Umask 22H 693Number of ITLB page walker loads that hit in the L2. 694.It Li PAGE_WALKER_LOADS.DTLB_L3 695.Pq Event BCH , Umask 14H 696Number of DTLB page walker loads that hit in the L3. 697.It Li PAGE_WALKER_LOADS.ITLB_L3 698.Pq Event BCH , Umask 24H 699Number of ITLB page walker loads that hit in the L3. 700.It Li PAGE_WALKER_LOADS.DTLB_MEMORY 701.Pq Event BCH , Umask 18H 702Number of DTLB page walker loads from memory. 703.It Li PAGE_WALKER_LOADS.ITLB_MEMORY 704.Pq Event BCH , Umask 28H 705Number of ITLB page walker loads from memory. 706.It Li TLB_FLUSH.DTLB_THREAD 707.Pq Event BDH , Umask 01H 708DTLB flush attempts of the thread-specific entries. 709.It Li TLB_FLUSH.STLB_ANY 710.Pq Event BDH , Umask 20H 711Count number of STLB flush attempts. 712.It Li INST_RETIRED.ANY_P 713.Pq Event C0H , Umask 00H 714Number of instructions at retirement. 715.It Li INST_RETIRED.ALL 716.Pq Event C0H , Umask 01H 717Precise instruction retired event with HW to reduce 718effect of PEBS shadow in IP distribution. 719.It Li OTHER_ASSISTS.AVX_TO_SSE 720.Pq Event C1H , Umask 08H 721Number of transitions from AVX-256 to legacy SSE 722when penalty applicable. 723.It Li OTHER_ASSISTS.SSE_TO_AVX 724.Pq Event C1H , Umask 10H 725Number of transitions from SSE to AVX-256 when 726penalty applicable. 727.It Li OTHER_ASSISTS.ANY_WB_ASSIST 728.Pq Event C1H , Umask 40H 729Number of microcode assists invoked by HW upon 730uop writeback. 731.It Li UOPS_RETIRED.ALL 732.Pq Event C2H , Umask 01H 733Counts the number of micro-ops retired, Use 734cmask=1 and invert to count active cycles or stalled 735cycles. 736.It Li UOPS_RETIRED.RETIRE_SLOTS 737.Pq Event C2H , Umask 02H 738Counts the number of retirement slots used each 739cycle. 740.It Li MACHINE_CLEARS.MEMORY_ORDERING 741.Pq Event C3H , Umask 02H 742Counts the number of machine clears due to memory 743order conflicts. 744.It Li MACHINE_CLEARS.SMC 745.Pq Event C3H , Umask 04H 746Number of self-modifying-code machine clears 747detected. 748.It Li MACHINE_CLEARS.MASKMOV 749.Pq Event C3H , Umask 20H 750Counts the number of executed AVX masked load 751operations that refer to an illegal address range with 752the mask bits set to 0. 753.It Li BR_INST_RETIRED.ALL_BRANCHES 754.Pq Event C4H , Umask 00H 755Branch instructions at retirement. 756.It Li BR_INST_RETIRED.CONDITIONAL 757.Pq Event C4H , Umask 01H 758Counts the number of conditional branch instructions Supports PEBS 759retired. 760.It Li BR_INST_RETIRED.NEAR_CALL 761.Pq Event C4H , Umask 02H 762Direct and indirect near call instructions retired. 763.It Li BR_INST_RETIRED.ALL_BRANCHES 764.Pq Event C4H , Umask 04H 765Counts the number of branch instructions retired. 766.It Li BR_INST_RETIRED.NEAR_RETURN 767.Pq Event C4H , Umask 08H 768Counts the number of near return instructions 769retired. 770.It Li BR_INST_RETIRED.NOT_TAKEN 771.Pq Event C4H , Umask 10H 772Counts the number of not taken branch instructions 773retired. 774 It Li BR_INST_RETIRED.NEAR_TAKEN 775.Pq Event C4H , Umask 20H 776Number of near taken branches retired. 777.It Li BR_INST_RETIRED.FAR_BRANCH 778.Pq Event C4H , Umask 40H 779Number of far branches retired. 780.It Li BR_MISP_RETIRED.ALL_BRANCHES 781.Pq Event C5H , Umask 00H 782Mispredicted branch instructions at retirement 783.It Li BR_MISP_RETIRED.CONDITIONAL 784.Pq Event C5H , Umask 01H 785Mispredicted conditional branch instructions retired. 786.It Li BR_MISP_RETIRED.CONDITIONAL 787.Pq Event C5H , Umask 04H 788Mispredicted macro branch instructions retired. 789.It Li FP_ASSIST.X87_OUTPUT 790.Pq Event CAH , Umask 02H 791Number of X87 FP assists due to Output values. 792.It Li FP_ASSIST.X87_INPUT 793.Pq Event CAH , Umask 04H 794Number of X87 FP assists due to input values. 795.It Li FP_ASSIST.SIMD_OUTPUT 796.Pq Event CAH , Umask 08H 797Number of SIMD FP assists due to Output values. 798.It Li FP_ASSIST.SIMD_INPUT 799.Pq Event CAH , Umask 10H 800Number of SIMD FP assists due to input values. 801.It Li FP_ASSIST.ANY 802.Pq Event CAH , Umask 1EH 803Cycles with any input/output SSE* or FP assists. 804.It Li ROB_MISC_EVENTS.LBR_INSERTS 805.Pq Event CCH , Umask 20H 806Count cases of saving new LBR records by hardware. 807.It Li MEM_TRANS_RETIRED.LOAD_LATENCY 808.Pq Event CDH , Umask 01H 809Randomly sampled loads whose latency is above a 810user defined threshold. A small fraction of the overall 811loads are sampled due to randomization. 812.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS 813.Pq Event D0H , Umask 11H 814Count retired load uops that missed the STLB. 815.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES 816.Pq Event D0H , Umask 12H 817Count retired store uops that missed the STLB. 818.It Li MEM_UOPS_RETIRED.SPLIT_LOADS 819.Pq Event D0H , Umask 41H 820Count retired load uops that were split across a cache line. 821.It Li MEM_UOPS_RETIRED.SPLIT_STORES 822.Pq Event D0H , Umask 42H 823Count retired store uops that were split across a cache line. 824.It Li MEM_UOPS_RETIRED.ALL_LOADS 825.Pq Event D0H , Umask 81H 826Count all retired load uops. 827.It Li MEM_UOPS_RETIRED.ALL_STORES 828.Pq Event D0H , Umask 82H 829Count all retired store uops. 830.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT 831.Pq Event D1H , Umask 01H 832Retired load uops with L1 cache hits as data sources. 833.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT 834.Pq Event D1H , Umask 02H 835Retired load uops with L2 cache hits as data sources. 836.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT 837.Pq Event D1H , Umask 04H 838Retired load uops with LLC cache hits as data 839sources. 840.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS 841.Pq Event D1H , Umask 10H 842Retired load uops missed L2. Unknown data source 843excluded. 844.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB 845.Pq Event D1H , Umask 40H 846Retired load uops which data sources were load uops 847missed L1 but hit FB due to preceding miss to the 848same cache line with data not ready. 849.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS 850.Pq Event D2H , Umask 01H 851Retired load uops which data sources were LLC hit 852and cross-core snoop missed in on-pkg core cache. 853.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT 854.Pq Event D2H , Umask 02H 855Retired load uops which data sources were LLC and 856cross-core snoop hits in on-pkg core cache. 857.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM 858.Pq Event D2H , Umask 04H 859Retired load uops which data sources were HitM 860responses from shared LLC. 861.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE 862.Pq Event D2H , Umask 08H 863Retired load uops which data sources were hits in 864LLC without snoops required. 865.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM 866.Pq Event D3H , Umask 01H 867Retired load uops which data sources missed LLC but 868serviced from local dram. 869.It Li BACLEARS.ANY 870.Pq Event E6H , Umask 1FH 871Number of front end re-steers due to BPU 872misprediction. 873.It Li L2_TRANS.DEMAND_DATA_RD 874.Pq Event F0H , Umask 01H 875Demand Data Read requests that access L2 cache. 876.It Li L2_TRANS.RFO 877.Pq Event F0H , Umask 02H 878RFO requests that access L2 cache. 879.It Li L2_TRANS.CODE_RD 880.Pq Event F0H , Umask 04H 881L2 cache accesses when fetching instructions. 882.It Li L2_TRANS.ALL_PF 883.Pq Event F0H , Umask 08H 884Any MLC or LLC HW prefetch accessing L2, including 885rejects. 886.It Li L2_TRANS.L1D_WB 887.Pq Event F0H , Umask 10H 888L1D writebacks that access L2 cache. 889.It Li L2_TRANS.L2_FILL 890.Pq Event F0H , Umask 20H 891L2 fill requests that access L2 cache. 892.It Li L2_TRANS.L2_WB 893.Pq Event F0H , Umask 40H 894L2 writebacks that access L2 cache. 895.It Li L2_TRANS.ALL_REQUESTS 896.Pq Event F0H , Umask 80H 897Transactions accessing L2 pipe. 898.It Li L2_LINES_IN.I 899.Pq Event F1H , Umask 01H 900L2 cache lines in I state filling L2. 901.It Li L2_LINES_IN.S 902.Pq Event F1H , Umask 02H 903L2 cache lines in S state filling L2. 904.It Li L2_LINES_IN.E 905.Pq Event F1H , Umask 04H 906L2 cache lines in E state filling L2. 907.It Li L2_LINES_IN.ALL 908.Pq Event F1H , Umask 07H 909L2 cache lines filling L2. 910.It Li L2_LINES_OUT.DEMAND_CLEAN 911.Pq Event F2H , Umask 05H 912Clean L2 cache lines evicted by demand. 913.It Li L2_LINES_OUT.DEMAND_DIRTY 914.Pq Event F2H , Umask 06H 915Dirty L2 cache lines evicted by demand. 916.El 917.Sh SEE ALSO 918.Xr pmc 3 , 919.Xr pmc.atom 3 , 920.Xr pmc.core 3 , 921.Xr pmc.iaf 3 , 922.Xr pmc.ucf 3 , 923.Xr pmc.k7 3 , 924.Xr pmc.k8 3 , 925.Xr pmc.p4 3 , 926.Xr pmc.p5 3 , 927.Xr pmc.p6 3 , 928.Xr pmc.corei7 3 , 929.Xr pmc.corei7uc 3 , 930.Xr pmc.haswell 3 , 931.Xr pmc.haswelluc 3 , 932.Xr pmc.ivybridge 3 , 933.Xr pmc.ivybridgexeon 3 , 934.Xr pmc.sandybridge 3 , 935.Xr pmc.sandybridgeuc 3 , 936.Xr pmc.sandybridgexeon 3 , 937.Xr pmc.westmere 3 , 938.Xr pmc.westmereuc 3 , 939.Xr pmc.soft 3 , 940.Xr pmc.tsc 3 , 941.Xr pmc_cpuinfo 3 , 942.Xr pmclog 3 , 943.Xr hwpmc 4 944.Sh HISTORY 945Support for the Haswell Xeon microarchitecture first appeared in 946.Fx 10.2 . 947.Sh AUTHORS 948The 949.Lb libpmc 950library was written by 951.An "Joseph Koshy" 952.Aq jkoshy@FreeBSD.org . 953The support for the Haswell Xeon 954microarchitecture was written by 955.An "Randall Stewart" 956.Aq rrs@FreeBSD.org . 957