xref: /freebsd/lib/libpmc/pmc.atom.3 (revision ae477ca7da55f76d28859e1bd01cd1051e36f28f)
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24.Dd March 20, 2014
25.Dt PMC.ATOM 3
26.Os
27.Sh NAME
28.Nm pmc.atom
29.Nd measurement events for
30.Tn Intel
31.Tn Atom
32family CPUs
33.Sh LIBRARY
34.Lb libpmc
35.Sh SYNOPSIS
36.In pmc.h
37.Sh DESCRIPTION
38.Tn Intel
39.Tn Atom
40CPUs contain PMCs conforming to version 3 of the
41.Tn Intel
42performance measurement architecture.
43These CPUs contains two classes of PMCs:
44.Bl -tag -width "Li PMC_CLASS_IAP"
45.It Li PMC_CLASS_IAF
46Fixed-function counters that count only one hardware event per counter.
47.It Li PMC_CLASS_IAP
48Programmable counters that may be configured to count one of a defined
49set of hardware events.
50.El
51.Pp
52The number of PMCs available in each class and their widths need to be
53determined at run time by calling
54.Xr pmc_cpuinfo 3 .
55.Pp
56Intel Atom PMCs are documented in
57.Rs
58.%B "IA-32 Intel(R) Architecture Software Developer's Manual"
59.%T "Volume 3: System Programming Guide"
60.%N "Order Number 253669-027US"
61.%D July 2008
62.%Q "Intel Corporation"
63.Re
64.Ss ATOM FIXED FUNCTION PMCS
65These PMCs and their supported events are documented in
66.Xr pmc.iaf 3 .
67.Ss ATOM PROGRAMMABLE PMCS
68The programmable PMCs support the following capabilities:
69.Bl -column "PMC_CAP_INTERRUPT" "Support"
70.It Em Capability Ta Em Support
71.It PMC_CAP_CASCADE Ta \&No
72.It PMC_CAP_EDGE Ta Yes
73.It PMC_CAP_INTERRUPT Ta Yes
74.It PMC_CAP_INVERT Ta Yes
75.It PMC_CAP_READ Ta Yes
76.It PMC_CAP_PRECISE Ta \&No
77.It PMC_CAP_SYSTEM Ta Yes
78.It PMC_CAP_TAGGING Ta \&No
79.It PMC_CAP_THRESHOLD Ta Yes
80.It PMC_CAP_USER Ta Yes
81.It PMC_CAP_WRITE Ta Yes
82.El
83.Ss Event Qualifiers
84Event specifiers for these PMCs support the following common
85qualifiers:
86.Bl -tag -width indent
87.It Li any
88Count matching events seen on any logical processor in a package.
89.It Li cmask= Ns Ar value
90Configure the PMC to increment only if the number of configured
91events measured in a cycle is greater than or equal to
92.Ar value .
93.It Li edge
94Configure the PMC to count the number of de-asserted to asserted
95transitions of the conditions expressed by the other qualifiers.
96If specified, the counter will increment only once whenever a
97condition becomes true, irrespective of the number of clocks during
98which the condition remains true.
99.It Li inv
100Invert the sense of comparison when the
101.Dq Li cmask
102qualifier is present, making the counter increment when the number of
103events per cycle is less than the value specified by the
104.Dq Li cmask
105qualifier.
106.It Li os
107Configure the PMC to count events happening at processor privilege
108level 0.
109.It Li usr
110Configure the PMC to count events occurring at privilege levels 1, 2
111or 3.
112.El
113.Pp
114If neither of the
115.Dq Li os
116or
117.Dq Li usr
118qualifiers are specified, the default is to enable both.
119.Pp
120Events that require core-specificity to be specified use a
121additional qualifier
122.Dq Li core= Ns Ar core ,
123where argument
124.Ar core
125is one of:
126.Bl -tag -width indent
127.It Li all
128Measure event conditions on all cores.
129.It Li this
130Measure event conditions on this core.
131.El
132.Pp
133The default is
134.Dq Li this .
135.Pp
136Events that require an agent qualifier to be specified use an
137additional qualifier
138.Dq Li agent= Ns agent ,
139where argument
140.Ar agent
141is one of:
142.Bl -tag -width indent
143.It Li this
144Measure events associated with this bus agent.
145.It Li any
146Measure events caused by any bus agent.
147.El
148.Pp
149The default is
150.Dq Li this .
151.Pp
152Events that require a hardware prefetch qualifier to be specified use an
153additional qualifier
154.Dq Li prefetch= Ns Ar prefetch ,
155where argument
156.Ar prefetch
157is one of:
158.Bl -tag -width "exclude"
159.It Li both
160Include all prefetches.
161.It Li only
162Only count hardware prefetches.
163.It Li exclude
164Exclude hardware prefetches.
165.El
166.Pp
167The default is
168.Dq Li both .
169.Pp
170Events that require a cache coherence qualifier to be specified use an
171additional qualifier
172.Dq Li cachestate= Ns Ar state ,
173where argument
174.Ar state
175contains one or more of the following letters:
176.Bl -tag -width indent
177.It Li e
178Count cache lines in the exclusive state.
179.It Li i
180Count cache lines in the invalid state.
181.It Li m
182Count cache lines in the modified state.
183.It Li s
184Count cache lines in the shared state.
185.El
186.Pp
187The default is
188.Dq Li eims .
189.Pp
190Events that require a snoop response qualifier to be specified use an
191additional qualifier
192.Dq Li snoopresponse= Ns Ar response ,
193where argument
194.Ar response
195comprises of the following keywords separated by
196.Dq +
197signs:
198.Bl -tag -width indent
199.It Li clean
200Measure CLEAN responses.
201.It Li hit
202Measure HIT responses.
203.It Li hitm
204Measure HITM responses.
205.El
206.Pp
207The default is to measure all the above responses.
208.Pp
209Events that require a snoop type qualifier use an additional qualifier
210.Dq Li snooptype= Ns Ar type ,
211where argument
212.Ar type
213comprises the one of the following keywords:
214.Bl -tag -width indent
215.It Li cmp2i
216Measure CMP2I snoops.
217.It Li cmp2s
218Measure CMP2S snoops.
219.El
220.Pp
221The default is to measure both snoops.
222.Ss Event Specifiers (Programmable PMCs)
223Atom programmable PMCs support the following events:
224.Bl -tag -width indent
225.It Li BACLEARS
226.Pq Event E6H , Umask 01H
227The number of times the front end is resteered.
228.It Li BOGUS_BR
229.Pq Event E4H , Umask 00H
230The number of byte sequences mistakenly detected as taken branch
231instructions.
232.It Li BR_BAC_MISSP_EXEC
233.Pq Event 8AH , Umask 00H
234The number of branch instructions that were mispredicted when
235decoded.
236.It Li BR_CALL_MISSP_EXEC
237.Pq Event 93H , Umask 00H
238The number of mispredicted
239.Li CALL
240instructions that were executed.
241.It Li BR_CALL_EXEC
242.Pq Event 92H , Umask 00H
243The number of
244.Li CALL
245instructions executed.
246.It Li BR_CND_EXEC
247.Pq Event 8BH , Umask 00H
248The number of conditional branches executed, but not necessarily retired.
249.It Li BR_CND_MISSP_EXEC
250.Pq Event 8CH , Umask 00H
251The number of mispredicted conditional branches executed.
252.It Li BR_IND_CALL_EXEC
253.Pq Event 94H , Umask 00H
254The number of indirect
255.Li CALL
256instructions executed.
257.It Li BR_IND_EXEC
258.Pq Event 8DH , Umask 00H
259The number of indirect branch instructions executed.
260.It Li BR_IND_MISSP_EXEC
261.Pq Event 8EH , Umask 00H
262The number of mispredicted indirect branch instructions executed.
263.It Li BR_INST_DECODED
264.Pq Event E0H , Umask 01H
265The number of branch instructions decoded.
266.It Li BR_INST_EXEC
267.Pq Event 88H , Umask 00H
268The number of branches executed, but not necessarily retired.
269.It Li BR_INST_RETIRED.ANY
270.Pq Event C4H , Umask 00H
271.Pq Alias Qq "Branch Instruction Retired"
272The number of branch instructions retired.
273This is an architectural performance event.
274.It Li BR_INST_RETIRED.ANY1
275.Pq Event C4H , Umask 0FH
276The number of branch instructions retired that were mispredicted.
277.It Li BR_INST_RETIRED.MISPRED
278.Pq Event C5H , Umask 00H
279.Pq Alias Qq "Branch Misses Retired"
280The number of mispredicted branch instructions retired.
281This is an architectural performance event.
282.It Li BR_INST_RETIRED.MISPRED_NOT_TAKEN
283.Pq Event C4H , Umask 02H
284The number of not taken branch instructions retired that were
285mispredicted.
286.It Li BR_INST_RETIRED.MISPRED_TAKEN
287.Pq Event C4H , Umask 08H
288The number taken branch instructions retired that were mispredicted.
289.It Li BR_INST_RETIRED.PRED_NOT_TAKEN
290.Pq Event C4H , Umask 01H
291The number of not taken branch instructions retired that were
292correctly predicted.
293.It Li BR_INST_RETIRED.PRED_TAKEN
294.Pq Event C4H , Umask 04H
295The number of taken branch instructions retired that were correctly
296predicted.
297.It Li BR_INST_RETIRED.TAKEN
298.Pq Event C4H , Umask 0CH
299The number of taken branch instructions retired.
300.It Li BR_MISSP_EXEC
301.Pq Event 89H , Umask 00H
302The number of mispredicted branch instructions that were executed.
303.It Li BR_RET_MISSP_EXEC
304.Pq Event 90H , Umask 00H
305The number of mispredicted
306.Li RET
307instructions executed.
308.It Li BR_RET_BAC_MISSP_EXEC
309.Pq Event 91H , Umask 00H
310The number of
311.Li RET
312instructions executed that were mispredicted at decode time.
313.It Li BR_RET_EXEC
314.Pq Event 8FH , Umask 00H
315The number of
316.Li RET
317instructions executed.
318.It Li BR_TKN_BUBBLE_1
319.Pq Event 97H , Umask 00H
320The number of branch predicted taken with bubble 1.
321.It Li BR_TKN_BUBBLE_2
322.Pq Event 98H , Umask 00H
323The number of branch predicted taken with bubble 2.
324.It Li BUSQ_EMPTY Op ,core= Ns Ar core
325.Pq Event 7DH
326The number of cycles during which the core did not have any pending
327transactions in the bus queue.
328.It Li BUS_BNR_DRV Op ,agent= Ns Ar agent
329.Pq Event 61H
330The number of Bus Not Ready signals asserted on the bus.
331This event is thread-independent.
332.It Li BUS_DATA_RCV Op ,core= Ns Ar core
333.Pq Event 64H
334The number of bus cycles during which the processor is receiving data.
335This event is thread-independent.
336.It Li BUS_DRDY_CLOCKS Op ,agent= Ns Ar agent
337.Pq Event 62H
338The number of bus cycles during which the Data Ready signal is asserted
339on the bus.
340This event is thread-independent.
341.It Li BUS_HIT_DRV Op ,agent= Ns Ar agent
342.Pq Event 7AH
343The number of bus cycles during which the processor drives the
344.Li HIT#
345pin.
346This event is thread-independent.
347.It Li BUS_HITM_DRV Op ,agent= Ns Ar agent
348.Pq Event 7BH
349The number of bus cycles during which the processor drives the
350.Li HITM#
351pin.
352This event is thread-independent.
353.It Li BUS_IO_WAIT Op ,core= Ns Ar core
354.Pq Event 7FH
355The number of core cycles during which I/O requests wait in the bus
356queue.
357.It Li BUS_LOCK_CLOCKS Xo
358.Op ,agent= Ns Ar agent
359.Op ,core= Ns Ar core
360.Xc
361.Pq Event 63H
362The number of bus cycles during which the
363.Li LOCK
364signal was asserted on the bus.
365This event is thread independent.
366.It Li BUS_REQUEST_OUTSTANDING Xo
367.Op ,agent= Ns Ar agent
368.Op ,core= Ns Ar core
369.Xc
370.Pq Event 60H
371The number of pending full cache line read transactions on the bus
372occurring in each cycle.
373This event is thread independent.
374.It Li BUS_TRANS_P Xo
375.Op ,agent= Ns Ar agent
376.Op ,core= Ns Ar core
377.Xc
378.Pq Event 6BH
379The number of partial bus transactions.
380.It Li BUS_TRANS_IFETCH Xo
381.Op ,agent= Ns Ar agent
382.Op ,core= Ns Ar core
383.Xc
384.Pq Event 68H
385The number of instruction fetch full cache line bus transactions.
386.It Li BUS_TRANS_INVAL Xo
387.Op ,agent= Ns Ar agent
388.Op ,core= Ns Ar core
389.Xc
390.Pq Event 69H
391The number of invalidate bus transactions.
392.It Li BUS_TRANS_PWR Xo
393.Op ,agent= Ns Ar agent
394.Op ,core= Ns Ar core
395.Xc
396.Pq Event 6AH
397The number of partial write bus transactions.
398.It Li BUS_TRANS_DEF Xo
399.Op ,agent= Ns Ar agent
400.Op ,core= Ns Ar core
401.Xc
402.Pq Event 6DH
403The number of deferred bus transactions.
404.It Li BUS_TRANS_BURST Xo
405.Op ,agent= Ns Ar agent
406.Op ,core= Ns Ar core
407.Xc
408.Pq Event 6EH
409The number of burst transactions.
410.It Li BUS_TRANS_MEM Xo
411.Op ,agent= Ns Ar agent
412.Op ,core= Ns Ar core
413.Xc
414.Pq Event 6FH
415The number of memory bus transactions.
416.It Li BUS_TRANS_ANY Xo
417.Op ,agent= Ns Ar agent
418.Op ,core= Ns Ar core
419.Xc
420.Pq Event 70H
421The number of bus transactions of any kind.
422.It Li BUS_TRANS_BRD Xo
423.Op ,agent= Ns Ar agent
424.Op ,core= Ns Ar core
425.Xc
426.Pq Event 65H
427The number of burst read transactions.
428.It Li BUS_TRANS_IO Xo
429.Op ,agent= Ns Ar agent
430.Op ,core= Ns Ar core
431.Xc
432.Pq Event 6CH
433The number of completed I/O bus transactions due to
434.Li IN
435and
436.Li OUT
437instructions.
438.It Li BUS_TRANS_RFO Xo
439.Op ,agent= Ns Ar agent
440.Op ,core= Ns Ar core
441.Xc
442.Pq Event 66H
443The number of Read For Ownership bus transactions.
444.It Li BUS_TRANS_WB Xo
445.Op ,agent= Ns Ar agent
446.Op ,core= Ns Ar core
447.Xc
448.Pq Event 67H
449The number explicit write-back bus transactions due to dirty line
450evictions.
451.It Li CMP_SNOOP Xo
452.Op ,core= Ns Ar core
453.Op ,snooptype= Ns Ar snoop
454.Xc
455.Pq Event 78H
456The number of times the L1 data cache is snooped by the other core in
457the same processor.
458.It Li CPU_CLK_UNHALTED.BUS
459.Pq Event 3CH , Umask 01H
460.Pq Alias Qq "Unhalted Reference Cycles"
461The number of bus cycles when the core is not in the halt state.
462This is an architectural performance event.
463.It Li CPU_CLK_UNHALTED.CORE_P
464.Pq Event 3CH , Umask 00H
465.Pq Alias Qq "Unhalted Core Cycles"
466The number of core cycles while the core is not in a halt state.
467This is an architectural performance event.
468.It Li CPU_CLK_UNHALTED.NO_OTHER
469.Pq Event 3CH , Umask 02H
470The number of bus cycles during which the core remains unhalted and
471the other core is halted.
472.It Li CYCLES_DIV_BUSY
473.Pq Event 14H , Umask 01H
474The number of cycles the divider is busy.
475.It Li CYCLES_INT_MASKED.CYCLES_INT_MASKED
476.Pq Event C6H , Umask 01H
477The number of cycles during which interrupts are disabled.
478.It Li CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED
479.Pq Event C6H , Umask 02H
480The number of cycles during which there were pending interrupts while
481interrupts were disabled.
482.It Li CYCLES_L1I_MEM_STALLED
483.Pq Event 86H , Umask 00H
484The number of cycles for which an instruction fetch stalls.
485.It Li DATA_TLB_MISSES.DTLB_MISS
486.Pq Event 08H , Umask 07H
487The number of memory access that missed the Data TLB
488.It Li DATA_TLB_MISSES.DTLB_MISS_LD
489.Pq Event 08H , Umask 05H
490The number of loads that missed the Data TLB.
491.It Li DATA_TLB_MISSES.DTLB_MISS_ST
492.Pq Event 08H , Umask 06H
493The number of stores that missed the Data TLB.
494.It Li DATA_TLB_MISSES.UTLB_MISS_LD
495.Pq Event 08H , Umask 09H
496The number of loads that missed the UTLB.
497.It Li DELAYED_BYPASS.FP
498.Pq Event 19H , Umask 00H
499The number of floating point operations that used data immediately
500after the data was generated by a non floating point execution unit.
501.It Li DELAYED_BYPASS.LOAD
502.Pq Event 19H , Umask 01H
503The number of delayed bypass penalty cycles that a load operation incurred.
504.It Li DELAYED_BYPASS.SIMD
505.Pq Event 19H , Umask 02H
506The number of times SIMD operations use data immediately after data,
507was generated by a non-SIMD execution unit.
508.It Li DIV
509.Pq Event 13H , Umask 00H
510The number of divide operations executed.
511This event is only available on PMC1.
512.It Li DIV.AR
513.Pq Event 13H , Umask 81H
514The number of divide operations retired.
515.It Li DIV.S
516.Pq Event 13H , Umask 01H
517The number of divide operations executed.
518.It Li DTLB_MISSES.ANY
519.Pq Event 08H , Umask 01H
520The number of Data TLB misses, including misses that result from
521speculative accesses.
522.It Li DTLB_MISSES.L0_MISS_LD
523.Pq Event 08H , Umask 04H
524The number of level 0 DTLB misses due to load operations.
525.It Li DTLB_MISSES.MISS_LD
526.Pq Event 08H , Umask 02H
527The number of Data TLB misses due to load operations.
528.It Li DTLB_MISSES.MISS_ST
529.Pq Event 08H , Umask 08H
530The number of Data TLB misses due to store operations.
531.It Li EIST_TRANS
532.Pq Event 3AH , Umask 00H
533The number of Enhanced Intel SpeedStep Technology transitions.
534.It Li ESP.ADDITIONS
535.Pq Event ABH , Umask 02H
536The number of automatic additions to the
537.Li %esp
538register.
539.It Li ESP.SYNCH
540.Pq Event ABH , Umask 01H
541The number of times the
542.Li %esp
543register was explicitly used in an address expression after
544it is implicitly used by a
545.Li PUSH
546or
547.Li POP
548instruction.
549.It Li EXT_SNOOP Xo
550.Op ,agent= Ns Ar agent
551.Op ,snoopresponse= Ns Ar response
552.Xc
553.Pq Event 77H
554The number of snoop responses to bus transactions.
555.It Li FP_ASSIST
556.Pq Event 11H , Umask 01H
557The number of floating point operations executed that needed
558a microcode assist, including speculatively executed instructions.
559.It Li FP_ASSIST.AR
560.Pq Event 11H , Umask 81H
561The number of floating point operations retired that needed
562a microcode assist.
563.It Li FP_COMP_OPS_EXE
564.Pq Event 10H , Umask 00H
565The number of floating point computational micro-ops executed.
566The event is available only on PMC0.
567.It Li FP_MMX_TRANS_TO_FP
568.Pq Event CCH , Umask 02H
569The number of transitions from MMX instructions to floating point
570instructions.
571.It Li FP_MMX_TRANS_TO_MMX
572.Pq Event CCH , Umask 01H
573The number of transitions from floating point instructions to MMX
574instructions.
575.It Li HW_INT_RCV
576.Pq Event C8H , Umask 00H
577The number of hardware interrupts received.
578.It Li ICACHE.ACCESSES
579.Pq Event 80H , Umask 03H
580The number of instruction fetches.
581.It Li ICACHE.MISSES
582.Pq Event 80H , Umask 02H
583The number of instruction fetches that miss the instruction cache.
584.It Li IDLE_DURING_DIV
585.Pq Event 18H , Umask 00H
586The number of cycles the divider is busy and no other execution unit
587or load operation was in progress.
588This event is available only on PMC0.
589.It Li ILD_STALL
590.Pq Event 87H , Umask 00H
591The number of cycles the instruction length decoder stalled due to a
592length changing prefix.
593.It Li INST_QUEUE.FULL
594.Pq Event 83H , Umask 02H
595The number of cycles during which the instruction queue is full.
596.It Li INST_RETIRED.ANY_P
597.Pq Event C0H , Umask 00H
598.Pq Alias Qq "Instruction Retired"
599The number of instructions retired.
600This is an architectural performance event.
601.It Li INST_RETIRED.LOADS
602.Pq Event C0H , Umask 01H
603The number of instructions retired that contained a load operation.
604.It Li INST_RETIRED.OTHER
605.Pq Event C0H , Umask 04H
606The number of instructions retired that did not contain a load or a
607store operation.
608.It Li INST_RETIRED.STORES
609.Pq Event C0H , Umask 02H
610The number of instructions retired that contained a store operation.
611.It Li ITLB.FLUSH
612.Pq Event 82H , Umask 04H
613The number of ITLB flushes.
614.It Li ITLB.LARGE_MISS
615.Pq Event 82H , Umask 10H
616The number of instruction fetches from large pages that miss the
617ITLB.
618.It Li ITLB.MISSES
619.Pq Event 82H , Umask 02H
620The number of instruction fetches from both large and small pages that
621miss the ITLB.
622.It Li ITLB.SMALL_MISS
623.Pq Event 82H , Umask 02H
624The number of instruction fetches from small pages that miss the ITLB.
625.It Li ITLB_MISS_RETIRED
626.Pq Event C9H , Umask 00H
627The number of retired instructions that missed the ITLB when they were
628fetched.
629.It Li L1D_ALL_REF
630.Pq Event 43H , Umask 01H
631The number of references to L1 data cache counting loads and stores of
632to all memory types.
633.It Li L1D_ALL_CACHE_REF
634.Pq Event 43H , Umask 02H
635The number of data reads and writes to cacheable memory.
636.It Li L1D_CACHE_LOCK Op ,cachestate= Ns Ar state
637.Pq Event 42H
638The number of locked reads from cacheable memory.
639.It Li L1D_CACHE_LOCK_DURATION
640.Pq Event 42H , Umask 10H
641The number of cycles during which any cache line is locked by any
642locking instruction.
643.It Li L1D_CACHE.LD
644.Pq Event 40H , Umask 21H
645The number of data reads from cacheable memory.
646.It Li L1D_CACHE.ST
647.Pq Event 41H , Umask 22H
648The number of data writes to cacheable memory.
649.It Li L1D_M_EVICT
650.Pq Event 47H , Umask 00H
651The number of modified cache lines evicted from L1 data cache.
652.It Li L1D_M_REPL
653.Pq Event 46H , Umask 00H
654The number of modified lines allocated in L1 data cache.
655.It Li L1D_PEND_MISS
656.Pq Event 48H , Umask 00H
657The total number of outstanding L1 data cache misses at any clock.
658.It Li L1D_PREFETCH.REQUESTS
659.Pq Event 4EH , Umask 10H
660The number of times L1 data cache requested to prefetch a data cache
661line.
662.It Li L1D_REPL
663.Pq Event 45H , Umask 0FH
664The number of lines brought into L1 data cache.
665.It Li L1D_SPLIT.LOADS
666.Pq Event 49H , Umask 01H
667The number of load operations that span two cache lines.
668.It Li L1D_SPLIT.STORES
669.Pq Event 49H , Umask 02H
670The number of store operations that span two cache lines.
671.It Li L1I_MISSES
672.Pq Event 81H , Umask 00H
673The number of instruction fetch unit misses.
674.It Li L1I_READS
675.Pq Event 80H , Umask 00H
676The number of instruction fetches.
677.It Li L2_ADS Op ,core= Ns core
678.Pq Event 21H
679The number of cycles that the L2 address bus is in use.
680.It Li L2_DBUS_BUSY_RD Op ,core= Ns core
681.Pq Event 23H
682The number of core cycles during which the L2 data bus is busy
683transferring data to the core.
684.It Li L2_IFETCH Xo
685.Op ,cachestate= Ns Ar state
686.Op ,core= Ns Ar core
687.Xc
688.Pq Event 28H
689The number of instruction cache line requests from the instruction
690fetch unit.
691.It Li L2_LD Xo
692.Op ,cachestate= Ns Ar state
693.Op ,core= Ns Ar core
694.Op ,prefetch= Ns Ar prefetch
695.Xc
696.Pq Event 29H
697The number of L2 cache read requests from L1 cache and L2
698prefetchers.
699.It Li L2_LINES_IN Xo
700.Op ,core= Ns Ar core
701.Op ,prefetch= Ns Ar prefetch
702.Xc
703.Pq Event 24H
704The number of cache lines allocated in L2 cache.
705.It Li L2_LINES_OUT Xo
706.Op ,core= Ns Ar core
707.Op ,prefetch= Ns Ar prefetch
708.Xc
709.Pq Event 26H
710The number of L2 cache lines evicted.
711.It Li L2_LOCK Xo
712.Op ,cachestate= Ns Ar state
713.Op ,core= Ns Ar core
714.Xc
715.Pq Event 2BH
716The number of locked accesses to cache lines that miss L1 data
717cache.
718.It Li L2_M_LINES_IN Op ,core= Ns Ar core
719.Pq Event 25H
720The number of L2 cache line modifications.
721.It Li L2_M_LINES_OUT Xo
722.Op ,core= Ns Ar core
723.Op ,prefetch= Ns Ar prefetch
724.Xc
725.Pq Event 27H
726The number of modified lines evicted from L2 cache.
727.It Li L2_NO_REQ Op ,core= Ns Ar core
728.Pq Event 32H
729The number of cycles during which no L2 cache requests were pending
730from a core.
731.It Li L2_REJECT_BUSQ Xo
732.Op ,cachestate= Ns Ar state
733.Op ,core= Ns Ar core
734.Op ,prefetch= Ns Ar prefetch
735.Xc
736.Pq Event 30H
737The number of L2 cache requests that were rejected.
738.It Li L2_RQSTS Xo
739.Op ,cachestate= Ns Ar state
740.Op ,core= Ns Ar core
741.Op ,prefetch= Ns Ar prefetch
742.Xc
743.Pq Event 2EH
744The number of completed L2 cache requests.
745.It Li L2_RQSTS.SELF.DEMAND.I_STATE
746.Pq Event 2EH , Umask 41H
747.Pq Alias Qq "LLC Misses"
748The number of completed L2 cache demand requests from this core that
749missed the L2 cache.
750This is an architectural performance event.
751.It Li L2_RQSTS.SELF.DEMAND.MESI
752.Pq Event 2EH , Umask 4FH
753.Pq Alias Qq "LLC References"
754The number of completed L2 cache demand requests from this core.
755.It Li L2_ST Xo
756.Op ,cachestate= Ns Ar state
757.Op ,core= Ns Ar core
758.Xc
759.Pq Event 2AH
760The number of store operations that miss the L1 cache and request data
761from the L2 cache.
762.It Li LOAD_BLOCK.L1D
763.Pq Event 03H , Umask 20H
764The number of loads blocked by the L1 data cache.
765.It Li LOAD_BLOCK.OVERLAP_STORE
766.Pq Event 03H , Umask 08H
767The number of loads that partially overlap an earlier store or are
768aliased with a previous store.
769.It Li LOAD_BLOCK.STA
770.Pq Event 03H , Umask 02H
771The number of loads blocked by preceding stores whose address is yet
772to be calculated.
773.It Li LOAD_BLOCK.STD
774.Pq Event 03H , Umask 04H
775The number of loads blocked by preceding stores to the same address
776whose data value is not known.
777.It Li LOAD_BLOCK.UNTIL_RETIRE
778.Pq Event 03H , Umask 10H
779The number of load operations that were blocked until retirement.
780.It Li LOAD_HIT_PRE
781.Pq Event 4CH , Umask 00H
782The number of load operations that conflicted with an prefetch to the
783same cache line.
784.It Li MACHINE_CLEARS.SMC
785.Pq Event C3H , Umask 01H
786The number of times a program writes to a code section.
787.It Li MACHINE_NUKES.MEM_ORDER
788.Pq Event C3H , Umask 04H
789The number of times the execution pipeline was restarted due to a
790memory ordering conflict or memory disambiguation misprediction.
791.It Li MACRO_INSTS.ALL_DECODED
792.Pq Event AAH , Umask 03H
793The number of instructions decoded.
794.It Li MACRO_INSTS.CISC_DECODED
795.Pq Event AAH , Umask 02H
796The number of complex instructions decoded.
797.It Li MEMORY_DISAMBIGUATION.RESET
798.Pq Event 09H , Umask 01H
799The number of cycles during which memory disambiguation misprediction
800occurs.
801.It Li MEMORY_DISAMBIGUATION.SUCCESS
802.Pq Event 09H , Umask 02H
803The number of load operations that were successfully disambiguated.
804.It Li MEM_LOAD_RETIRED.DTLB_MISS
805.Pq Event CBH , Umask 04H
806The number of retired load operations that missed the DTLB.
807.It Li MEM_LOAD_RETIRED.L2_MISS
808.Pq Event CBH , Umask 02H
809The number of retired load operations that miss L2 cache.
810.It Li MEM_LOAD_RETIRED.L2_HIT
811.Pq Event CBH , Umask 01H
812The number of retired load operations that hit L2 cache.
813.It Li MEM_LOAD_RETIRED.L2_LINE_MISS
814.Pq Event CBH , Umask 08H
815The number of load operations that missed L2 cache and that caused a
816bus request.
817.It Li MUL
818.Pq Event 12H , Umask 00H
819The number of multiply operations executed.
820This event is only available on PMC1.
821.It Li MUL.AR
822.Pq Event 12H , Umask 81H
823The number of multiply operations retired.
824.It Li MUL.S
825.Pq Event 12H , Umask 01H
826The number of multiply operations executed.
827.It Li PAGE_WALKS.WALKS
828.Pq Event 0CH , Umask 03H
829The number of page walks executed due to an ITLB or DTLB miss.
830.It Li PAGE_WALKS.CYCLES
831.Pq Event 0CH , Umask 03H
832.\" XXX Clarify.  Identical event umask/event numbers.
833The number of cycles spent in a page walk caused by an ITLB or DTLB
834miss.
835.It Li PREF_RQSTS_DN
836.Pq Event F8H , Umask 00H
837The number of downward prefetches issued from the Data Prefetch Logic
838unit to L2 cache.
839.It Li PREF_RQSTS_UP
840.Pq Event F0H , Umask 00H
841The number of upward prefetches issued from the Data Prefetch Logic
842unit to L2 cache.
843.It Li PREFETCH.PREFETCHNTA
844.Pq Event 07H , Umask 08H
845The number of
846.Li PREFETCHNTA
847instructions executed.
848.It Li PREFETCH.PREFETCHT0
849.Pq Event 07H , Umask 01H
850The number of
851.Li PREFETCHT0
852instructions executed.
853.It Li PREFETCH.SW_L2
854.Pq Event 07H , Umask 06H
855The number of
856.Li PREFETCHT1
857and
858.Li PREFETCHT2
859instructions executed.
860.It Li RAT_STALLS.ANY
861.Pq Event D2H , Umask 0FH
862The number of stall cycles due to any of
863.Li RAT_STALLS.FLAGS
864.Li RAT_STALLS.FPSW ,
865.Li RAT_STALLS.PARTIAL
866and
867.Li RAT_STALLS.ROB_READ_PORT .
868.It Li RAT_STALLS.FLAGS
869.Pq Event D2H , Umask 04H
870The number of cycles execution stalled due to a flag register induced
871stall.
872.It Li RAT_STALLS.FPSW
873.Pq Event D2H , Umask 08H
874The number of times the floating point status word was written.
875.It Li RAT_STALLS.PARTIAL_CYCLES
876.Pq Event D2H , Umask 02H
877The number of cycles of added instruction execution latency due to the
878use of a register that was partially written by previous instructions.
879.It Li RAT_STALLS.ROB_READ_PORT
880.Pq Event D2H , Umask 01H
881The number of cycles when ROB read port stalls occurred.
882.It Li RESOURCE_STALLS.ANY
883.Pq Event DCH , Umask 1FH
884The number of cycles during which any resource related stall
885occurred.
886.It Li RESOURCE_STALLS.BR_MISS_CLEAR
887.Pq Event DCH , Umask 10H
888The number of cycles stalled due to branch misprediction.
889.It Li RESOURCE_STALLS.FPCW
890.Pq Event DCH , Umask 08H
891The number of cycles stalled due to writing the floating point control
892word.
893.It Li RESOURCE_STALLS.LD_ST
894.Pq Event DCH , Umask 04H
895The number of cycles during which the number of loads and stores in
896the pipeline exceeded their limits.
897.It Li RESOURCE_STALLS.ROB_FULL
898.Pq Event DCH , Umask 01H
899The number of cycles when the reorder buffer was full.
900.It Li RESOURCE_STALLS.RS_FULL
901.Pq Event DCH , Umask 02H
902The number of cycles during which the RS was full.
903.It Li RS_UOPS_DISPATCHED
904.Pq Event A0H , Umask 00H
905The number of micro-ops dispatched for execution.
906.It Li RS_UOPS_DISPATCHED.PORT0
907.Pq Event A1H , Umask 01H
908The number of cycles micro-ops were dispatched for execution on port
9090.
910.It Li RS_UOPS_DISPATCHED.PORT1
911.Pq Event A1H , Umask 02H
912The number of cycles micro-ops were dispatched for execution on port
9131.
914.It Li RS_UOPS_DISPATCHED.PORT2
915.Pq Event A1H , Umask 04H
916The number of cycles micro-ops were dispatched for execution on port
9172.
918.It Li RS_UOPS_DISPATCHED.PORT3
919.Pq Event A1H , Umask 08H
920The number of cycles micro-ops were dispatched for execution on port
9213.
922.It Li RS_UOPS_DISPATCHED.PORT4
923.Pq Event A1H , Umask 10H
924The number of cycles micro-ops were dispatched for execution on port
9254.
926.It Li RS_UOPS_DISPATCHED.PORT5
927.Pq Event A1H , Umask 20H
928The number of cycles micro-ops were dispatched for execution on port
9295.
930.It Li SB_DRAIN_CYCLES
931.Pq Event 04H , Umask 01H
932The number of cycles while the store buffer is draining.
933.It Li SEGMENT_REG_LOADS.ANY
934.Pq Event 06H , Umask 00H
935The number of segment register loads.
936.It Li SEG_REG_RENAMES.ANY
937.Pq Event D5H , Umask 0FH
938The number of times the any segment register was renamed.
939.It Li SEG_REG_RENAMES.DS
940.Pq Event D5H , Umask 02H
941The number of times the
942.Li %ds
943register is renamed.
944.It Li SEG_REG_RENAMES.ES
945.Pq Event D5H , Umask 01H
946The number of times the
947.Li %es
948register is renamed.
949.It Li SEG_REG_RENAMES.FS
950.Pq Event D5H , Umask 04H
951The number of times the
952.Li %fs
953register is renamed.
954.It Li SEG_REG_RENAMES.GS
955.Pq Event D5H , Umask 08H
956The number of times the
957.Li %gs
958register is renamed.
959.It Li SEG_RENAME_STALLS.ANY
960.Pq Event D4H , Umask 0FH
961The number of stalls due to lack of resource to rename any segment
962register.
963.It Li SEG_RENAME_STALLS.DS
964.Pq Event D4H , Umask 02H
965The number of stalls due to lack of renaming resources for the
966.Li %ds
967register.
968.It Li SEG_RENAME_STALLS.ES
969.Pq Event D4H , Umask 01H
970The number of stalls due to lack of renaming resources for the
971.Li %es
972register.
973.It Li SEG_RENAME_STALLS.FS
974.Pq Event D4H , Umask 04H
975The number of stalls due to lack of renaming resources for the
976.Li %fs
977register.
978.It Li SEG_RENAME_STALLS.GS
979.Pq Event D4H , Umask 08H
980The number of stalls due to lack of renaming resources for the
981.Li %gs
982register.
983.It Li SIMD_ASSIST
984.Pq Event CDH , Umask 00H
985The number SIMD assists invoked.
986.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
987.Pq Event CAH , Umask 04H
988Then number of computational SSE2 packed double precision instructions
989retired.
990.It Li SIMD_COMP_INST_RETIRED.PACKED_SINGLE
991.Pq Event CAH , Umask 01H
992Then number of computational SSE2 packed single precision instructions
993retired.
994.It Li SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE
995.Pq Event CAH , Umask 08H
996Then number of computational SSE2 scalar double precision instructions
997retired.
998.It Li SIMD_COMP_INST_RETIRED.SCALAR_SINGLE
999.Pq Event CAH , Umask 02H
1000Then number of computational SSE2 scalar single precision instructions
1001retired.
1002.It Li SIMD_INSTR_RETIRED
1003.Pq Event CEH , Umask 00H
1004The number of retired SIMD instructions that use MMX registers.
1005.It Li SIMD_INST_RETIRED.ANY
1006.Pq Event C7H , Umask 1FH
1007The number of streaming SIMD instructions retired.
1008.It Li SIMD_INST_RETIRED.PACKED_DOUBLE
1009.Pq Event C7H , Umask 04H
1010The number of SSE2 packed double precision instructions retired.
1011.It Li SIMD_INST_RETIRED.PACKED_SINGLE
1012.Pq Event C7H , Umask 01H
1013The number of SSE packed single precision instructions retired.
1014.It Li SIMD_INST_RETIRED.SCALAR_DOUBLE
1015.Pq Event C7H , Umask 08H
1016The number of SSE2 scalar double precision instructions retired.
1017.It Li SIMD_INST_RETIRED.SCALAR_SINGLE
1018.Pq Event C7H , Umask 02H
1019The number of SSE scalar single precision instructions retired.
1020.It Li SIMD_INST_RETIRED.VECTOR
1021.Pq Event C7H , Umask 10H
1022The number of SSE2 vector instructions retired.
1023.It Li SIMD_SAT_INSTR_RETIRED
1024.Pq Event CFH , Umask 00H
1025The number of saturated arithmetic SIMD instructions retired.
1026.It Li SIMD_SAT_UOP_EXEC.AR
1027.Pq Event B1H , Umask 80H
1028The number of SIMD saturated arithmetic micro-ops retired.
1029.It Li SIMD_SAT_UOP_EXEC.S
1030.Pq Event B1H , Umask 00H
1031The number of SIMD saturated arithmetic micro-ops executed.
1032.It Li SIMD_UOPS_EXEC.AR
1033.Pq Event B0H , Umask 80H
1034The number of SIMD micro-ops retired.
1035.It Li SIMD_UOPS_EXEC.S
1036.Pq Event B0H , Umask 00H
1037The number of SIMD micro-ops executed.
1038.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR
1039.Pq Event B3H , Umask A0H
1040The number of SIMD packed arithmetic micro-ops executed.
1041.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC.S
1042.Pq Event B3H , Umask 20H
1043The number of SIMD packed arithmetic micro-ops executed.
1044.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.AR
1045.Pq Event B3H , Umask 90H
1046The number of SIMD packed logical micro-ops executed.
1047.It Li SIMD_UOP_TYPE_EXEC.LOGICAL.S
1048.Pq Event B3H , Umask 10H
1049The number of SIMD packed logical micro-ops executed.
1050.It Li SIMD_UOP_TYPE_EXEC.MUL.AR
1051.Pq Event B3H , Umask 81H
1052The number of SIMD packed multiply micro-ops retired.
1053.It Li SIMD_UOP_TYPE_EXEC.MUL.S
1054.Pq Event B3H , Umask 01H
1055The number of SIMD packed multiply micro-ops executed.
1056.It Li SIMD_UOP_TYPE_EXEC.PACK.AR
1057.Pq Event B3H , Umask 84H
1058The number of SIMD pack micro-ops retired.
1059.It Li SIMD_UOP_TYPE_EXEC.PACK.S
1060.Pq Event B3H , Umask 04H
1061The number of SIMD pack micro-ops executed.
1062.It Li SIMD_UOP_TYPE_EXEC.SHIFT.AR
1063.Pq Event B3H , Umask 82H
1064The number of SIMD packed shift micro-ops retired.
1065.It Li SIMD_UOP_TYPE_EXEC.SHIFT.S
1066.Pq Event B3H , Umask 02H
1067The number of SIMD packed shift micro-ops executed.
1068.It Li SIMD_UOP_TYPE_EXEC.UNPACK.AR
1069.Pq Event B3H , Umask 88H
1070The number of SIMD unpack micro-ops executed.
1071.It Li SIMD_UOP_TYPE_EXEC.UNPACK.S
1072.Pq Event B3H , Umask 08H
1073The number of SIMD unpack micro-ops executed.
1074.It Li SNOOP_STALL_DRV Xo
1075.Op ,agent= Ns Ar agent
1076.Op ,core= Ns Ar core
1077.Xc
1078.Pq Event 7EH
1079The number of times the bus stalled for snoops.
1080This event is thread-independent.
1081.It Li SSE_PRE_EXEC.L2
1082.Pq Event 07H , Umask 02H
1083The number of
1084.Li PREFETCHT1
1085instructions executed.
1086.It Li SSE_PRE_EXEC.STORES
1087.Pq Event 07H , Umask 03H
1088The number of times SSE non-temporal store instructions were executed.
1089.It Li SSE_PRE_MISS.L1
1090.Pq Event 4BH , Umask 01H
1091The number of times the
1092.Li PREFETCHT0
1093instruction executed and missed all cache levels.
1094.It Li SSE_PRE_MISS.L2
1095.Pq Event 4BH , Umask 02H
1096The number of times the
1097.Li PREFETCHT1
1098instruction executed and missed all cache levels.
1099.It Li SSE_PRE_MISS.NTA
1100.Pq Event 4BH , Umask 00H
1101The number of times the
1102.Li PREFETCHNTA
1103instruction executed and missed all cache levels.
1104.It Li STORE_BLOCK.ORDER
1105.Pq Event 04H , Umask 02H
1106The number of cycles while a store was waiting for another store to be
1107globally observed.
1108.It Li STORE_BLOCK.SNOOP
1109.Pq Event 04H , Umask 08H
1110The number of cycles while a store was blocked due to a conflict with
1111an internal or external snoop.
1112.It Li STORE_FORWARDS.GOOD
1113.Pq Event 02H , Umask 81H
1114The number of times stored data was forwarded directly to a load.
1115.It Li THERMAL_TRIP
1116.Pq Event 3BH , Umask C0H
1117The number of thermal trips.
1118.It Li UOPS_RETIRED.LD_IND_BR
1119.Pq Event C2H , Umask 01H
1120The number of micro-ops retired that fused a load with another
1121operation.
1122.It Li UOPS_RETIRED.STD_STA
1123.Pq Event C2H , Umask 02H
1124The number of store address calculations that fused into one micro-op.
1125.It Li UOPS_RETIRED.MACRO_FUSION
1126.Pq Event C2H , Umask 04H
1127The number of times retired instruction pairs were fused into one
1128micro-op.
1129.It Li UOPS_RETIRED.FUSED
1130.Pq Event C2H , Umask 07H
1131The number of fused micro-ops retired.
1132.It Li UOPS_RETIRED.NON_FUSED
1133.Pq Event C2H , Umask 8H
1134The number of non-fused micro-ops retired.
1135.It Li UOPS_RETIRED.ANY
1136.Pq Event C2H , Umask 10H
1137The number of micro-ops retired.
1138.It Li X87_COMP_OPS_EXE.ANY.AR
1139.Pq Event 10H , Umask 81H
1140The number of x87 floating-point computational micro-ops retired.
1141.It Li X87_COMP_OPS_EXE.ANY.S
1142.Pq Event 10H , Umask 01H
1143The number of x87 floating-point computational micro-ops executed.
1144.It Li X87_OPS_RETIRED.ANY
1145.Pq Event C1H , Umask FEH
1146The number of floating point computational instructions retired.
1147.It Li X87_OPS_RETIRED.FXCH
1148.Pq Event C1H , Umask 01H
1149The number of
1150.Li FXCH
1151instructions retired.
1152.El
1153.Ss Event Name Aliases
1154The following table shows the mapping between the PMC-independent
1155aliases supported by
1156.Lb libpmc
1157and the underlying hardware events used on these CPUs.
1158.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" "PMC Class"
1159.It Em Alias Ta Em Event Ta Em PMC Class
1160.It Li branches Ta Li BR_INST_RETIRED.ANY Ta Li PMC_CLASS_IAP
1161.It Li branch-mispredicts Ta Li BR_INST_RETIRED.MISPRED Ta Li PMC_CLASS_IAP
1162.It Li ic-misses Ta Li ICACHE.MISSES Ta Li PMC_CLASS_IAP
1163.It Li instructions Ta Li INST_RETIRED.ANY_P Ta Li PMC_CLASS_IAF
1164.It Li interrupts Ta Li HW_INT_RCV Ta Li PMC_CLASS_IAP
1165.It Li unhalted-cycles Ta Li CPU_CLK_UNHALTED.CORE_P Ta Li PMC_CLASS_IAF
1166.El
1167.Sh SEE ALSO
1168.Xr pmc 3 ,
1169.Xr pmc.amd 3 ,
1170.Xr pmc.atomsilvermont 3 ,
1171.Xr pmc.core 3 ,
1172.Xr pmc.core2 3 ,
1173.Xr pmc.iaf 3 ,
1174.Xr pmc.soft 3 ,
1175.Xr pmc.tsc 3 ,
1176.Xr pmc_cpuinfo 3 ,
1177.Xr pmclog 3 ,
1178.Xr hwpmc 4
1179.Sh HISTORY
1180The
1181.Nm pmc
1182library first appeared in
1183.Fx 6.0 .
1184.Sh AUTHORS
1185The
1186.Lb libpmc
1187library was written by
1188.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
1189