1//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Intel Silvermont to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SLMModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 16 // instructions per cycle. 17 let IssueWidth = 2; 18 let MicroOpBufferSize = 32; // Based on the reorder buffer. 19 let LoadLatency = 3; 20 let MispredictPenalty = 10; 21 let PostRAScheduler = 1; 22 23 // For small loops, expand by a small factor to hide the backedge cost. 24 let LoopMicroOpBufferSize = 10; 25 26 // FIXME: SSE4 is unimplemented. This flag is set to allow 27 // the scheduler to assign a default model to unrecognized opcodes. 28 let CompleteModel = 0; 29} 30 31let SchedModel = SLMModel in { 32 33// Silvermont has 5 reservation stations for micro-ops 34def SLM_IEC_RSV0 : ProcResource<1>; 35def SLM_IEC_RSV1 : ProcResource<1>; 36def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } 37def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } 38def SLM_MEC_RSV : ProcResource<1>; 39 40// Many micro-ops are capable of issuing on multiple ports. 41def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; 42def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; 43 44def SLMDivider : ProcResource<1>; 45def SLMFPMultiplier : ProcResource<1>; 46def SLMFPDivider : ProcResource<1>; 47 48// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 49// cycles after the memory operand. 50def : ReadAdvance<ReadAfterLd, 3>; 51def : ReadAdvance<ReadAfterVecLd, 3>; 52def : ReadAdvance<ReadAfterVecXLd, 3>; 53def : ReadAdvance<ReadAfterVecYLd, 3>; 54 55def : ReadAdvance<ReadInt2Fpu, 0>; 56 57// Many SchedWrites are defined in pairs with and without a folded load. 58// Instructions with folded loads are usually micro-fused, so they only appear 59// as two micro-ops when queued in the reservation station. 60// This multiclass defines the resource usage for variants with and without 61// folded loads. 62multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW, 63 list<ProcResourceKind> ExePorts, 64 int Lat, list<int> Res = [1], int UOps = 1, 65 int LoadUOps = 0, int LoadLat = 3> { 66 // Register variant is using a single cycle on ExePort. 67 def : WriteRes<SchedRW, ExePorts> { 68 let Latency = Lat; 69 let ResourceCycles = Res; 70 let NumMicroOps = UOps; 71 } 72 73 // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to 74 // the latency (default = 3). 75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> { 76 let Latency = !add(Lat, LoadLat); 77 let ResourceCycles = !listconcat([1], Res); 78 let NumMicroOps = !add(UOps, LoadUOps); 79 } 80} 81 82// A folded store needs a cycle on MEC_RSV for the store data (using the same uop), 83// but it does not need an extra port cycle to recompute the address. 84def : WriteRes<WriteRMW, [SLM_MEC_RSV]> { let NumMicroOps = 0; } 85 86def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 87def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 88def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; } 89def : WriteRes<WriteMove, [SLM_IEC_RSV01]>; 90def : WriteRes<WriteZero, []>; 91defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>; 92 93// Load/store MXCSR. 94// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. 95def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 96def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; } 97 98// Treat misc copies as a move. 99def : InstRW<[WriteMove], (instrs COPY)>; 100 101defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>; 102defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>; 103 104defm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 5, [5], 3>; 105defm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 5, [5], 4, 1>; 106defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 4, [4], 2, 1>; 107defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 4, [4], 2, 1>; 108defm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 5, [5], 3, 1>; 109defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>; 110defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>; 111defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 7, [7], 3>; 112defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 5, [2]>; 113defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 5, [2]>; 114defm : X86WriteResUnsupported<WriteIMulH>; 115defm : X86WriteResUnsupported<WriteIMulHLd>; 116defm : X86WriteResPairUnsupported<WriteMULX32>; 117defm : X86WriteResPairUnsupported<WriteMULX64>; 118 119defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>; 120defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>; 121defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 122defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>; 123defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 124 125defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>; 126defm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>; 127defm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>; 128defm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>; 129 130defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>; 131defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>; 132defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 133defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 134 135defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>; 136defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>; 137 138defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>; 139defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move. 140def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>; 141def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> { 142 // FIXME Latency and NumMicrOps? 143 let ResourceCycles = [2,1]; 144} 145defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>; 146defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>; 147defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 1>; 148defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 4, [1,1,1], 7>; 149defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>; 150defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 1>; 151defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV0, SLM_IEC_RSV1, SLM_MEC_RSV], 3, [1,1,1], 7>; 152 153// This is for simple LEAs with one or two input operands. 154// The complex ones can only execute on port 1, and they require two cycles on 155// the port to read all inputs. We don't model that. 156def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>; 157 158// Bit counts. 159defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>; 160defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV0, SLM_IEC_RSV1], 10, [10,10], 10>; 161defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; 162defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; 163defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; 164 165// BMI1 BEXTR/BLS, BMI2 BZHI 166defm : X86WriteResPairUnsupported<WriteBEXTR>; 167defm : X86WriteResPairUnsupported<WriteBLS>; 168defm : X86WriteResPairUnsupported<WriteBZHI>; 169 170defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 171defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 172defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 173defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 174defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 175defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 176defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 177defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 0, 4>; 178 179// Scalar and vector floating point. 180defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>; 181defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>; 182defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>; 183def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; } 184def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 185def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 186def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 187def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 188def : WriteRes<WriteFStore, [SLM_MEC_RSV]>; 189def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>; 190def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>; 191def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>; 192def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>; 193def : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>; 194 195def : WriteRes<WriteFMaskedStore32, [SLM_MEC_RSV]>; 196def : WriteRes<WriteFMaskedStore32Y, [SLM_MEC_RSV]>; 197def : WriteRes<WriteFMaskedStore64, [SLM_MEC_RSV]>; 198def : WriteRes<WriteFMaskedStore64Y, [SLM_MEC_RSV]>; 199 200def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>; 201def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>; 202def : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>; 203defm : X86WriteResUnsupported<WriteFMoveZ>; 204defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>; 205 206defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>; 207defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>; 208defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>; 209defm : X86WriteResPairUnsupported<WriteFAddZ>; 210defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>; 211defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 4, [2]>; 212defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 4, [2]>; 213defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 214defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>; 215defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>; 216defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>; 217defm : X86WriteResPairUnsupported<WriteFCmpZ>; 218defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>; 219defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>; 220defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>; 221defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 222defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>; 223defm : SLMWriteResPair<WriteFComX, [SLM_FPC_RSV1], 3>; 224defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 225defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 226defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 227defm : X86WriteResPairUnsupported<WriteFMulZ>; 228defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 229defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>; 230defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>; 231defm : X86WriteResPairUnsupported<WriteFMul64Z>; 232defm : X86WriteResPairUnsupported<WriteFMA>; 233defm : X86WriteResPairUnsupported<WriteFMAX>; 234defm : X86WriteResPairUnsupported<WriteFMAY>; 235defm : X86WriteResPairUnsupported<WriteFMAZ>; 236defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>; 237defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39], 6, 1>; 238defm : X86WriteResPairUnsupported<WriteFDivY>; 239defm : X86WriteResPairUnsupported<WriteFDivZ>; 240defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>; 241defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69], 6, 1>; 242defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 243defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 244defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 4>; 245defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 9, [8], 5, 1>; 246defm : X86WriteResPairUnsupported<WriteFRcpY>; 247defm : X86WriteResPairUnsupported<WriteFRcpZ>; 248defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 4>; 249defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 9, [8], 5, 1>; 250defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 251defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 252defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0, SLMFPDivider], 20, [1,20]>; 253defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0, SLMFPDivider], 41, [1,40], 5, 1>; 254defm : X86WriteResPairUnsupported<WriteFSqrtY>; 255defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 256defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0, SLMFPDivider], 35, [1,35]>; 257defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0, SLMFPDivider], 71, [1,70], 5, 1>; 258defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 259defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 260defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>; 261defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 12, [8], 5, 1>; 262defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 15, [12], 9, 1>; 263defm : X86WriteResPairUnsupported<WriteDPPSY>; 264defm : X86WriteResPairUnsupported<WriteDPPSZ>; 265defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>; 266defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>; 267defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>; 268defm : X86WriteResPairUnsupported<WriteFRndZ>; 269defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>; 270defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>; 271defm : X86WriteResPairUnsupported<WriteFLogicZ>; 272defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>; 273defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>; 274defm : X86WriteResPairUnsupported<WriteFTestZ>; 275defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; 276defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>; 277defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 278defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>; 279defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>; 280defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 281defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; 282defm : X86WriteResPairUnsupported<WriteFBlendY>; 283defm : X86WriteResPairUnsupported<WriteFBlendZ>; 284defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>; 285defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 286defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 287defm : X86WriteResPairUnsupported<WriteFShuffle256>; 288defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 289 290// Conversion between integer and float. 291defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV0], 5>; 292defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV0], 5, [2]>; 293defm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV0], 5, [2]>; 294defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 295defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV0], 5>; 296defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV0], 5, [2]>; 297defm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV0], 5, [2]>; 298defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 299 300defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV0], 5, [2]>; 301defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV0], 5, [2]>; 302defm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV0], 5, [2]>; 303defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 304defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV0], 5, [2]>; 305defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV0], 5, [2]>; 306defm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV0], 5, [2]>; 307defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 308 309defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV0], 4, [2]>; 310defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV0], 5, [2]>; 311defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV0], 5, [2]>; 312defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 313defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV0], 4, [2]>; 314defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV0], 5, [2]>; 315defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV0], 5, [2]>; 316defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 317 318defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 319defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 320defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 321 322defm : X86WriteResUnsupported<WriteCvtPS2PH>; 323defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 324defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 325defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 326defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 327defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 328 329// Vector integer operations. 330def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } 331def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 332def : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 333def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; } 334def : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; } 335def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 336def : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 337def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>; 338def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>; 339def : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>; 340def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>; 341def : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>; 342def : WriteRes<WriteVecMaskedStore32, [SLM_MEC_RSV]>; 343def : WriteRes<WriteVecMaskedStore32Y, [SLM_MEC_RSV]>; 344def : WriteRes<WriteVecMaskedStore64, [SLM_MEC_RSV]>; 345def : WriteRes<WriteVecMaskedStore64Y, [SLM_MEC_RSV]>; 346def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; 347def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>; 348def : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>; 349defm : X86WriteResUnsupported<WriteVecMoveZ>; 350def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>; 351def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>; 352 353defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 2, [2], 2>; 354defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 2, [2], 2>; 355defm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 2, [2], 2>; 356defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 357defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>; 358defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>; 359defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>; 360defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 361defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>; 362defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 363defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 364 365defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; 366defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>; 367defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>; 368defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 369defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>; 370defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>; 371defm : X86WriteResPairUnsupported<WriteVecTestZ>; 372defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; 373defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>; 374defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>; 375defm : X86WriteResPairUnsupported<WriteVecALUZ>; 376defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; 377defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 5, [2]>; 378defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 5, [2]>; 379defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 380defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; 381defm : X86WriteResPairUnsupported<WritePMULLDY>; 382defm : X86WriteResPairUnsupported<WritePMULLDZ>; 383defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; 384defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>; 385defm : X86WriteResPairUnsupported<WriteShuffleZ>; 386defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>; 387defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>; 388defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 5, [5], 4, 1>; 389defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 390defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 391defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; 392defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>; 393defm : X86WriteResPairUnsupported<WriteBlendZ>; 394defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 4, [4], 2, 1>; 395defm : X86WriteResPairUnsupported<WriteVarBlendY>; 396defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 397defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7, [5], 3, 1>; 398defm : X86WriteResPairUnsupported<WriteMPSADY>; 399defm : X86WriteResPairUnsupported<WriteMPSADZ>; 400defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>; 401defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 5, [2]>; 402defm : X86WriteResPairUnsupported<WritePSADBWY>; 403defm : X86WriteResPairUnsupported<WritePSADBWZ>; 404defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>; 405defm : X86WriteResPairUnsupported<WriteShuffle256>; 406defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 407defm : X86WriteResPairUnsupported<WriteVPMOV256>; 408 409// Vector insert/extract operations. 410defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>; 411 412def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>; 413def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 414 let Latency = 4; 415 let NumMicroOps = 2; 416 let ResourceCycles = [1, 2]; 417} 418 419//////////////////////////////////////////////////////////////////////////////// 420// Horizontal add/sub instructions. 421//////////////////////////////////////////////////////////////////////////////// 422 423defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV1], 6, [6], 4, 1>; 424defm : X86WriteResPairUnsupported<WriteFHAddY>; 425defm : X86WriteResPairUnsupported<WriteFHAddZ>; 426defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 6, [6], 3, 1>; 427defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 6, [6], 3, 1>; 428defm : X86WriteResPairUnsupported<WritePHAddY>; 429defm : X86WriteResPairUnsupported<WritePHAddZ>; 430 431// String instructions. 432// Packed Compare Implicit Length Strings, Return Mask 433defm : SLMWriteResPair<WritePCmpIStrM, [SLM_FPC_RSV0], 13, [13], 5, 1>; 434 435// Packed Compare Explicit Length Strings, Return Mask 436defm : SLMWriteResPair<WritePCmpEStrM, [SLM_FPC_RSV0], 17, [17], 8, 1>; 437 438// Packed Compare Implicit Length Strings, Return Index 439defm : SLMWriteResPair<WritePCmpIStrI, [SLM_FPC_RSV0], 17, [17], 6, 1>; 440 441// Packed Compare Explicit Length Strings, Return Index 442defm : SLMWriteResPair<WritePCmpEStrI, [SLM_FPC_RSV0], 21, [21], 9, 1>; 443 444// MOVMSK Instructions. 445def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 446def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 447def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; } 448def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 449 450// AES Instructions. 451defm : SLMWriteResPair<WriteAESDecEnc, [SLM_FPC_RSV0], 8, [5]>; 452defm : SLMWriteResPair<WriteAESIMC, [SLM_FPC_RSV0], 8, [5]>; 453defm : SLMWriteResPair<WriteAESKeyGen, [SLM_FPC_RSV0], 8, [5]>; 454 455// Carry-less multiplication instructions. 456defm : SLMWriteResPair<WriteCLMul, [SLM_FPC_RSV0], 10, [10], 8, 1>; 457 458def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; } 459def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; } 460def : WriteRes<WriteFence, [SLM_MEC_RSV]>; 461def : WriteRes<WriteNop, []>; 462 463// Remaining SLM instrs. 464 465def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> { 466 let Latency = 4; 467 let NumMicroOps = 2; 468 let ResourceCycles = [8]; 469} 470def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr, 471 MMX_PSUBQrr, PSUBQrr, 472 PCMPEQQrr)>; 473 474def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> { 475 let Latency = 7; 476 let NumMicroOps = 3; 477 let ResourceCycles = [1,8]; 478} 479def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm, 480 MMX_PSUBQrm, PSUBQrm, 481 PCMPEQQrm)>; 482 483/////////////////////////////////////////////////////////////////////////////// 484// Dependency breaking instructions. 485/////////////////////////////////////////////////////////////////////////////// 486 487def : IsZeroIdiomFunction<[ 488 // GPR Zero-idioms. 489 DepBreakingClass<[ XOR32rr ], ZeroIdiomPredicate>, 490 491 // SSE Zero-idioms. 492 DepBreakingClass<[ 493 // fp variants. 494 XORPSrr, XORPDrr, 495 496 // int variants. 497 PXORrr, 498 ], ZeroIdiomPredicate>, 499]>; 500 501} // SchedModel 502