1//===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes FMA (Fused Multiply-Add) instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// FMA3 - Intel 3 operand Fused Multiply-Add instructions 15//===----------------------------------------------------------------------===// 16 17// For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses 18// defined below, both the register and memory variants are commutable. 19// For the register form the commutable operands are 1, 2 and 3. 20// For the memory variant the folded operand must be in 3. Thus, 21// in that case, only the operands 1 and 2 can be swapped. 22// Commuting some of operands may require the opcode change. 23// FMA*213*: 24// operands 1 and 2 (memory & register forms): *213* --> *213*(no changes); 25// operands 1 and 3 (register forms only): *213* --> *231*; 26// operands 2 and 3 (register forms only): *213* --> *132*. 27// FMA*132*: 28// operands 1 and 2 (memory & register forms): *132* --> *231*; 29// operands 1 and 3 (register forms only): *132* --> *132*(no changes); 30// operands 2 and 3 (register forms only): *132* --> *213*. 31// FMA*231*: 32// operands 1 and 2 (memory & register forms): *231* --> *132*; 33// operands 1 and 3 (register forms only): *231* --> *213*; 34// operands 2 and 3 (register forms only): *231* --> *231*(no changes). 35 36multiclass fma3p_rm_213<bits<8> opc, string OpcodeStr, RegisterClass RC, 37 ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, 38 SDNode Op, X86FoldableSchedWrite sched> { 39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 40 (ins RC:$src1, RC:$src2, RC:$src3), 41 !strconcat(OpcodeStr, 42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>, 44 Sched<[sched]>; 45 46 let mayLoad = 1 in 47 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 48 (ins RC:$src1, RC:$src2, x86memop:$src3), 49 !strconcat(OpcodeStr, 50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, 52 (MemFrag addr:$src3))))]>, 53 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 54} 55 56multiclass fma3p_rm_231<bits<8> opc, string OpcodeStr, RegisterClass RC, 57 ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, 58 SDNode Op, X86FoldableSchedWrite sched> { 59 let hasSideEffects = 0 in 60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 61 (ins RC:$src1, RC:$src2, RC:$src3), 62 !strconcat(OpcodeStr, 63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 64 []>, Sched<[sched]>; 65 66 let mayLoad = 1 in 67 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 68 (ins RC:$src1, RC:$src2, x86memop:$src3), 69 !strconcat(OpcodeStr, 70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 71 [(set RC:$dst, (VT (Op RC:$src2, (MemFrag addr:$src3), 72 RC:$src1)))]>, 73 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 74} 75 76multiclass fma3p_rm_132<bits<8> opc, string OpcodeStr, RegisterClass RC, 77 ValueType VT, X86MemOperand x86memop, PatFrag MemFrag, 78 SDNode Op, X86FoldableSchedWrite sched> { 79 let hasSideEffects = 0 in 80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 81 (ins RC:$src1, RC:$src2, RC:$src3), 82 !strconcat(OpcodeStr, 83 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 84 []>, Sched<[sched]>; 85 86 // Pattern is 312 order so that the load is in a different place from the 87 // 213 and 231 patterns this helps tablegen's duplicate pattern detection. 88 let mayLoad = 1 in 89 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 90 (ins RC:$src1, RC:$src2, x86memop:$src3), 91 !strconcat(OpcodeStr, 92 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 93 [(set RC:$dst, (VT (Op (MemFrag addr:$src3), RC:$src1, 94 RC:$src2)))]>, 95 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 96} 97 98let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in 99multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 100 string OpcodeStr, string PackTy, string Suff, 101 PatFrag MemFrag128, PatFrag MemFrag256, 102 SDNode Op, ValueType OpTy128, ValueType OpTy256, 103 X86SchedWriteWidths sched> { 104 defm NAME#213#Suff : fma3p_rm_213<opc213, !strconcat(OpcodeStr, "213", PackTy), 105 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>; 106 defm NAME#231#Suff : fma3p_rm_231<opc231, !strconcat(OpcodeStr, "231", PackTy), 107 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>; 108 defm NAME#132#Suff : fma3p_rm_132<opc132, !strconcat(OpcodeStr, "132", PackTy), 109 VR128, OpTy128, f128mem, MemFrag128, Op, sched.XMM>; 110 111 defm NAME#213#Suff#Y : fma3p_rm_213<opc213, !strconcat(OpcodeStr, "213", PackTy), 112 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>, 113 VEX_L; 114 defm NAME#231#Suff#Y : fma3p_rm_231<opc231, !strconcat(OpcodeStr, "231", PackTy), 115 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>, 116 VEX_L; 117 defm NAME#132#Suff#Y : fma3p_rm_132<opc132, !strconcat(OpcodeStr, "132", PackTy), 118 VR256, OpTy256, f256mem, MemFrag256, Op, sched.YMM>, 119 VEX_L; 120} 121 122// Fused Multiply-Add 123let ExeDomain = SSEPackedSingle in { 124 defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", 125 loadv4f32, loadv8f32, X86Fmadd, v4f32, v8f32, 126 SchedWriteFMA>; 127 defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", 128 loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32, 129 SchedWriteFMA>; 130 defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", "PS", 131 loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32, 132 SchedWriteFMA>; 133 defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", "PS", 134 loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32, 135 SchedWriteFMA>; 136} 137 138let ExeDomain = SSEPackedDouble in { 139 defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", 140 loadv2f64, loadv4f64, X86Fmadd, v2f64, 141 v4f64, SchedWriteFMA>, VEX_W; 142 defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", 143 loadv2f64, loadv4f64, X86Fmsub, v2f64, 144 v4f64, SchedWriteFMA>, VEX_W; 145 defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", 146 loadv2f64, loadv4f64, X86Fmaddsub, 147 v2f64, v4f64, SchedWriteFMA>, VEX_W; 148 defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", 149 loadv2f64, loadv4f64, X86Fmsubadd, 150 v2f64, v4f64, SchedWriteFMA>, VEX_W; 151} 152 153// Fused Negative Multiply-Add 154let ExeDomain = SSEPackedSingle in { 155 defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", "PS", loadv4f32, 156 loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>; 157 defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", "PS", loadv4f32, 158 loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>; 159} 160let ExeDomain = SSEPackedDouble in { 161 defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64, 162 loadv4f64, X86Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W; 163 defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64, 164 loadv4f64, X86Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W; 165} 166 167// All source register operands of FMA opcodes defined in fma3s_rm multiclass 168// can be commuted. In many cases such commute transformation requres an opcode 169// adjustment, for example, commuting the operands 1 and 2 in FMA*132 form 170// would require an opcode change to FMA*231: 171// FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; 172// --> 173// FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2; 174// Please see more detailed comment at the very beginning of the section 175// defining FMA3 opcodes above. 176multiclass fma3s_rm_213<bits<8> opc, string OpcodeStr, 177 X86MemOperand x86memop, RegisterClass RC, 178 SDPatternOperator OpNode, 179 X86FoldableSchedWrite sched> { 180 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 181 (ins RC:$src1, RC:$src2, RC:$src3), 182 !strconcat(OpcodeStr, 183 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 184 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>, 185 Sched<[sched]>; 186 187 let mayLoad = 1 in 188 def m : FMA3S<opc, MRMSrcMem, (outs RC:$dst), 189 (ins RC:$src1, RC:$src2, x86memop:$src3), 190 !strconcat(OpcodeStr, 191 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 192 [(set RC:$dst, 193 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>, 194 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 195} 196 197multiclass fma3s_rm_231<bits<8> opc, string OpcodeStr, 198 X86MemOperand x86memop, RegisterClass RC, 199 SDPatternOperator OpNode, X86FoldableSchedWrite sched> { 200 let hasSideEffects = 0 in 201 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 202 (ins RC:$src1, RC:$src2, RC:$src3), 203 !strconcat(OpcodeStr, 204 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 205 []>, Sched<[sched]>; 206 207 let mayLoad = 1 in 208 def m : FMA3S<opc, MRMSrcMem, (outs RC:$dst), 209 (ins RC:$src1, RC:$src2, x86memop:$src3), 210 !strconcat(OpcodeStr, 211 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 212 [(set RC:$dst, 213 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>, 214 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 215} 216 217multiclass fma3s_rm_132<bits<8> opc, string OpcodeStr, 218 X86MemOperand x86memop, RegisterClass RC, 219 SDPatternOperator OpNode, X86FoldableSchedWrite sched> { 220 let hasSideEffects = 0 in 221 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst), 222 (ins RC:$src1, RC:$src2, RC:$src3), 223 !strconcat(OpcodeStr, 224 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 225 []>, Sched<[sched]>; 226 227 // Pattern is 312 order so that the load is in a different place from the 228 // 213 and 231 patterns this helps tablegen's duplicate pattern detection. 229 let mayLoad = 1 in 230 def m : FMA3S<opc, MRMSrcMem, (outs RC:$dst), 231 (ins RC:$src1, RC:$src2, x86memop:$src3), 232 !strconcat(OpcodeStr, 233 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 234 [(set RC:$dst, 235 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>, 236 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 237} 238 239let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1, 240 hasSideEffects = 0 in 241multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 242 string OpStr, string PackTy, string Suff, 243 SDNode OpNode, RegisterClass RC, 244 X86MemOperand x86memop, X86FoldableSchedWrite sched> { 245 defm NAME#213#Suff : fma3s_rm_213<opc213, !strconcat(OpStr, "213", PackTy), 246 x86memop, RC, OpNode, sched>; 247 defm NAME#231#Suff : fma3s_rm_231<opc231, !strconcat(OpStr, "231", PackTy), 248 x86memop, RC, OpNode, sched>; 249 defm NAME#132#Suff : fma3s_rm_132<opc132, !strconcat(OpStr, "132", PackTy), 250 x86memop, RC, OpNode, sched>; 251} 252 253// These FMA*_Int instructions are defined specially for being used when 254// the scalar FMA intrinsics are lowered to machine instructions, and in that 255// sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc. 256// instructions. 257// 258// All of the FMA*_Int opcodes are defined as commutable here. 259// Commuting the 2nd and 3rd source register operands of FMAs is quite trivial 260// and the corresponding optimizations have been developed. 261// Commuting the 1st operand of FMA*_Int requires some additional analysis, 262// the commute optimization is legal only if all users of FMA*_Int use only 263// the lowest element of the FMA*_Int instruction. Even though such analysis 264// may be not implemented yet we allow the routines doing the actual commute 265// transformation to decide if one or another instruction is commutable or not. 266let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in 267multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, 268 Operand memopr, RegisterClass RC, 269 X86FoldableSchedWrite sched> { 270 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst), 271 (ins RC:$src1, RC:$src2, RC:$src3), 272 !strconcat(OpcodeStr, 273 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 274 []>, Sched<[sched]>; 275 276 let mayLoad = 1 in 277 def m_Int : FMA3S_Int<opc, MRMSrcMem, (outs RC:$dst), 278 (ins RC:$src1, RC:$src2, memopr:$src3), 279 !strconcat(OpcodeStr, 280 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 281 []>, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 282} 283 284// The FMA 213 form is created for lowering of scalar FMA intrinscis 285// to machine instructions. 286// The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands 287// of FMA 213 form. 288// The FMA 231 form can be get only by commuting the 1st operand of 213 or 132 289// forms and is possible only after special analysis of all uses of the initial 290// instruction. Such analysis do not exist yet and thus introducing the 231 291// form of FMA*_Int instructions is done using an optimistic assumption that 292// such analysis will be implemented eventually. 293multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 294 string OpStr, string PackTy, string Suff, 295 RegisterClass RC, Operand memop, 296 X86FoldableSchedWrite sched> { 297 defm NAME#132#Suff : fma3s_rm_int<opc132, !strconcat(OpStr, "132", PackTy), 298 memop, RC, sched>; 299 defm NAME#213#Suff : fma3s_rm_int<opc213, !strconcat(OpStr, "213", PackTy), 300 memop, RC, sched>; 301 defm NAME#231#Suff : fma3s_rm_int<opc231, !strconcat(OpStr, "231", PackTy), 302 memop, RC, sched>; 303} 304 305multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231, 306 string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> { 307 let ExeDomain = SSEPackedSingle in 308 defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", OpNode, 309 FR32, f32mem, sched>, 310 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", "SS", 311 VR128, ssmem, sched>; 312 313 let ExeDomain = SSEPackedDouble in 314 defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "SD", OpNode, 315 FR64, f64mem, sched>, 316 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", "SD", 317 VR128, sdmem, sched>, VEX_W; 318} 319 320defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd, 321 SchedWriteFMA.Scl>, VEX_LIG; 322defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub, 323 SchedWriteFMA.Scl>, VEX_LIG; 324 325defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd, 326 SchedWriteFMA.Scl>, VEX_LIG; 327defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub, 328 SchedWriteFMA.Scl>, VEX_LIG; 329 330multiclass scalar_fma_patterns<SDNode Op, string Prefix, string Suffix, 331 SDNode Move, ValueType VT, ValueType EltVT, 332 RegisterClass RC, PatFrag mem_frag> { 333 let Predicates = [HasFMA, NoAVX512] in { 334 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector 335 (Op RC:$src2, 336 (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), 337 RC:$src3))))), 338 (!cast<Instruction>(Prefix#"213"#Suffix#"r_Int") 339 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 340 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; 341 342 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector 343 (Op RC:$src2, RC:$src3, 344 (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), 345 (!cast<Instruction>(Prefix#"231"#Suffix#"r_Int") 346 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 347 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; 348 349 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector 350 (Op RC:$src2, 351 (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), 352 (mem_frag addr:$src3)))))), 353 (!cast<Instruction>(Prefix#"213"#Suffix#"m_Int") 354 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 355 addr:$src3)>; 356 357 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector 358 (Op (EltVT (extractelt (VT VR128:$src1), (iPTR 0))), 359 (mem_frag addr:$src3), RC:$src2))))), 360 (!cast<Instruction>(Prefix#"132"#Suffix#"m_Int") 361 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 362 addr:$src3)>; 363 364 def : Pat<(VT (Move (VT VR128:$src1), (VT (scalar_to_vector 365 (Op RC:$src2, (mem_frag addr:$src3), 366 (EltVT (extractelt (VT VR128:$src1), (iPTR 0)))))))), 367 (!cast<Instruction>(Prefix#"231"#Suffix#"m_Int") 368 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 369 addr:$src3)>; 370 } 371} 372 373defm : scalar_fma_patterns<X86Fmadd, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 374defm : scalar_fma_patterns<X86Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 375defm : scalar_fma_patterns<X86Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 376defm : scalar_fma_patterns<X86Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>; 377 378defm : scalar_fma_patterns<X86Fmadd, "VFMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 379defm : scalar_fma_patterns<X86Fmsub, "VFMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 380defm : scalar_fma_patterns<X86Fnmadd, "VFNMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 381defm : scalar_fma_patterns<X86Fnmsub, "VFNMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>; 382 383//===----------------------------------------------------------------------===// 384// FMA4 - AMD 4 operand Fused Multiply-Add instructions 385//===----------------------------------------------------------------------===// 386 387multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC, 388 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, 389 PatFrag mem_frag, X86FoldableSchedWrite sched> { 390 let isCommutable = 1 in 391 def rr : FMA4S<opc, MRMSrcRegOp4, (outs RC:$dst), 392 (ins RC:$src1, RC:$src2, RC:$src3), 393 !strconcat(OpcodeStr, 394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 395 [(set RC:$dst, 396 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, 397 Sched<[sched]>; 398 def rm : FMA4S<opc, MRMSrcMemOp4, (outs RC:$dst), 399 (ins RC:$src1, RC:$src2, x86memop:$src3), 400 !strconcat(OpcodeStr, 401 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 402 [(set RC:$dst, (OpNode RC:$src1, RC:$src2, 403 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, 404 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 405 def mr : FMA4S<opc, MRMSrcMem, (outs RC:$dst), 406 (ins RC:$src1, x86memop:$src2, RC:$src3), 407 !strconcat(OpcodeStr, 408 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 409 [(set RC:$dst, 410 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG, 411 Sched<[sched.Folded, sched.ReadAfterFold, 412 // x86memop:$src2 413 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 414 ReadDefault, 415 // RC:$src3 416 sched.ReadAfterFold]>; 417// For disassembler 418let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 419 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst), 420 (ins RC:$src1, RC:$src2, RC:$src3), 421 !strconcat(OpcodeStr, 422 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 423 VEX_LIG, FoldGenData<NAME#rr>, Sched<[sched]>; 424} 425 426multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop, 427 ValueType VT, X86FoldableSchedWrite sched> { 428let isCodeGenOnly = 1, hasSideEffects = 0 in { 429 def rr_Int : FMA4S_Int<opc, MRMSrcRegOp4, (outs VR128:$dst), 430 (ins VR128:$src1, VR128:$src2, VR128:$src3), 431 !strconcat(OpcodeStr, 432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 433 []>, VEX_W, VEX_LIG, Sched<[sched]>; 434 let mayLoad = 1 in 435 def rm_Int : FMA4S_Int<opc, MRMSrcMemOp4, (outs VR128:$dst), 436 (ins VR128:$src1, VR128:$src2, memop:$src3), 437 !strconcat(OpcodeStr, 438 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 439 []>, VEX_W, VEX_LIG, 440 Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; 441 let mayLoad = 1 in 442 def mr_Int : FMA4S_Int<opc, MRMSrcMem, (outs VR128:$dst), 443 (ins VR128:$src1, memop:$src2, VR128:$src3), 444 !strconcat(OpcodeStr, 445 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 446 []>, 447 VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold, 448 // memop:$src2 449 ReadDefault, ReadDefault, ReadDefault, 450 ReadDefault, ReadDefault, 451 // VR128::$src3 452 sched.ReadAfterFold]>; 453 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst), 454 (ins VR128:$src1, VR128:$src2, VR128:$src3), 455 !strconcat(OpcodeStr, 456 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 457 []>, VEX_LIG, FoldGenData<NAME#rr_Int>, Sched<[sched]>; 458} // isCodeGenOnly = 1 459} 460 461multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode, 462 ValueType OpVT128, ValueType OpVT256, 463 PatFrag ld_frag128, PatFrag ld_frag256, 464 X86SchedWriteWidths sched> { 465 let isCommutable = 1 in 466 def rr : FMA4<opc, MRMSrcRegOp4, (outs VR128:$dst), 467 (ins VR128:$src1, VR128:$src2, VR128:$src3), 468 !strconcat(OpcodeStr, 469 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 470 [(set VR128:$dst, 471 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>, 472 VEX_W, Sched<[sched.XMM]>; 473 def rm : FMA4<opc, MRMSrcMemOp4, (outs VR128:$dst), 474 (ins VR128:$src1, VR128:$src2, f128mem:$src3), 475 !strconcat(OpcodeStr, 476 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 477 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2, 478 (ld_frag128 addr:$src3)))]>, VEX_W, 479 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold, sched.XMM.ReadAfterFold]>; 480 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 481 (ins VR128:$src1, f128mem:$src2, VR128:$src3), 482 !strconcat(OpcodeStr, 483 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 484 [(set VR128:$dst, 485 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>, 486 Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold, 487 // f128mem:$src2 488 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 489 ReadDefault, 490 // VR128::$src3 491 sched.XMM.ReadAfterFold]>; 492 let isCommutable = 1 in 493 def Yrr : FMA4<opc, MRMSrcRegOp4, (outs VR256:$dst), 494 (ins VR256:$src1, VR256:$src2, VR256:$src3), 495 !strconcat(OpcodeStr, 496 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 497 [(set VR256:$dst, 498 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>, 499 VEX_W, VEX_L, Sched<[sched.YMM]>; 500 def Yrm : FMA4<opc, MRMSrcMemOp4, (outs VR256:$dst), 501 (ins VR256:$src1, VR256:$src2, f256mem:$src3), 502 !strconcat(OpcodeStr, 503 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 504 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2, 505 (ld_frag256 addr:$src3)))]>, VEX_W, VEX_L, 506 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold, sched.YMM.ReadAfterFold]>; 507 def Ymr : FMA4<opc, MRMSrcMem, (outs VR256:$dst), 508 (ins VR256:$src1, f256mem:$src2, VR256:$src3), 509 !strconcat(OpcodeStr, 510 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 511 [(set VR256:$dst, (OpNode VR256:$src1, 512 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L, 513 Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold, 514 // f256mem:$src2 515 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 516 ReadDefault, 517 // VR256::$src3 518 sched.YMM.ReadAfterFold]>; 519// For disassembler 520let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 521 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 522 (ins VR128:$src1, VR128:$src2, VR128:$src3), 523 !strconcat(OpcodeStr, 524 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 525 Sched<[sched.XMM]>, FoldGenData<NAME#rr>; 526 def Yrr_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst), 527 (ins VR256:$src1, VR256:$src2, VR256:$src3), 528 !strconcat(OpcodeStr, 529 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 530 VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>; 531} // isCodeGenOnly = 1 532} 533 534let ExeDomain = SSEPackedSingle in { 535 // Scalar Instructions 536 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32, 537 SchedWriteFMA.Scl>, 538 fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, 539 SchedWriteFMA.Scl>; 540 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32, 541 SchedWriteFMA.Scl>, 542 fma4s_int<0x6E, "vfmsubss", ssmem, v4f32, 543 SchedWriteFMA.Scl>; 544 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 545 X86Fnmadd, loadf32, SchedWriteFMA.Scl>, 546 fma4s_int<0x7A, "vfnmaddss", ssmem, v4f32, 547 SchedWriteFMA.Scl>; 548 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, 549 X86Fnmsub, loadf32, SchedWriteFMA.Scl>, 550 fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, 551 SchedWriteFMA.Scl>; 552 // Packed Instructions 553 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, 554 loadv4f32, loadv8f32, SchedWriteFMA>; 555 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, 556 loadv4f32, loadv8f32, SchedWriteFMA>; 557 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, 558 loadv4f32, loadv8f32, SchedWriteFMA>; 559 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, 560 loadv4f32, loadv8f32, SchedWriteFMA>; 561 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, 562 loadv4f32, loadv8f32, SchedWriteFMA>; 563 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, 564 loadv4f32, loadv8f32, SchedWriteFMA>; 565} 566 567let ExeDomain = SSEPackedDouble in { 568 // Scalar Instructions 569 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64, 570 SchedWriteFMA.Scl>, 571 fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, 572 SchedWriteFMA.Scl>; 573 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64, 574 SchedWriteFMA.Scl>, 575 fma4s_int<0x6F, "vfmsubsd", sdmem, v2f64, 576 SchedWriteFMA.Scl>; 577 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, 578 X86Fnmadd, loadf64, SchedWriteFMA.Scl>, 579 fma4s_int<0x7B, "vfnmaddsd", sdmem, v2f64, 580 SchedWriteFMA.Scl>; 581 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, 582 X86Fnmsub, loadf64, SchedWriteFMA.Scl>, 583 fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, 584 SchedWriteFMA.Scl>; 585 // Packed Instructions 586 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, 587 loadv2f64, loadv4f64, SchedWriteFMA>; 588 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, 589 loadv2f64, loadv4f64, SchedWriteFMA>; 590 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, 591 loadv2f64, loadv4f64, SchedWriteFMA>; 592 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, 593 loadv2f64, loadv4f64, SchedWriteFMA>; 594 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, 595 loadv2f64, loadv4f64, SchedWriteFMA>; 596 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, 597 loadv2f64, loadv4f64, SchedWriteFMA>; 598} 599 600multiclass scalar_fma4_patterns<SDNode Op, string Name, 601 ValueType VT, ValueType EltVT, 602 RegisterClass RC, PatFrag mem_frag> { 603 let Predicates = [HasFMA4] in { 604 def : Pat<(VT (X86vzmovl (VT (scalar_to_vector 605 (Op RC:$src1, RC:$src2, RC:$src3))))), 606 (!cast<Instruction>(Name#"rr_Int") 607 (VT (COPY_TO_REGCLASS RC:$src1, VR128)), 608 (VT (COPY_TO_REGCLASS RC:$src2, VR128)), 609 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; 610 611 def : Pat<(VT (X86vzmovl (VT (scalar_to_vector 612 (Op RC:$src1, RC:$src2, 613 (mem_frag addr:$src3)))))), 614 (!cast<Instruction>(Name#"rm_Int") 615 (VT (COPY_TO_REGCLASS RC:$src1, VR128)), 616 (VT (COPY_TO_REGCLASS RC:$src2, VR128)), addr:$src3)>; 617 618 def : Pat<(VT (X86vzmovl (VT (scalar_to_vector 619 (Op RC:$src1, (mem_frag addr:$src2), 620 RC:$src3))))), 621 (!cast<Instruction>(Name#"mr_Int") 622 (VT (COPY_TO_REGCLASS RC:$src1, VR128)), addr:$src2, 623 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>; 624 } 625} 626 627defm : scalar_fma4_patterns<X86Fmadd, "VFMADDSS4", v4f32, f32, FR32, loadf32>; 628defm : scalar_fma4_patterns<X86Fmsub, "VFMSUBSS4", v4f32, f32, FR32, loadf32>; 629defm : scalar_fma4_patterns<X86Fnmadd, "VFNMADDSS4", v4f32, f32, FR32, loadf32>; 630defm : scalar_fma4_patterns<X86Fnmsub, "VFNMSUBSS4", v4f32, f32, FR32, loadf32>; 631 632defm : scalar_fma4_patterns<X86Fmadd, "VFMADDSD4", v2f64, f64, FR64, loadf64>; 633defm : scalar_fma4_patterns<X86Fmsub, "VFMSUBSD4", v2f64, f64, FR64, loadf64>; 634defm : scalar_fma4_patterns<X86Fnmadd, "VFNMADDSD4", v2f64, f64, FR64, loadf64>; 635defm : scalar_fma4_patterns<X86Fnmsub, "VFNMSUBSD4", v2f64, f64, FR64, loadf64>; 636