1//==- X86InstrAsmAlias.td - Assembler Instruction Aliases --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the assembler mnemonic/instruction aliases in the X86 10// architecture. 11// 12//===----------------------------------------------------------------------===// 13 14// Reversed version with ".s" suffix for GAS compatibility. 15def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 16 (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 17def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 18 (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 19def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 20 (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 21def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 22 (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 23def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 24 (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 25def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 26 (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 27def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 28 (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 29def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 30 (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 31 32// MONITORX/MWAITX Instructions Alias 33def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 34 Requires<[ Not64BitMode ]>; 35def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 36 Requires<[ In64BitMode ]>; 37 38// MONITORX/MWAITX Instructions Alias 39def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>, 40 Requires<[ Not64BitMode ]>; 41def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>, 42 Requires<[ In64BitMode ]>; 43 44// CLZERO Instruction Alias 45def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>; 46def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>; 47 48// INVLPGB Instruction Alias 49def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>; 50def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>; 51 52// CMPCCXADD Instructions Alias 53multiclass CMPCCXADD_Aliases<string Cond, int CC> { 54 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 55 (CMPCCXADDmr32 GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>; 56 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 57 (CMPCCXADDmr64 GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>; 58 59 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 60 (CMPCCXADDmr32_EVEX GR32:$dst, i32mem:$dstsrc2, GR32:$src3, CC), 0>; 61 def : InstAlias<"cmp"#Cond#"xadd"#"\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", 62 (CMPCCXADDmr64_EVEX GR64:$dst, i64mem:$dstsrc2, GR64:$src3, CC), 0>; 63} 64 65//===----------------------------------------------------------------------===// 66// Assembler Mnemonic Aliases 67//===----------------------------------------------------------------------===// 68 69defm : CMPCCXADD_Aliases<"o" , 0>; 70defm : CMPCCXADD_Aliases<"no", 1>; 71defm : CMPCCXADD_Aliases<"b" , 2>; 72defm : CMPCCXADD_Aliases<"ae", 3>; 73defm : CMPCCXADD_Aliases<"nb", 3>; 74defm : CMPCCXADD_Aliases<"e" , 4>; 75defm : CMPCCXADD_Aliases<"z" , 4>; 76defm : CMPCCXADD_Aliases<"ne", 5>; 77defm : CMPCCXADD_Aliases<"nz", 5>; 78defm : CMPCCXADD_Aliases<"be", 6>; 79defm : CMPCCXADD_Aliases<"nbe", 7>; 80defm : CMPCCXADD_Aliases<"a", 7>; 81defm : CMPCCXADD_Aliases<"s" , 8>; 82defm : CMPCCXADD_Aliases<"ns", 9>; 83defm : CMPCCXADD_Aliases<"p" , 10>; 84defm : CMPCCXADD_Aliases<"np", 11>; 85defm : CMPCCXADD_Aliases<"l" , 12>; 86defm : CMPCCXADD_Aliases<"ge", 13>; 87defm : CMPCCXADD_Aliases<"nl", 13>; 88defm : CMPCCXADD_Aliases<"le", 14>; 89defm : CMPCCXADD_Aliases<"g", 15>; 90defm : CMPCCXADD_Aliases<"nle",15>; 91 92 93def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 94def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 95def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 96 97def : MnemonicAlias<"cbw", "cbtw", "att">; 98def : MnemonicAlias<"cwde", "cwtl", "att">; 99def : MnemonicAlias<"cwd", "cwtd", "att">; 100def : MnemonicAlias<"cdq", "cltd", "att">; 101def : MnemonicAlias<"cdqe", "cltq", "att">; 102def : MnemonicAlias<"cqo", "cqto", "att">; 103 104// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 105def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 106def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 107 108def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 109def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 110 111def : MnemonicAlias<"loopz", "loope">; 112def : MnemonicAlias<"loopnz", "loopne">; 113 114def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 115def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 116def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 117def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 118def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 119def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 120def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 121def : MnemonicAlias<"popfd", "popfl", "att">; 122def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In32BitMode]>; 123def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In64BitMode]>; 124 125// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 126// all modes. However: "push (addr)" and "push $42" should default to 127// pushl/pushq depending on the current mode. Similar for "pop %bx" 128def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 129def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 130def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 131def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 132def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 133def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 134def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 135def : MnemonicAlias<"pushfd", "pushfl", "att">; 136def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In32BitMode]>; 137def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In64BitMode]>; 138 139def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 140def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 141def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 142def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 143def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 144def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 145 146def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 147def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 148def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 149def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 150 151def : MnemonicAlias<"repe", "rep">; 152def : MnemonicAlias<"repz", "rep">; 153def : MnemonicAlias<"repnz", "repne">; 154 155def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 156def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 157def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 158 159// Apply 'ret' behavior to 'retn' 160def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 161def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 162def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 163def : MnemonicAlias<"retn", "ret", "intel">; 164 165def : MnemonicAlias<"sal", "shl", "intel">; 166def : MnemonicAlias<"salb", "shlb", "att">; 167def : MnemonicAlias<"salw", "shlw", "att">; 168def : MnemonicAlias<"sall", "shll", "att">; 169def : MnemonicAlias<"salq", "shlq", "att">; 170 171def : MnemonicAlias<"smovb", "movsb", "att">; 172def : MnemonicAlias<"smovw", "movsw", "att">; 173def : MnemonicAlias<"smovl", "movsl", "att">; 174def : MnemonicAlias<"smovq", "movsq", "att">; 175 176def : MnemonicAlias<"ud2a", "ud2", "att">; 177def : MnemonicAlias<"ud2bw", "ud1w", "att">; 178def : MnemonicAlias<"ud2bl", "ud1l", "att">; 179def : MnemonicAlias<"ud2bq", "ud1q", "att">; 180def : MnemonicAlias<"verrw", "verr", "att">; 181 182// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 183def : MnemonicAlias<"acquire", "xacquire", "intel">; 184def : MnemonicAlias<"release", "xrelease", "intel">; 185 186// System instruction aliases. 187def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 188def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 189def : MnemonicAlias<"sysret", "sysretl", "att">; 190def : MnemonicAlias<"sysexit", "sysexitl", "att">; 191 192def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 193def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 194def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 195def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 196def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 197def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 198def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 199def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 200def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 201def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 202def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 203def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 204def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 205def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 206def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 207def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 208def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 209def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 210def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 211def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 212 213 214// Floating point stack aliases. 215def : MnemonicAlias<"fcmovz", "fcmove", "att">; 216def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 217def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 218def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 219def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 220def : MnemonicAlias<"fcomip", "fcompi">; 221def : MnemonicAlias<"fildq", "fildll", "att">; 222def : MnemonicAlias<"fistpq", "fistpll", "att">; 223def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 224def : MnemonicAlias<"fldcww", "fldcw", "att">; 225def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 226def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 227def : MnemonicAlias<"fucomip", "fucompi">; 228def : MnemonicAlias<"fwait", "wait">; 229 230def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 231def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 232def : MnemonicAlias<"xsaveq", "xsave64", "att">; 233def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 234def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 235def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 236def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 237def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 238 239class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 240 string VariantName> 241 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 242 !strconcat(Prefix, NewCond, Suffix), VariantName>; 243 244/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 245/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 246/// example "setz" -> "sete". 247multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 248 string V = ""> { 249 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 250 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 251 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 252 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 253 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 254 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 255 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 256 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 257 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 258 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 259 260 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 261 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 262 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 263 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 264} 265 266// Aliases for set<CC> 267defm : IntegerCondCodeMnemonicAlias<"set", "">; 268// Aliases for j<CC> 269defm : IntegerCondCodeMnemonicAlias<"j", "">; 270// Aliases for cmov<CC>{w,l,q} 271defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 272defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 273defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 274// No size suffix for intel-style asm. 275defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 276 277//===----------------------------------------------------------------------===// 278// Assembler Instruction Aliases 279//===----------------------------------------------------------------------===// 280 281// aad/aam default to base 10 if no operand is specified. 282def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 283def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 284 285// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 286// Likewise for btc/btr/bts. 287def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 288 (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 289def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 290 (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 291def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 292 (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 293def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 294 (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 295 296// clr aliases. 297def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 298def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 299def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 300def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 301 302// lods aliases. Accept the destination being omitted because it's implicit 303// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 304// in the destination. 305def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 306def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 307def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 308def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 309def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 310def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 311def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 312def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 313def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 314def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 315def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 316def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 317 318 319// stos aliases. Accept the source being omitted because it's implicit in 320// the mnemonic, or the mnemonic suffix being omitted because it's implicit 321// in the source. 322def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 323def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 324def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 325def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 326def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 327def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 328def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 329def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 330def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 331def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 332def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 333def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 334 335 336// scas aliases. Accept the destination being omitted because it's implicit 337// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 338// in the destination. 339def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 340def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 341def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 342def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 343def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 344def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 345def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 346def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 347def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 348def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 349def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 350def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 351 352// cmps aliases. Mnemonic suffix being omitted because it's implicit 353// in the destination. 354def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 355def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 356def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 357def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 358 359// movs aliases. Mnemonic suffix being omitted because it's implicit 360// in the destination. 361def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 362def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 363def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 364def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 365 366// div and idiv aliases for explicit A register. 367def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 368def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 369def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 370def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 371def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 372def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 373def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 374def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 375def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 376def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 377def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 378def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 379def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 380def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 381def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 382def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 383 384 385 386// Various unary fpstack operations default to operating on ST1. 387// For example, "fxch" -> "fxch %st(1)" 388def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 389def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 390def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 391def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 392def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 393def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 394def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 395def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 396def : InstAlias<"fxch", (XCH_F ST1), 0>; 397def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 398def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 399def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 400def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 401def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 402def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 403def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 404def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 405 406// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 407// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 408// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 409// gas. 410multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 411 def : InstAlias<!strconcat(Mnemonic, "\t$op"), 412 (Inst RSTi:$op), EmitAlias>; 413 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), 414 (Inst ST0), EmitAlias>; 415} 416 417defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>; 418defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 419defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>; 420defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>; 421defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>; 422defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>; 423defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>; 424defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>; 425defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>; 426defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>; 427defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>; 428defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>; 429defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 430defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 431defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>; 432defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>; 433 434 435// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they 436// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 437// solely because gas supports it. 438def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>; 439def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>; 440def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>; 441def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>; 442def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>; 443def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>; 444 445def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 446 447// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 448// this is compatible with what GAS does. 449def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 450def : InstAlias<"ljmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 451def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 452def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 453def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 454def : InstAlias<"ljmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 455def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 456def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 457 458def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 459def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 460def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 461 462 463// "imul <imm>, B" is an alias for "imul <imm>, B, B". 464def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 465def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 466def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 467def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 468def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 469def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 470 471// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 472// in the destination. 473def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 474def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 475def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 476 477// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 478// in the source. 479def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 480def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 481def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 482 483// inb %dx -> inb %al, %dx 484def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 485def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 486def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 487def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 488def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 489def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 490 491 492// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 493def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 494def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 495def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 496def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 497def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 498def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 499def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 500def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 501 502// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 503def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 504 505// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 506// which supports this due to an old AMD documentation bug when 64-bit mode was 507// created. 508def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 509 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 510def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 511 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 512 513// movsx aliases 514def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 515def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 516def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 517def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 518def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 519def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 520def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 521 522// movzx aliases 523def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 524def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 525def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 526def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 527def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 528def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 529// Note: No GR32->GR64 movzx form. 530 531// outb %dx -> outb %al, %dx 532def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 533def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 534def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 535def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 536def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 537def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 538 539// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 540// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 541// errors, since its encoding is the most compact. 542def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 543 544// shld/shrd op,op -> shld op, op, CL 545def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 546def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 547def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 548def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 549def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 550def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 551 552def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 553def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 554def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 555def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 556def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 557def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 558 559// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 560def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 561 (TEST8mr i8mem :$mem, GR8 :$val), 0>; 562def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 563 (TEST16mr i16mem:$mem, GR16:$val), 0>; 564def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 565 (TEST32mr i32mem:$mem, GR32:$val), 0>; 566def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 567 (TEST64mr i64mem:$mem, GR64:$val), 0>; 568 569// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 570def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 571 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 572def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 573 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 574def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 575 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 576def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 577 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 578 579// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 580def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 581def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 582def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 583 584// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 585// would get by default because it's defined as NOP. But xchg %eax, %eax implies 586// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 587def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 588 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 589 590// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 591// we emit an unneeded REX.w prefix. 592def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 593 594// These aliases exist to get the parser to prioritize matching 8-bit 595// immediate encodings over matching the implicit ax/eax/rax encodings. By 596// explicitly mentioning the A register here, these entries will be ordered 597// first due to the more explicit immediate type. 598def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 599def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 600def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 601def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 602def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 603def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 604def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 605def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 606 607def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 608def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 609def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 610def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 611def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 612def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 613def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 614def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 615 616def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 617def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 618def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 619def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 620def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 621def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 622def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 623def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 624 625// MMX instr alia 626def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", 627 (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>; 628 629// CMOV SETCC Aliases 630multiclass CMOV_SETCC_Aliases<string Cond, int CC> { 631 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 632 (CMOV16rr GR16:$dst, GR16:$src, CC), 0>; 633 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", 634 (CMOV16rm GR16:$dst, i16mem:$src, CC), 0>; 635 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 636 (CMOV32rr GR32:$dst, GR32:$src, CC), 0>; 637 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}", 638 (CMOV32rm GR32:$dst, i32mem:$src, CC), 0>; 639 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 640 (CMOV64rr GR64:$dst, GR64:$src, CC), 0>; 641 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}", 642 (CMOV64rm GR64:$dst, i64mem:$src, CC), 0>; 643 644 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>; 645 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>; 646} 647 648defm : CMOV_SETCC_Aliases<"o" , 0>; 649defm : CMOV_SETCC_Aliases<"no", 1>; 650defm : CMOV_SETCC_Aliases<"b" , 2>; 651defm : CMOV_SETCC_Aliases<"ae", 3>; 652defm : CMOV_SETCC_Aliases<"e" , 4>; 653defm : CMOV_SETCC_Aliases<"ne", 5>; 654defm : CMOV_SETCC_Aliases<"be", 6>; 655defm : CMOV_SETCC_Aliases<"a" , 7>; 656defm : CMOV_SETCC_Aliases<"s" , 8>; 657defm : CMOV_SETCC_Aliases<"ns", 9>; 658defm : CMOV_SETCC_Aliases<"p" , 10>; 659defm : CMOV_SETCC_Aliases<"np", 11>; 660defm : CMOV_SETCC_Aliases<"l" , 12>; 661defm : CMOV_SETCC_Aliases<"ge", 13>; 662defm : CMOV_SETCC_Aliases<"le", 14>; 663defm : CMOV_SETCC_Aliases<"g" , 15>; 664 665// Condition dump instructions Alias 666def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>; 667def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>; 668def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>; 669def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>; 670def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>; 671def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>; 672def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>; 673def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>; 674def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>; 675def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>; 676def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>; 677def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>; 678def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>; 679def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>; 680def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>; 681def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>; 682 683// SVM instructions Alias 684def : InstAlias<"skinit\t{%eax|eax}", (SKINIT), 0>; 685def : InstAlias<"vmrun\t{%eax|eax}", (VMRUN32), 0>, Requires<[Not64BitMode]>; 686def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>; 687def : InstAlias<"vmload\t{%eax|eax}", (VMLOAD32), 0>, Requires<[Not64BitMode]>; 688def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>; 689def : InstAlias<"vmsave\t{%eax|eax}", (VMSAVE32), 0>, Requires<[Not64BitMode]>; 690def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>; 691def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>; 692def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>; 693 694// Aliases with explicit %xmm0 695def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", 696 (SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>; 697def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", 698 (SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>; 699 700def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}", 701 (SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>; 702