1 //===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines a pass that fixes zero-extension of setcc patterns. 10 // X86 setcc instructions are modeled to have no input arguments, and a single 11 // GR8 output argument. This is consistent with other similar instructions 12 // (e.g. movb), but means it is impossible to directly generate a setcc into 13 // the lower GR8 of a specified GR32. 14 // This means that ISel must select (zext (setcc)) into something like 15 // seta %al; movzbl %al, %eax. 16 // Unfortunately, this can cause a stall due to the partial register write 17 // performed by the setcc. Instead, we can use: 18 // xor %eax, %eax; seta %al 19 // This both avoids the stall, and encodes shorter. 20 //===----------------------------------------------------------------------===// 21 22 #include "X86.h" 23 #include "X86InstrInfo.h" 24 #include "X86Subtarget.h" 25 #include "llvm/ADT/Statistic.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "x86-fixup-setcc" 33 34 STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted"); 35 36 namespace { 37 class X86FixupSetCCPass : public MachineFunctionPass { 38 public: 39 X86FixupSetCCPass() : MachineFunctionPass(ID) {} 40 41 StringRef getPassName() const override { return "X86 Fixup SetCC"; } 42 43 bool runOnMachineFunction(MachineFunction &MF) override; 44 45 private: 46 MachineRegisterInfo *MRI = nullptr; 47 const X86InstrInfo *TII = nullptr; 48 49 enum { SearchBound = 16 }; 50 51 static char ID; 52 }; 53 54 char X86FixupSetCCPass::ID = 0; 55 } 56 57 FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); } 58 59 bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { 60 bool Changed = false; 61 MRI = &MF.getRegInfo(); 62 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); 63 64 SmallVector<MachineInstr*, 4> ToErase; 65 66 for (auto &MBB : MF) { 67 MachineInstr *FlagsDefMI = nullptr; 68 for (auto &MI : MBB) { 69 // Remember the most recent preceding eflags defining instruction. 70 if (MI.definesRegister(X86::EFLAGS)) 71 FlagsDefMI = &MI; 72 73 // Find a setcc that is used by a zext. 74 // This doesn't have to be the only use, the transformation is safe 75 // regardless. 76 if (MI.getOpcode() != X86::SETCCr) 77 continue; 78 79 MachineInstr *ZExt = nullptr; 80 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg())) 81 if (Use.getOpcode() == X86::MOVZX32rr8) 82 ZExt = &Use; 83 84 if (!ZExt) 85 continue; 86 87 if (!FlagsDefMI) 88 continue; 89 90 // We'd like to put something that clobbers eflags directly before 91 // FlagsDefMI. This can't hurt anything after FlagsDefMI, because 92 // it, itself, by definition, clobbers eflags. But it may happen that 93 // FlagsDefMI also *uses* eflags, in which case the transformation is 94 // invalid. 95 if (FlagsDefMI->readsRegister(X86::EFLAGS)) 96 continue; 97 98 ++NumSubstZexts; 99 Changed = true; 100 101 // On 32-bit, we need to be careful to force an ABCD register. 102 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() 103 ? &X86::GR32RegClass 104 : &X86::GR32_ABCDRegClass; 105 Register ZeroReg = MRI->createVirtualRegister(RC); 106 Register InsertReg = MRI->createVirtualRegister(RC); 107 108 // Initialize a register with 0. This must go before the eflags def 109 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0), 110 ZeroReg); 111 112 // X86 setcc only takes an output GR8, so fake a GR32 input by inserting 113 // the setcc result into the low byte of the zeroed register. 114 BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(), 115 TII->get(X86::INSERT_SUBREG), InsertReg) 116 .addReg(ZeroReg) 117 .addReg(MI.getOperand(0).getReg()) 118 .addImm(X86::sub_8bit); 119 MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg); 120 ToErase.push_back(ZExt); 121 } 122 } 123 124 for (auto &I : ToErase) 125 I->eraseFromParent(); 126 127 return Changed; 128 } 129