1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SparcFixupKinds.h" 10 #include "MCTargetDesc/SparcMCTargetDesc.h" 11 #include "llvm/ADT/StringSwitch.h" 12 #include "llvm/MC/MCAsmBackend.h" 13 #include "llvm/MC/MCELFObjectWriter.h" 14 #include "llvm/MC/MCExpr.h" 15 #include "llvm/MC/MCFixupKindInfo.h" 16 #include "llvm/MC/MCObjectWriter.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/MC/MCValue.h" 19 #include "llvm/MC/TargetRegistry.h" 20 #include "llvm/Support/EndianStream.h" 21 22 using namespace llvm; 23 24 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 25 switch (Kind) { 26 default: 27 llvm_unreachable("Unknown fixup kind!"); 28 case FK_Data_1: 29 case FK_Data_2: 30 case FK_Data_4: 31 case FK_Data_8: 32 return Value; 33 34 case Sparc::fixup_sparc_wplt30: 35 case Sparc::fixup_sparc_call30: 36 return (Value >> 2) & 0x3fffffff; 37 38 case Sparc::fixup_sparc_br22: 39 return (Value >> 2) & 0x3fffff; 40 41 case Sparc::fixup_sparc_br19: 42 return (Value >> 2) & 0x7ffff; 43 44 case Sparc::fixup_sparc_br16_2: 45 return (Value >> 2) & 0xc000; 46 47 case Sparc::fixup_sparc_br16_14: 48 return (Value >> 2) & 0x3fff; 49 50 case Sparc::fixup_sparc_pc22: 51 case Sparc::fixup_sparc_got22: 52 case Sparc::fixup_sparc_tls_gd_hi22: 53 case Sparc::fixup_sparc_tls_ldm_hi22: 54 case Sparc::fixup_sparc_tls_ie_hi22: 55 case Sparc::fixup_sparc_hi22: 56 case Sparc::fixup_sparc_lm: 57 return (Value >> 10) & 0x3fffff; 58 59 case Sparc::fixup_sparc_got13: 60 case Sparc::fixup_sparc_13: 61 return Value & 0x1fff; 62 63 case Sparc::fixup_sparc_pc10: 64 case Sparc::fixup_sparc_got10: 65 case Sparc::fixup_sparc_tls_gd_lo10: 66 case Sparc::fixup_sparc_tls_ldm_lo10: 67 case Sparc::fixup_sparc_tls_ie_lo10: 68 case Sparc::fixup_sparc_lo10: 69 return Value & 0x3ff; 70 71 case Sparc::fixup_sparc_h44: 72 return (Value >> 22) & 0x3fffff; 73 74 case Sparc::fixup_sparc_m44: 75 return (Value >> 12) & 0x3ff; 76 77 case Sparc::fixup_sparc_l44: 78 return Value & 0xfff; 79 80 case Sparc::fixup_sparc_hh: 81 return (Value >> 42) & 0x3fffff; 82 83 case Sparc::fixup_sparc_hm: 84 return (Value >> 32) & 0x3ff; 85 86 case Sparc::fixup_sparc_tls_ldo_hix22: 87 case Sparc::fixup_sparc_tls_le_hix22: 88 case Sparc::fixup_sparc_tls_ldo_lox10: 89 case Sparc::fixup_sparc_tls_le_lox10: 90 assert(Value == 0 && "Sparc TLS relocs expect zero Value"); 91 return 0; 92 93 case Sparc::fixup_sparc_tls_gd_add: 94 case Sparc::fixup_sparc_tls_gd_call: 95 case Sparc::fixup_sparc_tls_ldm_add: 96 case Sparc::fixup_sparc_tls_ldm_call: 97 case Sparc::fixup_sparc_tls_ldo_add: 98 case Sparc::fixup_sparc_tls_ie_ld: 99 case Sparc::fixup_sparc_tls_ie_ldx: 100 case Sparc::fixup_sparc_tls_ie_add: 101 return 0; 102 } 103 } 104 105 /// getFixupKindNumBytes - The number of bytes the fixup may change. 106 static unsigned getFixupKindNumBytes(unsigned Kind) { 107 switch (Kind) { 108 default: 109 return 4; 110 case FK_Data_1: 111 return 1; 112 case FK_Data_2: 113 return 2; 114 case FK_Data_8: 115 return 8; 116 } 117 } 118 119 namespace { 120 class SparcAsmBackend : public MCAsmBackend { 121 protected: 122 const Target &TheTarget; 123 bool Is64Bit; 124 125 public: 126 SparcAsmBackend(const Target &T) 127 : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little 128 : support::big), 129 TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} 130 131 unsigned getNumFixupKinds() const override { 132 return Sparc::NumTargetFixupKinds; 133 } 134 135 Optional<MCFixupKind> getFixupKind(StringRef Name) const override { 136 unsigned Type; 137 Type = llvm::StringSwitch<unsigned>(Name) 138 #define ELF_RELOC(X, Y) .Case(#X, Y) 139 #include "llvm/BinaryFormat/ELFRelocs/Sparc.def" 140 #undef ELF_RELOC 141 .Case("BFD_RELOC_NONE", ELF::R_SPARC_NONE) 142 .Case("BFD_RELOC_8", ELF::R_SPARC_8) 143 .Case("BFD_RELOC_16", ELF::R_SPARC_16) 144 .Case("BFD_RELOC_32", ELF::R_SPARC_32) 145 .Case("BFD_RELOC_64", ELF::R_SPARC_64) 146 .Default(-1u); 147 if (Type == -1u) 148 return None; 149 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); 150 } 151 152 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 153 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { 154 // name offset bits flags 155 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 156 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 157 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 158 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel }, 159 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel }, 160 { "fixup_sparc_13", 19, 13, 0 }, 161 { "fixup_sparc_hi22", 10, 22, 0 }, 162 { "fixup_sparc_lo10", 22, 10, 0 }, 163 { "fixup_sparc_h44", 10, 22, 0 }, 164 { "fixup_sparc_m44", 22, 10, 0 }, 165 { "fixup_sparc_l44", 20, 12, 0 }, 166 { "fixup_sparc_hh", 10, 22, 0 }, 167 { "fixup_sparc_hm", 22, 10, 0 }, 168 { "fixup_sparc_lm", 10, 22, 0 }, 169 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 170 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel }, 171 { "fixup_sparc_got22", 10, 22, 0 }, 172 { "fixup_sparc_got10", 22, 10, 0 }, 173 { "fixup_sparc_got13", 19, 13, 0 }, 174 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 175 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 }, 176 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 }, 177 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 178 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 179 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 }, 180 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 }, 181 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 182 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 183 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 }, 184 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 }, 185 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 186 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 }, 187 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 }, 188 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 189 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 190 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 191 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 192 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 193 }; 194 195 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { 196 // name offset bits flags 197 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 198 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 199 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 200 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, 201 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, 202 { "fixup_sparc_13", 0, 13, 0 }, 203 { "fixup_sparc_hi22", 0, 22, 0 }, 204 { "fixup_sparc_lo10", 0, 10, 0 }, 205 { "fixup_sparc_h44", 0, 22, 0 }, 206 { "fixup_sparc_m44", 0, 10, 0 }, 207 { "fixup_sparc_l44", 0, 12, 0 }, 208 { "fixup_sparc_hh", 0, 22, 0 }, 209 { "fixup_sparc_hm", 0, 10, 0 }, 210 { "fixup_sparc_lm", 0, 22, 0 }, 211 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 212 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 213 { "fixup_sparc_got22", 0, 22, 0 }, 214 { "fixup_sparc_got10", 0, 10, 0 }, 215 { "fixup_sparc_got13", 0, 13, 0 }, 216 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 217 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, 218 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, 219 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 220 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 221 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, 222 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, 223 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 224 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 225 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, 226 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, 227 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 228 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, 229 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, 230 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 231 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 232 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 233 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 234 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 235 }; 236 237 // Fixup kinds from .reloc directive are like R_SPARC_NONE. They do 238 // not require any extra processing. 239 if (Kind >= FirstLiteralRelocationKind) 240 return MCAsmBackend::getFixupKindInfo(FK_NONE); 241 242 if (Kind < FirstTargetFixupKind) 243 return MCAsmBackend::getFixupKindInfo(Kind); 244 245 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 246 "Invalid kind!"); 247 if (Endian == support::little) 248 return InfosLE[Kind - FirstTargetFixupKind]; 249 250 return InfosBE[Kind - FirstTargetFixupKind]; 251 } 252 253 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 254 const MCValue &Target) override { 255 if (Fixup.getKind() >= FirstLiteralRelocationKind) 256 return true; 257 switch ((Sparc::Fixups)Fixup.getKind()) { 258 default: 259 return false; 260 case Sparc::fixup_sparc_wplt30: 261 if (Target.getSymA()->getSymbol().isTemporary()) 262 return false; 263 LLVM_FALLTHROUGH; 264 case Sparc::fixup_sparc_tls_gd_hi22: 265 case Sparc::fixup_sparc_tls_gd_lo10: 266 case Sparc::fixup_sparc_tls_gd_add: 267 case Sparc::fixup_sparc_tls_gd_call: 268 case Sparc::fixup_sparc_tls_ldm_hi22: 269 case Sparc::fixup_sparc_tls_ldm_lo10: 270 case Sparc::fixup_sparc_tls_ldm_add: 271 case Sparc::fixup_sparc_tls_ldm_call: 272 case Sparc::fixup_sparc_tls_ldo_hix22: 273 case Sparc::fixup_sparc_tls_ldo_lox10: 274 case Sparc::fixup_sparc_tls_ldo_add: 275 case Sparc::fixup_sparc_tls_ie_hi22: 276 case Sparc::fixup_sparc_tls_ie_lo10: 277 case Sparc::fixup_sparc_tls_ie_ld: 278 case Sparc::fixup_sparc_tls_ie_ldx: 279 case Sparc::fixup_sparc_tls_ie_add: 280 case Sparc::fixup_sparc_tls_le_hix22: 281 case Sparc::fixup_sparc_tls_le_lox10: 282 return true; 283 } 284 } 285 286 /// fixupNeedsRelaxation - Target specific predicate for whether a given 287 /// fixup requires the associated instruction to be relaxed. 288 bool fixupNeedsRelaxation(const MCFixup &Fixup, 289 uint64_t Value, 290 const MCRelaxableFragment *DF, 291 const MCAsmLayout &Layout) const override { 292 // FIXME. 293 llvm_unreachable("fixupNeedsRelaxation() unimplemented"); 294 return false; 295 } 296 void relaxInstruction(MCInst &Inst, 297 const MCSubtargetInfo &STI) const override { 298 // FIXME. 299 llvm_unreachable("relaxInstruction() unimplemented"); 300 } 301 302 bool writeNopData(raw_ostream &OS, uint64_t Count, 303 const MCSubtargetInfo *STI) const override { 304 // Cannot emit NOP with size not multiple of 32 bits. 305 if (Count % 4 != 0) 306 return false; 307 308 uint64_t NumNops = Count / 4; 309 for (uint64_t i = 0; i != NumNops; ++i) 310 support::endian::write<uint32_t>(OS, 0x01000000, Endian); 311 312 return true; 313 } 314 }; 315 316 class ELFSparcAsmBackend : public SparcAsmBackend { 317 Triple::OSType OSType; 318 public: 319 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) : 320 SparcAsmBackend(T), OSType(OSType) { } 321 322 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 323 const MCValue &Target, MutableArrayRef<char> Data, 324 uint64_t Value, bool IsResolved, 325 const MCSubtargetInfo *STI) const override { 326 327 if (Fixup.getKind() >= FirstLiteralRelocationKind) 328 return; 329 Value = adjustFixupValue(Fixup.getKind(), Value); 330 if (!Value) return; // Doesn't change encoding. 331 332 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 333 unsigned Offset = Fixup.getOffset(); 334 // For each byte of the fragment that the fixup touches, mask in the bits 335 // from the fixup value. The Value has been "split up" into the 336 // appropriate bitfields above. 337 for (unsigned i = 0; i != NumBytes; ++i) { 338 unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i; 339 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 340 } 341 } 342 343 std::unique_ptr<MCObjectTargetWriter> 344 createObjectTargetWriter() const override { 345 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); 346 return createSparcELFObjectWriter(Is64Bit, OSABI); 347 } 348 }; 349 350 } // end anonymous namespace 351 352 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, 353 const MCSubtargetInfo &STI, 354 const MCRegisterInfo &MRI, 355 const MCTargetOptions &Options) { 356 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); 357 } 358