1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 15 16 #include "MCTargetDesc/RISCVBaseInfo.h" 17 #include "RISCVFrameLowering.h" 18 #include "RISCVISelLowering.h" 19 #include "RISCVInstrInfo.h" 20 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 23 #include "llvm/CodeGen/RegisterBankInfo.h" 24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 25 #include "llvm/CodeGen/TargetSubtargetInfo.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/Target/TargetMachine.h" 28 29 #define GET_SUBTARGETINFO_HEADER 30 #include "RISCVGenSubtargetInfo.inc" 31 32 namespace llvm { 33 class StringRef; 34 35 class RISCVSubtarget : public RISCVGenSubtargetInfo { 36 public: 37 enum RISCVProcFamilyEnum : uint8_t { 38 Others, 39 SiFive7, 40 }; 41 42 private: 43 virtual void anchor(); 44 45 RISCVProcFamilyEnum RISCVProcFamily = Others; 46 47 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 48 bool ATTRIBUTE = DEFAULT; 49 #include "RISCVGenSubtargetInfo.inc" 50 51 unsigned XLen = 32; 52 unsigned ZvlLen = 0; 53 MVT XLenVT = MVT::i32; 54 unsigned RVVVectorBitsMin; 55 unsigned RVVVectorBitsMax; 56 uint8_t MaxInterleaveFactor = 2; 57 RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; 58 std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister; 59 RISCVFrameLowering FrameLowering; 60 RISCVInstrInfo InstrInfo; 61 RISCVRegisterInfo RegInfo; 62 RISCVTargetLowering TLInfo; 63 SelectionDAGTargetInfo TSInfo; 64 65 /// Initializes using the passed in CPU and feature strings so that we can 66 /// use initializer lists for subtarget initialization. 67 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT, 68 StringRef CPU, 69 StringRef TuneCPU, 70 StringRef FS, 71 StringRef ABIName); 72 73 public: 74 // Initializes the data members to match that of the specified triple. 75 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, 76 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, 77 unsigned RVVVectorLMULMax, const TargetMachine &TM); 78 79 // Parses features string setting specified subtarget options. The 80 // definition of this function is auto-generated by tblgen. 81 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 82 83 const RISCVFrameLowering *getFrameLowering() const override { 84 return &FrameLowering; 85 } 86 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } 87 const RISCVRegisterInfo *getRegisterInfo() const override { 88 return &RegInfo; 89 } 90 const RISCVTargetLowering *getTargetLowering() const override { 91 return &TLInfo; 92 } 93 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 94 return &TSInfo; 95 } 96 bool enableMachineScheduler() const override { return true; } 97 98 /// Returns RISCV processor family. 99 /// Avoid this function! CPU specifics should be kept local to this class 100 /// and preferably modeled with SubtargetFeatures or properties in 101 /// initializeProperties(). 102 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } 103 104 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 105 bool GETTER() const { return ATTRIBUTE; } 106 #include "RISCVGenSubtargetInfo.inc" 107 108 bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; } 109 bool hasStdExtZvl() const { return ZvlLen != 0; } 110 bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; } 111 bool is64Bit() const { return HasRV64; } 112 MVT getXLenVT() const { return XLenVT; } 113 unsigned getXLen() const { return XLen; } 114 unsigned getFLen() const { 115 if (HasStdExtD) 116 return 64; 117 118 if (HasStdExtF) 119 return 32; 120 121 return 0; 122 } 123 unsigned getELEN() const { 124 assert(hasVInstructions() && "Expected V extension"); 125 return hasVInstructionsI64() ? 64 : 32; 126 } 127 unsigned getRealMinVLen() const { 128 unsigned VLen = getMinRVVVectorSizeInBits(); 129 return VLen == 0 ? ZvlLen : VLen; 130 } 131 unsigned getRealMaxVLen() const { 132 unsigned VLen = getMaxRVVVectorSizeInBits(); 133 return VLen == 0 ? 65536 : VLen; 134 } 135 RISCVABI::ABI getTargetABI() const { return TargetABI; } 136 bool isRegisterReservedByUser(Register i) const { 137 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); 138 return UserReservedRegister[i]; 139 } 140 141 bool hasMacroFusion() const { return hasLUIADDIFusion(); } 142 143 // Vector codegen related methods. 144 bool hasVInstructions() const { return HasStdExtZve32x; } 145 bool hasVInstructionsI64() const { return HasStdExtZve64x; } 146 bool hasVInstructionsF16() const { 147 return HasStdExtZvfh && hasStdExtZfhOrZfhmin(); 148 } 149 // FIXME: Consider Zfinx in the future 150 bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; } 151 // FIXME: Consider Zdinx in the future 152 bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } 153 // F16 and F64 both require F32. 154 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } 155 unsigned getMaxInterleaveFactor() const { 156 return hasVInstructions() ? MaxInterleaveFactor : 1; 157 } 158 159 protected: 160 // GlobalISel related APIs. 161 std::unique_ptr<CallLowering> CallLoweringInfo; 162 std::unique_ptr<InstructionSelector> InstSelector; 163 std::unique_ptr<LegalizerInfo> Legalizer; 164 std::unique_ptr<RegisterBankInfo> RegBankInfo; 165 166 // Return the known range for the bit length of RVV data registers as set 167 // at the command line. A value of 0 means nothing is known about that particular 168 // limit beyond what's implied by the architecture. 169 // NOTE: Please use getRealMinVLen and getRealMaxVLen instead! 170 unsigned getMaxRVVVectorSizeInBits() const; 171 unsigned getMinRVVVectorSizeInBits() const; 172 173 public: 174 const CallLowering *getCallLowering() const override; 175 InstructionSelector *getInstructionSelector() const override; 176 const LegalizerInfo *getLegalizerInfo() const override; 177 const RegisterBankInfo *getRegBankInfo() const override; 178 179 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); } 180 181 bool useConstantPoolForLargeInts() const; 182 183 // Maximum cost used for building integers, integers will be put into constant 184 // pool if exceeded. 185 unsigned getMaxBuildIntsCost() const; 186 187 unsigned getMaxLMULForFixedLengthVectors() const; 188 bool useRVVForFixedLengthVectors() const; 189 190 bool enableSubRegLiveness() const override; 191 192 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> 193 &Mutations) const override; 194 }; 195 } // End llvm namespace 196 197 #endif 198