1//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard Integer 10// Conditional operations extension (Zicond). 11// This version is still experimental as the 'Zicond' extension hasn't been 12// ratified yet. It is based on v1.0-rc1 of the specification. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// RISC-V specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def riscv_czero_eqz : SDNode<"RISCVISD::CZERO_EQZ", SDTIntBinOp>; 21def riscv_czero_nez : SDNode<"RISCVISD::CZERO_NEZ", SDTIntBinOp>; 22 23//===----------------------------------------------------------------------===// 24// Instructions 25//===----------------------------------------------------------------------===// 26 27let Predicates = [HasStdExtZicond] in { 28def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">, 29 Sched<[WriteIALU, ReadIALU, ReadIALU]>; 30def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">, 31 Sched<[WriteIALU, ReadIALU, ReadIALU]>; 32} // Predicates = [HasStdExtZicond] 33 34//===----------------------------------------------------------------------===// 35// Pseudo-instructions and codegen patterns 36//===----------------------------------------------------------------------===// 37 38let Predicates = [HasStdExtZicond] in { 39def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)), 40 (CZERO_EQZ GPR:$rs1, GPR:$rc)>; 41def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)), 42 (CZERO_NEZ GPR:$rs1, GPR:$rc)>; 43} // Predicates = [HasStdExtZicond] 44